CN112510043A - Deep ultraviolet LED integrated chip and preparation method thereof - Google Patents

Abstract

The invention belongs to the field of deep ultraviolet LED chips and discloses a deep ultraviolet LED integrated chip and a preparation method thereof, wherein the chip takes a single wafer substrate epitaxially grown with an AlGaN epitaxial wafer as a base and is integrated with at least 2 PN junction units; each PN junction unit is used as a deep ultraviolet LED light emitting unit, and can realize deep ultraviolet light emission with the light emitting wavelength lambda less than 280 nm; each PN junction unit is provided with an N electrode pad and a P electrode pad, and the PN junction units are in parallel connection and/or series connection with each other. The invention improves the chip integration design and the corresponding preparation method, and the like, and integrates a plurality of light-emitting units in series and/or in parallel on a single wafer substrate, thereby providing another alternative way for the module packaging in the prior art. And the packaging material and labor cost corresponding to each light-emitting unit can be reduced, and the size of the device can be greatly reduced, so that the device is suitable for integration of various deep ultraviolet LED flip chips.

Description

A kind of deep ultraviolet LED integrated chip and preparation method thereof

technical field

The invention belongs to the field of deep ultraviolet LED chips, and more particularly, relates to a deep ultraviolet LED integrated chip and a preparation method thereof.

Background technique

AlGaN-based deep UV LEDs (λ<280 nm) have attracted the attention of many scientists due to their wide range of applications, such as disinfection, air and water purification, biochemical detection, and optical communication. With the outbreak of the new coronavirus pneumonia, the market of deep ultraviolet sterilization and disinfection products is becoming more and more popular. However, the low optical power of deep ultraviolet LEDs still cannot meet the requirements of current high-power sterilization and disinfection applications. This is mainly because The material defect density of deep ultraviolet LED is too high, and the technical threshold is very high. At present, it is difficult to make a high-power single chip. As a result, high-power sterilization products must use a module composed of multiple lamp beads to achieve the expected sterilization and disinfection. Effect.

SUMMARY OF THE INVENTION

In view of the above defects or improvement needs of the prior art, the purpose of the present invention is to provide a deep ultraviolet LED integrated chip and a preparation method thereof, wherein by improving the integrated design of the chip and the corresponding preparation method, a single wafer can be The integration of several light-emitting units in series and/or parallel is performed on the substrate (that is, the integrated design of multiple PN junction units located on the same substrate is performed through a parallel relationship and/or a series relationship), which provides a module package in the prior art. Another alternative approach is proposed, and the cost of packaging materials and labor corresponding to each light-emitting unit can be reduced, and the volume of the device can be greatly reduced, which is suitable for the integration of various deep ultraviolet LED flip chips.

In order to achieve the above purpose, according to one aspect of the present invention, a deep ultraviolet LED integrated chip is provided, characterized in that the chip is based on a single wafer substrate epitaxially grown with AlGaN epitaxial wafers, and is integrated with at least 2 PN junction units; each PN junction unit, as a deep ultraviolet LED light-emitting unit, has an independent flip-chip pad, which can realize deep ultraviolet light emission with a light emission wavelength of λ<280nm; between any two adjacent PN junction units Through deep groove electrical isolation, the depth of the deep groove reaches the contact interface between the epitaxial wafer and the wafer substrate;

The chip as a whole has a total P-pole flip-chip pad and a total N-pole flip-chip pad, and each PN junction unit also has an independent N electrode pad and P electrode pad, and these PN junction units form a parallel relationship with each other and/or series relationship, the power supply to these PN junction units can be realized through the total P-pole flip-chip pad and the total N-pole flip-chip pad; wherein,

When two PN junction units satisfy that the N electrode pad of one PN junction unit is connected to the P electrode pad of another PN junction unit at the same potential, then the two PN junction units are in a series relationship, and the chip has corresponding to the series connection. the way the relationship is integrated;

When two PN junction units satisfy the condition that the N electrode pad of one PN junction unit is connected to the N electrode pad of another PN junction unit at the same potential, or the P electrode pad of one PN junction unit is connected to the other PN junction unit If the P electrode pads are connected at the same potential, the two PN junction units are in a parallel relationship, and the chip has an integration mode corresponding to the parallel relationship.

As a further preference of the present invention, the chip has an integration mode corresponding to a series relationship and a parallel relationship at the same time, the chip integrates m×n PN junction units, and correspondingly forms n parallel branches, each parallel branch is connected by m PN junction units are formed in a series relationship; wherein, m and n are both integers greater than or equal to 2;

Preferably, the total P-pole flip-chip pads and the total N-pole flip-chip pads on the integrated chip are respectively located at the connection intersection of the n parallel branches.

As a further preference of the present invention, the N electrode pad of the one PN junction unit is connected to the P electrode pad of the other PN junction unit in an equipotential connection, specifically connected by a conductive metal material, correspondingly forming an electrical connection metal layer;

The N electrode pad of the one PN junction unit is equipotentially connected to the N electrode pad of the other PN junction unit, and is specifically connected through a conductive metal material to form an electrical connection metal layer correspondingly;

The P electrode pad of one PN junction unit is equipotentially connected to the P electrode pad of another PN junction unit, specifically connected through a conductive metal material, correspondingly forming an electrical connection metal layer;

Furthermore, 2 of these electrical connection metal layers are used as the overall P-pole flip-chip pad and the overall N-pole flip-chip pad.

As a further preference of the present invention, the electrical connection metal layer is located outside the AlGaN epitaxial wafer, and is connected to the AlGaN epitaxial wafer through a passivation material; the passivation material is selected from SiO ₂ , Si ₃ N ₄ , HfO _2. A Brah mirror DBR structure, wherein the Brah mirror DBR structure is obtained by periodically arranging SiO ₂ and Ti ₂ O ₅ .

As a further preference of the present invention, the N electrode terminal and the P electrode terminal of any one of the PN junction units are located in the AlGaN epitaxial wafer, and are formed by etching the AlGaN material and evaporating the electrode material.

As a further preference of the present invention, the N electrode end and the P electrode end of any one of the PN junction units are subjected to electrode thickening treatment, so that these N electrode ends and P electrode ends protrude from the plane where the upper surface of the AlGaN epitaxial wafer is located, and It is connected to the PAD electrode above the AlGaN epitaxial wafer, and the PAD electrode is the pad electrode.

As a further preference of the present invention, a passivation material is filled between the adjacent PAD electrodes; the top of any PAD electrode is connected to the electrical connection metal layer; the passivation material is selected from SiO ₂ , Si ₃ N ₄ , HfO ₂ , and Brahma mirror DBR structure, wherein the Brah mirror DBR structure is obtained by periodically arranging SiO ₂ and Ti ₂ O ₅ .

As a further preference of the present invention, the wafer substrate is a sapphire wafer or an AlN single crystal wafer.

According to another aspect of the present invention, the present invention provides a method for preparing the above-mentioned deep ultraviolet LED integrated chip, which is characterized by comprising the following steps:

(S1) using a clean wafer substrate epitaxially grown with an AlGaN deep ultraviolet epitaxial wafer as a base, and forming the AlGaN deep ultraviolet epitaxial wafer in the target area of the N electrode end and P electrode end in the AlGaN deep ultraviolet epitaxial wafer; then, electrode thickening treatment is performed on these N electrode end and P electrode end, so that the N electrode end and the P electrode end protrude above the AlGaN depth The plane where the upper surface of the UV epitaxial wafer is located;

(S2) forming deep grooves through photolithography and etching processes in the target area of the substrate, and the depth of the deep grooves reaches the contact interface between the deep ultraviolet epitaxial wafer and the wafer substrate; then, deposition passivation materials, so that these passivation materials fill the deep grooves and cover the deep ultraviolet epitaxial wafer to form a passivation layer; then, perform photolithography and etching in the target area of the passivation layer to form openings, and then open the holes Photolithography is performed on the position, and then metal evaporation is performed to form a PAD electrode, that is, a pad electrode, so that a single PN junction functional unit is completed;

(S3) Next, passivation materials are deposited for the second time, so that these passivation materials cover the substrate to form a second passivation layer; then, photolithography and etching are performed on the target area of the second passivation layer to form openings hole, then photolithography at the opening position, and then metal evaporation to form an electrical connection metal layer, thus completing the preparation of the deep ultraviolet LED integrated chip; two of these electrical connection metal layers are used as the total P-pole flip-chip welding pad and total N-pole flip-chip pad.

Through the above technical solutions conceived by the present invention, in order to promote and promote the wide application of the deep ultraviolet LED light source, the present invention adopts the chip integration technology in the front-end process of the deep ultraviolet LED, and can produce various combinations on COW (chip on wafer) The integrated chip in the form of the integrated chip can achieve the effect of the module. The invention can effectively reduce production material cost, labor cost and time cost. Taking two parallel and two series as an example, the volume of the device is only about 30% of the original module, and it can even be made smaller. The invention is applied in the field of preparation and packaging of LEDs, especially deep-ultraviolet LED chips.

The present invention designs an integrated chip in which several light-emitting units are connected in series and/or in parallel on a single wafer substrate, which is equivalent to adding two lithography processes (two lithography processes) on the basis of the single-chip COW preparation process. The photolithography process is respectively used to cooperate with the deposition of the second deposition layer and the vapor deposition of the electrically connected metal layer), a passivation layer process, and an electrode connection process to realize the integration of the chip, which is equivalent to the existing technology module. technical effect.

The present invention is applicable to the integration of multiple modes, such as two-string two-parallel, three-string two-parallel, three-string three-parallel, four-string four-parallel, four-string two-parallel, etc. integration of a light-emitting unit). Taking two strings and two parallels as an example (that is, m=2, n=2), if a conventional module in the prior art is used, four single-core lamp beads are formed into a module (that is, each single light-emitting The chips of the unit are packaged into lamp beads, and then each lamp bead is assembled to form a module); while using the present invention, only two strings and two integrated chips are packaged into lamp beads, and the cost of packaging materials and labor is only the mold bead. 1/4 of the group (that is, 1/(m×n), other cases of m×n are also applicable), and the volume of the device can be greatly reduced at the same time.

In addition, since the chip integration method of the present invention is very flexible, and due to the non-uniformity of the deep ultraviolet epitaxial wafer, the required integration mode can be flexibly selected according to the COW test data, thereby effectively reducing the defect rate. That is to say, because the design of the integrated chip in the present invention is to perform integrated production after the completion of a single PN junction device, this design can test the optoelectronic parameters after the completion of the single PN junction process, through the distribution of test data. and yield to flexibly choose the integration method.

In conclusion, the integrated chip design and the integration method of the present invention are suitable for the integration of various deep ultraviolet LED flip chips. The chip integration method of the invention is flexible, reduces the volume, reduces the packaging cost, can better integrate and assemble at the end of the deep ultraviolet sterilization and disinfection application product, is suitable for large-scale production, and has a very broad application prospect in the deep ultraviolet LED module packaging. .

Description of drawings

FIG. 1 is a schematic structural diagram of a deep ultraviolet LED chip integration according to an embodiment of the present invention, and the structure shown in the figure corresponds to two series and two parallel integrated chips.

FIG. 2 is a flow chart of an integrated fabrication process of a deep ultraviolet LED chip according to an embodiment of the present invention.

The meanings of the reference numerals in Fig. 1 are as follows: 1- Passivation layer opening, 2- Two-chip P electrode connection and P-pole flip-chip pad of the integrated chip, 3- Passivation layer SiO ₂ , 4- Two-chip PN The electrodes are connected in series, and the 5-chip N electrode is connected and the N-pole flip-chip pad of the integrated chip.

Detailed ways

In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention, but not to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

In general, as shown in FIG. 2, the main material of the deep ultraviolet LED chip integration preparation method of the present invention is deep ultraviolet epitaxial material, and the main preparation process includes chemical cleaning, 9 photolithography processes, dry etching, wet etching, etc. Etching, electron beam evaporation, metal alloys, deposition of silicon dioxide passivation layers. Specifically include the following steps:

(1) Cleaning the AlGaN-based deep ultraviolet epitaxial wafer, the material is an AlGaN-based deep ultraviolet epitaxial wafer grown on a sapphire substrate, and the size is a wafer with a diameter of 5.08 cm; the deep ultraviolet epitaxial wafer satisfies the conventional definition, that is, on the wafer AlN buffer layer, AlN/AlGaN superlattice, N-AlGaN, active area AlGaN multiple quantum well, P-AlGaN, P-GaN layer are epitaxially grown on the substrate (such as sapphire, AlN, GaN substrate). Directly use commercially available products, or prepare by yourself with reference to methods known in the prior art;

(2) mesa lithography and etching, etching to N-AlGaN, in order to make N electrode;

(3) Preparation of N-electrode terminals, namely: N-electrode lithography, N-region metal electrode evaporation and N-electrode alloying, and the N-electrode alloying process is to form an ohmic contact at the metal-semiconductor interface, thereby reducing the chip voltage;

(4) Preparation of P-electrode terminals, namely: P-electrode lithography, P-region metal electrode evaporation and P-electrode alloying, and the P-electrode alloying process is also to form an ohmic contact at the metal-semiconductor interface, thereby reducing the chip voltage;

(5) Thickened electrode lithography and metal evaporation in N and P regions, in order to have better current expansion and heat dissipation for N-P electrodes;

(6) Deep groove lithography and deep groove etching, etch through the epitaxial layer material to prevent leakage between chips

(7) deposition of the first passivation layer and hole etching;

(8) Preparation of pad electrodes, namely: PAD lithography and electrode evaporation of a single PN junction N-P electrode;

(9) Secondary passivation layer deposition and hole etching;

(10) The total pad and the chip electrode are connected by photolithography and metal electrode evaporation to complete the electrode connection between the total flip-chip pad and the integrated chip, as shown in FIG. 1 . Figure 1 shows a chip that integrates two series and two parallels. Of course, it can also be other integration methods of m series and n parallel, or even an integration method of only m series or only n parallel (where m and n are both is an integer greater than or equal to 2).

The following are specific examples:

Example 1

This embodiment includes the following steps:

(1) Cleaning of AlGaN epitaxial material: Mix 98% concentrated sulfuric acid and 30% hydrogen peroxide solution by mass respectively, the volume ratio is about 5:1, and the temperature is about 90 °C for 10 minutes;

(2) mesa lithography: spin coating photoresist RD-2900, spin coating thickness is about 2.8um, soft bake 120℃ for 70s; cover photolithography, 365nm UV light source projection exposure, exposure time 5.5s, AZ400K: H ₂ O =4:1, developing for 90s, hardened film at 120℃ for 5min; Mesa dry etching, plasma etching AlGaN material in a mixed atmosphere of Cl ₂ and BCl ₃ for 570s; degumming solution at 85℃ for degumming and cleaning.

(3) N-electrode lithography, N metal evaporation and N-electrode RTA annealing: spin coating photoresist RD-NL700 (85CP), spin coating thickness of about 4.5um, soft bake at 110°C for 100s; cover photolithography, 365nm UV light Light source projection exposure, exposure time 3.5s, AZ400K:H ₂ O=4:1 development for 70s, hot plate at 120°C for 2min, development for 80s, oxygen plasma glue for 200W for 3min, drying by drying machine, and evaporation by electron beam Metal Ti/Al/Ti/Au, the blue film is peeled off, and the degumming solution is degummed and cleaned at 85°C. N electrode rapid alloy annealing, annealing temperature 950 ℃-1min.

(4) P electrode lithography, P metal evaporation and P electrode RTA annealing: spin coating photoresist RD-NL700 (85CP), spin coating thickness of about 4.5um, soft bake at 110°C for 100s; cover photolithography, 365nm UV Light source projection exposure, exposure time 3.5s, AZ400K:H ₂ O=4:1 development for 70s, hot plate at 120°C for 2min, development for 80s, oxygen plasma glue for 200W for 3min, drying by drying machine, and evaporation by electron beam Metal Ni/Au, the blue film is peeled off, and the degumming solution is degummed and cleaned at 85°C. P electrode rapid alloy annealing, annealing temperature 550 ℃-3min.

(5) Thickened electrode NP-THICK lithography and metal evaporation: spin-coating photoresist RD-NL700 (85CP), spin-coating thickness is about 4.5um, soft-bake 110℃ for 100s; cover photolithography, 365nm UV light source projection Exposure, exposure time 3.5s, AZ400K: H ₂ O = 4:1, developing for 70s, hardening film at 120℃ for 2min, developing for 80s, applying oxygen plasma glue for 200W for 3min, drying by drying machine, and evaporating metal Cr with electron beam /Al/Ti/Pt/Au/Ti, the blue film was peeled off, and the degumming solution was degummed and cleaned at 85°C.

(6) Deep groove lithography and deep groove etching: spin coating photoresist RD-6100, spin coating thickness of about 12um, soft bake 120℃ for 150s; cover photolithography, 365nm UV light source projection exposure, exposure time 10s, AZ400K : H ₂ O=4:1, developing for 200s, hardened film at 120℃ for 5min; deep groove dry etching, plasma etching AlGaN material in a mixed atmosphere of Cl ₂ and BCl ₃ , time 1260s; degumming solution 85 ℃ to remove glue and wash.

旋涂光刻胶RD-6100，旋涂厚度约12um，软烘120℃150s；覆盖光刻板，365nm的紫外光源投影曝光，曝光时间10s，AZ400K：H₂O＝4:1显影200s，坚膜120℃的热板5min；SiO₂干法刻蚀，在CF₄和BCl₃的混合气氛中等离子体蚀刻SiO₂材料，时间1600s；去胶液85℃去胶清洗。(7) PECVD deposition passivation layer SiO ₂ and passivation layer opening lithography and etching: PECVD deposition passivation layer SiO ₂ thickness is

Spin coating photoresist RD-6100, spin coating thickness of about 12um, soft bake at 120℃ for 150s; cover photolithography, projection exposure with 365nm UV light source, exposure time 10s, AZ400K: H ₂ O=4:1 development for 200s, hard film Hot plate at 120 °C for ₅ min; _SiO2 dry etching, plasma etching _SiO2 material in a mixed atmosphere of CF4 and _BCl3 for 1600s; degumming solution at 85℃ for degumming cleaning.

(8) PAD lithography and PAD electrode evaporation: spin coating photoresist RD-NL700 (85CP), spin coating thickness is about 4.5um, soft bake 110℃ for 100s; cover photoresist, 365nm UV light source projection exposure, exposure time 3.5s, AZ400K: H ₂ O=4:1 development for 70s, hot plate at 120°C for 2min, development for 80s, oxygen plasma gluing at 200W for 3min, drying in a dryer, and metal Cr/Al/Ti evaporated by electron beam /Pt/Au/Ti, the blue film is peeled off, and the degumming solution is degummed and cleaned at 85 °C, that is, the COW of the single core is completed.

旋涂光刻胶RD-6100，旋涂厚度约12um，软烘120℃150s；覆盖光刻板，365nm的紫外光源投影曝光，曝光时间10s，AZ400K：H₂O＝4:1显影200s，坚膜120℃的热板5min；SiO₂干法刻蚀，在CF₄和BCl₃的混合气氛中等离子体蚀刻SiO₂材料，时间1600s；去胶液85℃去胶清洗。(9) The second PECVD deposition of passivation layer SiO ₂ and passivation layer opening lithography and etching: The thickness of PECVD deposition passivation layer SiO ₂ is

Spin coating photoresist RD-6100, spin coating thickness of about 12um, soft bake at 120℃ for 150s; cover photolithography, projection exposure with 365nm UV light source, exposure time 10s, AZ400K: H ₂ O=4:1 development for 200s, hard film Hot plate at 120 °C for ₅ min; _SiO2 dry etching, plasma etching _SiO2 material in a mixed atmosphere of CF4 and _BCl3 for 1600s; degumming solution at 85℃ for degumming cleaning.

(10) Integrated chip electrode connection lithography and electrode evaporation: spin-coating photoresist RD-NL700 (85CP), spin-coating thickness of about 4.5um, soft-bake at 110°C for 100s; Exposure time 3.5s, AZ400K: H ₂ O=4:1, developing for 70s, hardening film at 120℃ for 2min, developing for 80s, applying glue by oxygen plasma for 200W for 3min, drying by drying machine, and evaporating metal Cr/Al by electron beam /Ti/Pt/Ti/Pt/Au, the blue film is peeled off, and the degumming solution is degummed and cleaned at 85°C, that is, the COW of the integrated chip is completed.

In the subsequent packaging process, the lamp bead packaged by two strings and two integrated chips can replace the traditional module composed of four single-core lamp beads, but the packaging material and labor cost are only 1/4 of the module. The cycle of module production is greatly shortened, and the volume of the device can be greatly reduced.

Various reagents used in the above examples can be directly purchased from the market. In addition, the specific parameters and condition settings in the above embodiments are only examples, and other parameters and condition settings may also be used based on the present invention, which is not exhaustive.

Those skilled in the art can easily understand that the above are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present invention, etc., All should be included within the protection scope of the present invention.

Claims (9)

1. A deep ultraviolet LED integrated chip is characterized in that the chip takes a single wafer substrate epitaxially grown with an AlGaN epitaxial wafer as a base and is integrated with at least 2 PN junction units; each PN junction unit is used as a deep ultraviolet LED light emitting unit, each PN junction unit is provided with an independent flip bonding pad, and the deep ultraviolet light emitting with the light emitting wavelength lambda less than 280nm can be realized; any 2 adjacent PN junction units are electrically isolated through a deep groove, and the depth of the deep groove reaches the contact interface of the epitaxial wafer and the wafer substrate;

the whole chip is provided with a total P pole flip bonding pad and a total N pole flip bonding pad, each PN junction unit is also provided with an independent N electrode bonding pad and an independent P electrode bonding pad, the PN junction units form a parallel connection relation and/or a series connection relation, and power supply to the PN junction units can be realized through the total P pole flip bonding pad and the total N pole flip bonding pad; wherein,

when a certain 2 PN junction units meet the condition that an N electrode bonding pad of one PN junction unit is connected with a P electrode bonding pad of another PN junction unit in an equipotential manner, the 2 PN junction units are in a series connection relationship, and the chip has an integration mode corresponding to the series connection relationship;

when 2 PN junction units meet the condition that an N electrode bonding pad of one PN junction unit is connected with an N electrode bonding pad of another PN junction unit in an equipotential manner or a P electrode bonding pad of one PN junction unit is connected with a P electrode bonding pad of another PN junction unit in an equipotential manner, the 2 PN junction units are in a parallel connection relationship, and the chip has an integration mode corresponding to the parallel connection relationship.

2. The deep ultraviolet LED integrated chip of claim 1, wherein the chip has an integration corresponding to both a series connection relationship and a parallel connection relationship, the chip is integrated with m × n PN junction units, n parallel branches are correspondingly formed, and each parallel branch is formed by m PN junction units through the series connection relationship; wherein m and n are integers more than or equal to 2;

preferably, the total P-pole flip pad and the total N-pole flip pad on the integrated chip are respectively located at the connection intersection of the N parallel branches.

3. The deep ultraviolet LED integrated chip of claim 1, wherein the N electrode pad of one PN junction unit is connected to the P electrode pad of another PN junction unit at an equipotential, specifically by a conductive metal material, to correspondingly form an electrically connected metal layer;

the N electrode bonding pad of one PN junction unit is connected with the N electrode bonding pad of the other PN junction unit in an equipotential manner, specifically, the N electrode bonding pads are connected through a conductive metal material to correspondingly form an electric connection metal layer;

the P electrode bonding pad of one PN junction unit is connected with the P electrode bonding pad of the other PN junction unit in an equipotential manner, specifically, the P electrode bonding pad of one PN junction unit is connected with the P electrode bonding pad of the other PN junction unit through a conductive metal material, and an electric connection metal layer is correspondingly formed;

further, 2 of these electrical connection metal layers are as the total P-pole flip chip pad and the total N-pole flip chip pad.

4. The deep ultraviolet LED integrated chip of claim 1, wherein the electrical connection metal layer is located outside the AlGaN epitaxial wafer and is connected to the AlGaN epitaxial wafer through a passivation material; the passivation material is selected from SiO₂、Si₃N₄、HfO₂A DBR structure of the Bragg reflector, wherein the DBR structure of the Bragg reflector is made of SiO₂And Ti₂O₅And (3) arranging the components periodically.

5. The deep ultraviolet LED integrated chip of claim 1, wherein the N electrode terminal and the P electrode terminal of any one of the PN junction units are both located in the AlGaN epitaxial wafer, and are formed by etching an AlGaN material and evaporating an electrode material.

6. The deep ultraviolet LED integrated chip of claim 1, wherein an N electrode terminal and a P electrode terminal of any one of the PN junction units are subjected to electrode thickening processing, so that the N electrode terminal and the P electrode terminal protrude from a plane where an upper surface of the AlGaN epitaxial wafer is located and are connected to a PAD electrode above the AlGaN epitaxial wafer, where the PAD electrode is a PAD electrode.

7. The deep ultraviolet LED integrated chip of claim 6, wherein a passivation material is filled between adjacent PAD electrodes; the upper part of any PAD electrode is connected with the electric connection metal layer; the passivation material is selected from SiO₂、Si₃N₄、HfO₂A DBR structure of the Bragg reflector, wherein the DBR structure of the Bragg reflector is made of SiO₂And Ti₂O₅And (3) arranging the components periodically.

8. The deep ultraviolet LED integrated chip of claim 1, wherein the wafer substrate is a sapphire wafer or an AlN single crystal wafer.

9. The method for preparing the deep ultraviolet LED integrated chip as claimed in any one of claims 1 to 8, comprising the following steps:

(S1) taking a clean wafer substrate with the AlGaN deep ultraviolet epitaxial wafer epitaxially grown as a substrate, and forming an N electrode end and a P electrode end in the AlGaN deep ultraviolet epitaxial wafer in a target area of the AlGaN deep ultraviolet epitaxial wafer through photoetching, etching and metal evaporation processes; then, carrying out electrode thickening treatment on the N electrode end and the P electrode end to enable the N electrode end and the P electrode end to protrude out of the plane of the upper surface of the AlGaN deep ultraviolet epitaxial wafer;

(S2) forming a deep groove in the target area of the substrate through photoetching and etching processes, wherein the depth of the deep groove reaches the contact interface of the deep ultraviolet epitaxial wafer and the wafer substrate; then, depositing passivation materials, and enabling the passivation materials to fill the deep groove and cover the deep ultraviolet epitaxial wafer to form a passivation layer; then, photoetching and etching are carried out on the target area of the passivation layer to form an opening, photoetching is carried out on the position of the opening, and then metal evaporation is carried out to form a PAD electrode, namely a PAD electrode, so that the manufacturing of the single PN junction functional unit is finished;

(S3) next, depositing a second time of passivation materials so that the passivation materials cover the substrate to form a second passivation layer; then, photoetching and etching are carried out on the target area of the second passivation layer to form an opening, photoetching is carried out on the position of the opening, and then metal evaporation is carried out to form an electric connection metal layer, so that the preparation of the deep ultraviolet LED integrated chip is completed; 2 of these electrically connecting metal layers serve as a total P-pole flip-chip pad and a total N-pole flip-chip pad.

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