CN109524526B - Deep ultraviolet light-emitting diode chip and preparation method thereof - Google Patents
Deep ultraviolet light-emitting diode chip and preparation method thereof Download PDFInfo
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- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
- H01L33/382—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending partially in or entirely through the semiconductor body
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
- H01L33/387—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape with a plurality of electrode regions in direct contact with the semiconductor body and being electrically interconnected by another electrode layer
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- H—ELECTRICITY
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Abstract
The invention relates to a deep ultraviolet light-emitting diode chip which comprises an epitaxial structure and a P-type metal electrode layer positioned on the epitaxial structure, wherein the P-type metal electrode layer is provided with a plurality of holes, the positions of two adjacent layers of holes correspond to each other, the chip also comprises an N-type metal electrode layer and a lead layer, the N-type metal electrode layer comprises a plurality of rows of electrode columns, each row of electrode columns comprises a plurality of sub-electrode columns, the sub-electrode columns are connected in the holes of the N-AlGaN layer one by one, the diameters of the sub-electrode columns are smaller than those of the holes, and the central distances between two adjacent sub-electrode columns are equal.
Description
Technical Field
The invention relates to the field of design and preparation of semiconductor devices, in particular to a deep ultraviolet light emitting diode chip and a preparation method thereof.
Background
The AlGaN-based deep ultraviolet light emitting diode is continuously concerned due to the wide application fields, such as air purification, sterilization, biochemical detection, optical communication and the like, a wafer epitaxially grown on a c-plane sapphire substrate by using a Metal Organic Chemical Vapor Deposition (MOCVD) method has a mesa structure formed by etching the surface of the wafer due to the insulation of the substrate sapphire in the device preparation process, namely, an n-type electrode and a p-type electrode are on the same side, a lateral current spreading problem inevitably exists in the mesa structure, current is concentrated at the mesa edge, donor ionization energy is increased along with the increase of an Al component in an AlGaN material, the mobility of a carrier is reduced, the resistivity of an n-AlGaN layer is higher, the current spreading length on the n side is reduced, the current distribution is more uneven, in other words, the AlGaN-based deep ultraviolet L with a high Al component has a more serious current congestion problem than GaN-based visible light and near ultraviolet L ED, a large amount of current is emitted from a deep ultraviolet light source region, a light source region is generated due to a high-induced thermal radiation-induced thermal degradation, and a large amount of a local thermal carrier radiation of a local thermal degradation of the AlGaN-based ultraviolet light source is reduced due to a high-induced by a high-doped deep ultraviolet light-induced thermal degradation, and a high-induced thermal-induced degradation of a high-induced-emission-induced-emission-induced-emission deep-induced-emission-induced-emission deep-induced-emission-.
Disclosure of Invention
In view of the above, it is necessary to provide a deep ultraviolet light emitting diode chip and a method for manufacturing the same.
A deep ultraviolet light emitting diode chip comprises an epitaxial structure and a P-type metal electrode layer positioned on the epitaxial structure, wherein the epitaxial structure comprises a substrate, an AlN buffer layer, an N-AlGaN layer, a light emitting layer/an electron blocking layer/a P-GaN layer which are sequentially arranged;
the N-AlGaN layer, the light-emitting layer/the electron blocking layer/the P-GaN layer and the P-type metal electrode layer are all provided with a plurality of holes, and the positions of the adjacent two layers of holes are corresponding to each other;
the chip further comprises an N-type metal electrode layer and a lead layer, wherein the N-type metal electrode layer comprises a plurality of rows of electrode columns, each row of electrode columns comprises a plurality of sub-electrode columns, the sub-electrode columns are connected in the holes of the N-AlGaN layer one by one, and the diameters of the sub-electrode columns are smaller than those of the holes;
the center distances between two adjacent sub-electrode columns are equal;
the lead layer comprises a plurality of connecting columns, and the connecting columns penetrate through the P-type metal electrode layer and are connected with the sub-electrode columns one by one.
In one embodiment, the sub-electrode pillars have a height lower than a height of the N-AlGaN layer.
In one embodiment, the N-type metal electrode layer comprises 5 columns of electrode columns, each column of electrode columns comprises 4 sub-electrode columns, and the diameter of each sub-electrode column is 100-110 μm; the center distance between two adjacent holes is 140-155 mu m.
In one embodiment, the lead layer further comprises a plurality of connecting bars connected to the top ends of the connecting columns in each column.
In one embodiment, the metals in the N-type metal electrode layer sequentially comprise Ti/Al/Ti/Au, and the corresponding thicknesses are sequentially 5nm/10nm/5nm/10 nm; the metal of the lead layer comprises Cr and Au, and the total thickness is 300 nm.
In one embodiment, the substrate is a c-plane sapphire substrate, a Ni layer and an Au layer are arranged on the surface of the P-GaN layer, the thickness of the Ni layer is 20nm, and the thickness of the Au layer is 50 nm.
In one embodiment, the edge of the N-AlGaN layer shrinks inwards to form a step with a predetermined thickness, and the predetermined thickness is 600-800 nm.
The invention also provides a preparation method of the deep ultraviolet light-emitting diode chip, which is used for preparing the deep ultraviolet light-emitting diode chip and comprises the following steps:
s10: manufacturing an epitaxial structure: growing an epitaxial structure, and forming a plurality of holes on the epitaxial structure;
s20: manufacturing an N-type metal electrode layer: evaporating an N-type metal electrode layer and stripping to form a plurality of rows of electrode columns, and annealing for a first preset time;
s30: manufacturing a P-type metal electrode layer: evaporating a P-type metal electrode layer, stripping the P-type metal electrode layer to form a plurality of holes corresponding to the holes in the epitaxial structure, and annealing for a second preset time;
s40: manufacturing a lead layer: and evaporating the lead layer and peeling to form a plurality of connecting posts.
In one embodiment, the first predetermined time in the step S20 is 45S, and the annealing temperature is 750 ℃ to 850 ℃; the second preset time in the step S30 is 5min, and the annealing temperature is 500-550 ℃.
In one embodiment, the step S10 further includes masking with photoresist on BCl3And Cl2The step structure is etched on the epitaxial structure by using plasma in the mixed atmosphere.
Compared with the traditional strip-shaped electrode deep ultraviolet L ED, the deep ultraviolet light-emitting diode chip provided by the invention has the advantages that the serial resistance is small, the voltage is reduced, the uniform distribution of current is facilitated, the current congestion effect is reduced, the generation of joule heat is reduced, and the device performance can be greatly improved.
Drawings
Fig. 1 is a schematic structural diagram of a deep ultraviolet light emitting diode chip in an embodiment of the present invention;
FIG. 2 is a schematic diagram of a distribution structure of a metal electrode layer according to an embodiment of the present invention;
FIG. 3 is a flowchart of a method for manufacturing a deep ultraviolet light emitting diode chip according to an embodiment of the present invention;
FIG. 4 is a graph showing a comparison of wall plug efficiency between a deep ultraviolet light emitting diode chip and a reference group (conventional strip) electrode structure chip according to an embodiment of the present invention;
the same reference numbers will be used throughout the drawings to refer to the same or like elements or structures, wherein:
100-epitaxial structure; 110-a substrate; a 120-AlN buffer layer; a 130-N-AlGaN layer; 200-electrode columns; 310-light emitting layer/electron blocking layer/P-GaN layer; a 400-P type metal electrode layer; a 500-lead layer; 510-connecting column; 520-a connecting strip; 600-a silicon dioxide passivation layer; 610-hollowed out holes; 700-pad metal layer; 410-boss.
Detailed Description
To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
An embodiment of the present invention provides a deep ultraviolet light emitting diode chip, as shown in fig. 1 and fig. 2, including an epitaxial structure 100, and a P-type metal electrode layer 400 located on the epitaxial structure 100, where the epitaxial structure 100 includes a substrate 110, an al N buffer layer 120, an N-AlGaN layer 130, and a light emitting layer/electron blocking layer/P-GaN layer 310, which are sequentially disposed, and a silicon dioxide passivation layer 600 and a pad metal layer 700 respectively distributed at each portion of the chip according to design requirements, which are not described herein again. The main structure of the epitaxial structure 100 adopted by the invention specifically comprises a sapphire substrate 110, an AlN buffer layer 120, a high Al component N-AlGaN layer 130 and a light emitting layer/electron blocking layer/P-GaN layer 310, and the invention adopts the high Al component N-AlGaN-based material epitaxial wafer, wherein the mass percentage of the Al component in the N-AlGaN layer 130 is at least 40%, and more preferably, 55% can be adopted.
The N-AlGaN layer 130, the light emitting layer/electron blocking layer/P-GaN layer 310 and the P-type metal electrode layer 400 are all provided with a plurality of holes, and the positions of the adjacent two layers of holes correspond to each other, that is, the holes are provided on the above layers, and the holes of the upper and lower adjacent layers are overlapped and correspond to each other. In addition, the chip further comprises an N-type metal electrode layer and a lead layer 500, wherein the N-type metal electrode layer comprises a plurality of rows of electrode pillars 200, each row of electrode pillars 200 comprises a plurality of sub-electrode pillars, the sub-electrode pillars are connected in the holes of the N-AlGaN layer 130 one by one, the diameter of each sub-electrode pillar is smaller than that of each hole, and preferably, the height of each sub-electrode pillar is lower than that of the N-AlGaN layer 130, so that the device has lower voltage. It should be emphasized that the center distances between two adjacent sub-electrode columns are equal, that is, the center distances between two adjacent holes are also equal, so that a structure in which two adjacent rows of sub-electrode columns are distributed in a staggered manner is formed, and the whole structure is a honeycomb structure.
Preferably, the N-type metal electrode layer comprises 5 rows of electrode pillars 200, each row of electrode pillars comprises 4 sub-electrode pillars, each sub-electrode pillar has a diameter of 100-110 μm, preferably 106 μm, and a center distance between two adjacent holes is 140-155 μm, i.e. a minimum distance between hole walls of two holes is 40-45 μm, preferably 43 μm.
As a preferred mode, the lead layer 500 connecting the pad metal layer 700 and the N-type metal electrode layer takes the following special form: the lead layer 500 includes a plurality of connection posts 510, and the connection posts 510 penetrate through the P-type metal electrode layer 400 and are connected to the sub-electrode posts one by one.
It is further preferred that the lead layer 500 further comprises a plurality of connecting strips 520, and the connecting strips 520 are connected to the top ends of the connecting columns 510 in each row. In addition, one end of the connecting bar 520 is provided with a connecting point electrically connected with the pad metal layer 700 on the outer layer of the chip, so that the number of hollow through holes formed in the silicon dioxide passivation layer 600 can be reduced, and the integral molding of the chip is facilitated.
In a preferred embodiment, the metal in the N-type metal electrode layer used in the deep ultraviolet light emitting diode chip provided by the present invention sequentially comprises Ti/Al/Ti/Au with corresponding thicknesses of 5nm/10nm/5nm/10nm, while the metal in the lead layer 500 comprises Cr and Au, and the total thickness of the lead layer 500 is 300 nm.
Preferably, the substrate is a c-plane sapphire substrate 110, the surface of the P-GaN layer is provided with a Ni layer and an Au layer, the thickness of the Ni layer is 20nm, and the thickness of the Au layer is 50 nm. In one embodiment, the edge of the N-AlGaN layer 130 shrinks inward to form a step with a predetermined thickness, wherein the predetermined thickness is 600 nm and 800 nm. Namely, the N-AlGaN layer 130 has an upper layer and a lower layer, wherein the edge of the upper layer relative to the lower layer contracts inward at the same distance or in the same proportion to form a step, so that the current can be expanded transversely better, and thus a step with a width of 200-300 nm is formed by etching in the chip preparation process.
As another preferable scheme, a plurality of through holes 610 are formed in the silicon dioxide passivation layer 600 of the deep ultraviolet light emitting diode chip, a boss 410 corresponding to the through hole 610 is formed on the P-type metal electrode layer 400, and the boss 410 can abut on the surface of the pad metal layer 700 through the through hole 610. The bumps 410 are preferably formed in a rounded rectangular cross-sectional shape for facilitating photolithography and development, and for increasing the contact area between the pad metal layer 700 and the P-type metal electrode layer 400 (Ni/Au).
The invention also provides a method for preparing the deep ultraviolet light emitting diode chip, which is used for preparing the deep ultraviolet light emitting diode chip, and as shown in fig. 3, the method mainly comprises the following steps:
step S10: manufacturing an epitaxial structure 100: an epitaxial structure 100 is grown, and a plurality of holes are formed in the epitaxial structure 100. Specifically, holes for placing an N-type metal electrode layer are etched on the N-AlGaN layer 130 and the light-emitting layer/electron blocking layer/P-GaN layer 310 by a common etching method. Preferably, the photoresist is used as a mask, and BCl is treated3And Cl2The step structure is etched on the epitaxial structure by using plasma in the mixed atmosphere.
Step S20: manufacturing an N-type metal electrode layer: evaporating an N-type metal electrode layer and stripping to form a plurality of rows of electrode columns 200, and annealing for a first preset time. The method comprises the steps of spin-coating a photoresist, prebaking the photoresist, carrying out projection exposure and development on the photoresist by using an ultraviolet light source, evaporating an N-type metal electrode layer by using an electron beam and stripping by using a stripping solution, and annealing for first preset time, wherein the annealing temperature is 750-850 ℃, preferably 800 ℃, and the first preset time is 45 s. In addition, the formation process of the 5 columns of the cylindrical electrodes distributed in a staggered manner is as follows: spin-coating a photoresist on a chip to be processed, transferring a photoetching plate with 5 columns of columnar electrode patterns in staggered distribution onto the chip to be processed with the photoresist by an ultraviolet exposure method, then placing the chip to be processed in a developing solution for soaking for 60s to obtain 5 columns of electrode structure patterns in staggered distribution, evaporating an N-type metal electrode layer by an electron beam evaporation method, placing an evaporated experimental sample in a heated stripping solution for soaking for 10min, and removing redundant metal to obtain 5 columns of columnar electrode structures in staggered distribution.
Step S30: manufacturing a P-type metal electrode layer 400: and evaporating the P-type metal electrode layer 400, stripping the P-type metal electrode layer 400 to form a plurality of holes corresponding to the holes in the epitaxial structure 100, and annealing for a second preset time. The method comprises the steps of spin-coating a photoresist, pre-baking the photoresist, performing projection exposure and development on the photoresist by using an ultraviolet light source, evaporating a P-type metal electrode layer 400 by using an electron beam, stripping by using a stripping solution, and annealing for a second preset time, wherein the annealing temperature is 500-550 ℃, preferably 500 ℃, and the second preset time is 5 min.
Step S40: making a lead layer 500: the lead layer 500 is evaporated and stripped to form the plurality of connection studs 510. Specifically, spin-coating a photoresist, pre-baking the photoresist, performing projection exposure and development on the photoresist by using an ultraviolet light source, evaporating the lead layer 500 by using an electron beam, and stripping by using a stripping solution.
Of course, other relevant process steps are also included in the chip preparation process, such as:
the step S10 and the step S20 include one of the following steps: a through track is etched between adjacent chips.
Step S40 is followed by:
the second process step: and (3) evaporating a silicon dioxide passivation layer 600, evaporating the silicon dioxide passivation layer with the thickness of 1 mu m and the evaporation temperature of 300 ℃, and performing corrosion correction by using a buffer solution containing hydrofluoric acid through a photoresist photoetching mask, wherein the corrosion time is 1 min. The evaporated silicon dioxide passivation layer 600 prevents the protection electrode from being corroded and also plays a role in passivation.
The third process step: and (3) evaporation of metal of a bonding pad, spin-coating photoresist, pre-baking the photoresist, performing projection exposure and development on the photoresist by using an ultraviolet light source, and evaporating Cr/Al/Ti/Pt/Ti/Pt/Au by using an electron beam, wherein the total thickness is 1.9 mu m.
The fourth process step is as follows: and (3) polishing and cutting, namely, grinding and polishing the sapphire substrate 110 by using 2-micron grinding fluid, and performing laser cutting.
The fifth process step is as follows: and packaging, namely packaging the chip on the alumina ceramic substrate by using solder paste.
In order to show the beneficial effects of the chip with the structure, the invention tests the wall plug efficiency of the L ED chip and the L ED chip in the reference group, specifically, 30mil by 30mil is selected as the size of the chip, the duty ratio (the ratio of mesa to the whole chip area) is 70%, the distribution of the N-type metal electrode layer is designed in such a way that 20 independent cylindrical sub-electrode columns form a honeycomb structure, five rows are provided, each row of four sub-electrode columns has the diameter of 106 micrometers, the center distance between two adjacent holes is 43 micrometers, and the L ED chip is manufactured according to the preparation method.
According to the embodiment of the invention, a common strip is selected as a reference group, in order to ensure the accuracy of an experimental result, the duty ratio is kept at about 70% as well, meanwhile, L ED chip manufacturing is also completed according to the preparation method in the embodiment, the embodiment is only different from the reference group in the electrode structure, finally, 4-inch photoetching plates are manufactured by taking the two electrode structures as units, as shown in FIG. 4, when the injected current is 280mA, compared with the traditional strip electrode deep ultraviolet L ED, the wall insertion efficiency of the deep ultraviolet L ED of the honeycomb electrode is improved by 28%, and the deep ultraviolet L ED chip temperature of the honeycomb electrode is reduced by 3.1 ℃ through thermal infrared imager tests.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (9)
1. The deep ultraviolet light emitting diode chip is characterized by comprising an epitaxial structure and a P-type metal electrode layer positioned on the epitaxial structure, wherein the epitaxial structure comprises a substrate, an AlN buffer layer, an N-AlGaN layer, a light emitting layer/an electronic barrier layer/a P-GaN layer which are sequentially arranged;
the N-AlGaN layer, the light-emitting layer/the electron blocking layer/the P-GaN layer and the P-type metal electrode layer are all provided with a plurality of holes, and the positions of the adjacent two layers of holes are corresponding to each other;
the chip further comprises an N-type metal electrode layer and a lead layer, wherein the N-type metal electrode layer comprises a plurality of rows of electrode columns, each row of electrode columns comprises a plurality of sub-electrode columns, the sub-electrode columns are connected in the holes of the N-AlGaN layer one by one, and the diameters of the sub-electrode columns are smaller than those of the holes;
the center distances between two adjacent sub-electrode columns are equal;
the lead layer comprises a plurality of connecting columns, the connecting columns penetrate through the P-type metal electrode layer and are connected with the sub-electrode columns one by one, the lead layer further comprises a plurality of connecting strips, and the connecting strips are connected to the top ends of the connecting columns in each row;
the chip also comprises a silicon dioxide passivation layer positioned above the P-type metal electrode layer and two pad metal layers positioned above the silicon dioxide passivation layer, wherein a plurality of hollowed holes are formed in the silicon dioxide passivation layer, bosses corresponding to the hollowed holes are formed in the P-type metal electrode layer, and the bosses can penetrate through the hollowed holes to abut against the surface of one of the pad metal layers;
and arranging a connection point electrically connected with the other pad metal layer at one end of the connection strip.
2. The deep ultraviolet light emitting diode chip of claim 1, wherein the height of the sub-electrode pillar is lower than the height of the N-AlGaN layer.
3. The deep ultraviolet light emitting diode chip of claim 1, wherein the N-type metal electrode layer comprises 5 columns of electrode pillars, each column of electrode pillars comprises 4 sub-electrode pillars, and each sub-electrode pillar has a diameter of 100 to 110 μm; the center distance between two adjacent holes is 140-155 mu m.
4. The deep ultraviolet light emitting diode chip of claim 1, wherein the metals in the N-type metal electrode layer sequentially comprise Ti/Al/Ti/Au, and the corresponding thicknesses sequentially are 5nm/10nm/5nm/10 nm; the metal of the lead layer comprises Cr and Au, and the total thickness is 300 nm.
5. The deep ultraviolet light emitting diode chip of claim 1, wherein the substrate is a c-plane sapphire substrate, and the surface of the P-GaN layer is provided with a Ni layer and an Au layer, wherein the thickness of the Ni layer is 20nm, and the thickness of the Au layer is 50 nm.
6. The deep ultraviolet light emitting diode chip as claimed in claim 1, wherein the edge of the N-AlGaN layer is inwardly shrunk to form a step with a predetermined thickness, and the predetermined thickness is 600 to 800 nm.
7. A method for preparing a deep ultraviolet light emitting diode chip, which is used for preparing the deep ultraviolet light emitting diode chip as claimed in any one of claims 1 to 6, comprising the following steps:
s10: manufacturing an epitaxial structure: growing an epitaxial structure, and forming a plurality of holes on the epitaxial structure;
s20: manufacturing an N-type metal electrode layer: evaporating an N-type metal electrode layer and stripping to form a plurality of rows of electrode columns, and annealing for a first preset time;
s30: manufacturing a P-type metal electrode layer: evaporating a P-type metal electrode layer, stripping the P-type metal electrode layer to form a plurality of holes corresponding to the holes in the epitaxial structure, and annealing for a second preset time;
s40: manufacturing a lead layer: and evaporating the lead layer and peeling to form a plurality of connecting posts.
8. The method for manufacturing the deep ultraviolet light emitting diode chip as claimed in claim 7, wherein the first predetermined time in the step S20 is 45S, and the annealing temperature is 750 ℃ to 850 ℃; the second preset time in the step S30 is 5min, and the annealing temperature is 500-550 ℃.
9. The method for manufacturing deep ultraviolet light emitting diode chip as claimed in claim 7, wherein the step S10 further includes masking with photoresist on BCl3And Cl2The step structure is etched on the epitaxial structure by using plasma in the mixed atmosphere.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811375706.0A CN109524526B (en) | 2018-11-19 | 2018-11-19 | Deep ultraviolet light-emitting diode chip and preparation method thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201811375706.0A CN109524526B (en) | 2018-11-19 | 2018-11-19 | Deep ultraviolet light-emitting diode chip and preparation method thereof |
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| CN109524526A CN109524526A (en) | 2019-03-26 |
| CN109524526B true CN109524526B (en) | 2020-07-31 |
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