CN112510009A - DFN matrix carrier packaging structure and process flow - Google Patents
DFN matrix carrier packaging structure and process flow Download PDFInfo
- Publication number
- CN112510009A CN112510009A CN202011120431.3A CN202011120431A CN112510009A CN 112510009 A CN112510009 A CN 112510009A CN 202011120431 A CN202011120431 A CN 202011120431A CN 112510009 A CN112510009 A CN 112510009A
- Authority
- CN
- China
- Prior art keywords
- carrier
- chip
- dfn
- placing
- etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
- H01L23/4952—Additional leads the additional leads being a bump or a wire
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4825—Connection or disconnection of other leads to or from flat leads, e.g. wires, bumps, other flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68372—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support a device or wafer when forming electrical connections thereto
Abstract
The invention discloses a DFN matrix carrier packaging structure and a process flow, which comprises a carrier, wherein a placing table is arranged at the bottom end of the carrier, etching grooves are formed in the inner side of the lower part of the carrier, the number of the placing tables is four, and the etching grooves are formed in the space between the placing tables and the side wall of the lower part of the carrier. The DFN matrix carrier packaging structure adopts four carriers of a matrix 2X2, and can be used for placing one to four chips; compared with the existing structure, the size of a single chip can be enlarged by 1.4 times, and the range is wider; the bonding pad pins are square, the area of the bonding pad pins is twice that of the existing packaging form, and the bonding force of the bonding pad pins on a PCB (printed circuit board) is greatly enhanced; the production process is easy to process, and the chip does not need to be placed in a rotating way; the processing efficiency is improved.
Description
Technical Field
The invention relates to the field of chip packaging carriers, in particular to a DFN matrix type carrier packaging structure and a process flow.
Background
The chip package is a package for mounting a semiconductor integrated circuit chip, plays a role in mounting, fixing, sealing, protecting the chip and enhancing the electric heating performance, and is also a bridge for communicating the internal world of the chip with an external circuit, i.e., a contact on the chip is connected to pins of the package by wires, and the pins are connected with other devices by wires on a printed board. Therefore, the package plays an important role for both the CPU and other LSI integrated circuits, and a chip package carrier is required in this case.
In the prior art, a chip is placed on a square carrier which forms an angle of 45 degrees, four pins of a circuit are connected at the bottom, but the area of the pins contacting soldering tin is small, and the firmness is insufficient; only one chip can be placed; in the processing process, the requirement on equipment is high, the chip is placed to be consistent with the carrier in the processing process, the chip is placed in the center at 45 degrees, the chip rotates at 45 degrees in the processing process, and the requirement on the rotation precision of a machine is high; since the rotating function is used, the abrasion of the machine is high and the production efficiency is lowered.
Disclosure of Invention
The present invention is directed to a DFN matrix carrier package structure and a process flow thereof, so as to solve the problems mentioned in the background art.
In order to achieve the purpose, the invention provides the following technical scheme:
the utility model provides a DFN matrix carrier package structure, includes the carrier, the carrier bottom is provided with places the platform, carrier lower part inboard is provided with the etching groove, the quantity of placing the platform is four, place the space between platform and the carrier lower part lateral wall for the etching groove.
A process flow of adapting a DFN matrix carrier packaging structure to a large-size chip comprises the following steps:
1) coating the surface of the carrier with an etching coating;
2) carrying out half etching on the carrier in photoetching equipment to obtain an etching groove;
3) the unetched parts protrude to form placing tables, and the carrier is etched into four independent placing tables according to requirements;
4) grinding the chip to be packaged to the thickness required by packaging, and attaching a special adhesive film on the back.
5) And placing the chips on the placing tables of the carrier by using special equipment, wherein the large-size chips are positioned among the four placing tables.
6) The etching bath was filled with solder, and eight land pins for connecting circuits were formed on the bottom of the chip.
A process flow of adapting a DFN matrix carrier packaging structure to a small-size chip comprises the following steps:
1) coating the surface of the carrier with an etching coating;
2) carrying out half etching on the carrier in photoetching equipment to obtain an etching groove;
3) the unetched parts protrude to form placing tables, and the carrier is etched into four independent placing tables according to requirements;
4) grinding the chip to be packaged to the thickness required by packaging, and attaching a special adhesive film on the back.
5) And placing the chips on the placing tables of the carrier by using special equipment, wherein the small-size chips are respectively positioned in the middle of the four placing tables.
6) By filling the etching grooves with solder, two land pins for connecting circuits are formed at the bottom of the chip.
As a further scheme of the invention: the etching grooves are of arc surface structures and are mutually independent.
As a still further scheme of the invention: the side wall at the bottom end of the placing table protrudes out of the end face at the bottom end of the carrier.
As a still further scheme of the invention: the carrier can be used for placing one to four small-size chips or one large-size chip at the placing table.
As a still further scheme of the invention: and the side wall sideline of the carrier is parallel to the side wall sideline of the placing table.
As a still further scheme of the invention: and the bonding pad pin formed by pouring the etching groove is square.
Compared with the prior art, the invention has the beneficial effects that:
the DFN matrix carrier packaging structure adopts four carriers of a matrix 2X2, and can be used for placing one to four chips; compared with the existing structure, the size of a single chip can be enlarged by 1.4 times, and the range is wider; the bonding pad pins are square, the area of the bonding pad pins is twice that of the existing packaging form, and the bonding force of the bonding pad pins on a PCB (printed circuit board) is greatly enhanced; the production process is easy to process, and the chip does not need to be placed in a rotating way; the processing efficiency is improved.
Drawings
Fig. 1 is a top, bottom, side, and front cross-sectional view of a DFN matrix carrier package.
Fig. 2 is a schematic diagram of a DFN matrix carrier package structure and a large-sized chip.
Fig. 3 is a schematic diagram of a DFN matrix carrier package structure and a small-sized chip.
Fig. 4 is a top cross-sectional, bottom, and side view of a conventional carrier package structure.
Fig. 5 is a schematic diagram of a conventional carrier package structure and a large-sized chip.
In the figure: the chip comprises a carrier 1, a placing table 2, an etching groove 3, a large-size chip 4 and a small-size chip 5.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that unless otherwise explicitly stated or limited, the terms "mounted," "connected," and "disposed" are to be construed broadly and can, for example, be fixedly connected, disposed, detachably connected, disposed, or integrally connected and disposed. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
In the embodiment of the present invention, as shown in fig. 1 to 3, a DFN matrix carrier package structure includes a carrier 1, a placing table 2 is disposed at a bottom end of the carrier 1, etching grooves 3 are disposed on an inner side of a lower portion of the carrier 1, the number of the placing tables 2 is four, and a space between the placing tables 2 and a lower side wall of the carrier 1 is the etching groove 3.
The etching grooves 3 adopt cambered surface structures, and the etching grooves 3 are mutually independent.
The side wall at the bottom end of the placing table 2 protrudes out of the end surface at the bottom end of the carrier 1.
The carrier 1 can be placed with one to four small-sized chips 5 or one large-sized chip 4 at the placing table 2.
The side wall sidelines of the carrier 1 are parallel to the side wall sidelines of the placing table 2.
And the welding disc pins formed by pouring soldering tin in the etching grooves 3 are square.
As shown in fig. 4-5, a conventional carrier package structure includes a carrier 1, a square placing table 2 with an angle of 45 ° is used at the end of the carrier 1, and a large-sized chip 4 is placed on the placing table 2.
A process flow of adapting a DFN matrix carrier packaging structure to a large-size chip comprises the following steps:
1) coating an etching coating on the surface of the carrier 1;
2) carrying out half etching on the carrier 1 in photoetching equipment to obtain an etching groove 3;
3) the unetched parts protrude to form placing tables 2, and the carrier 1 is etched to form four independent placing tables 2 as required;
4) grinding the chip to be packaged to the thickness required by packaging, and attaching a special adhesive film on the back.
5) The chips are placed on the placing tables 2 of the carrier 1 with dedicated equipment, and the large-sized chips 4 are located in the middle of the four placing tables 2.
6) The etching bath 3 is filled with solder, and eight land pins for connecting circuits are formed on the bottom of the chip.
A process flow of adapting a DFN matrix carrier packaging structure to a small-size chip comprises the following steps:
1) coating an etching coating on the surface of the carrier 1;
2) carrying out half etching on the carrier 1 in photoetching equipment to obtain an etching groove 3;
3) the unetched parts protrude to form placing tables 2, and the carrier 1 is etched to form four independent placing tables 2 as required;
4) grinding the chip to be packaged to the thickness required by packaging, and attaching a special adhesive film on the back.
5) The chip is placed on the placing tables 2 of the carrier 1 by a special device, and the small-sized chips 5 are respectively positioned in the middle of the four placing tables 2.
6) By filling the etching bath 3 with solder, two land pins for connecting circuits are formed at the bottom of the chip.
The working principle of the invention is as follows:
the invention relates to a DFN matrix carrier packaging structure and a process flow,
the scheme of the prior art is briefly described as follows:
in the prior art, a square carrier with an angle of 45 degrees is used for placing a chip, four pins connected with a circuit are arranged at the bottom of the carrier,
objective disadvantages of the prior art:
a. the area of the pin contacting the soldering tin is small, and the firmness is insufficient
b. Can only place one chip
c. In the processing process, the requirement on equipment is higher, the chip is required to be placed in the same way as the carrier in the processing process, the chip is placed in the center at 45 degrees, the chip rotates at 45 degrees in the processing process, the requirement on the rotation precision of the machine is higher,
d. because of the use of the rotating function, the wear of the machine is high,
e. the production efficiency is reduced.
Objective disadvantages of the prior art:
1. only one carrier is provided, and one chip can be placed on the carrier;
2. the chip carrier is small, and the limitation on the size of a chip is large;
3. the pins are triangular, the contact surface is small, and the weldability is reduced;
4. the production process is difficult to process, the chip needs to be placed in a rotating mode, and the requirement on the rotating precision of the machine is high;
5. the processing efficiency is low.
The DFN matrix carrier packaging structure adopts four carriers of a matrix 2X2, and can be used for placing one to 4 chips; compared with the existing structure, the size of a single chip can be enlarged by 1.4 times, and the range is wider; the square pad pin is twice as large as the area of the conventional packaging form, so that the bonding force of the PCB is greatly enhanced; the production process is easy to process, and the chip does not need to be placed in a rotating way; the processing efficiency is improved;
one chip can be placed on each carrier, the chips are placed on the carriers by special equipment, multi-chip packaging can be completed, and 1-4 chips can be placed according to actual requirements; the matrix structure greatly enhances the versatility and diversity of such structures.
A. A single chip is placed in the package, the size of the chip can be amplified by 1.4 times under the condition of the same size, and the application range is enlarged;
B. 1-4 chips can be placed on the chip with the size smaller than that of a single carrier, and the selection range is enlarged;
C. the area of the bonding pad is doubled, and the bonding force of the pins on the PCB is increased;
D. the machining process does not need to rotate, the equipment performance is improved, and the efficiency is improved.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.
Claims (6)
1. The utility model provides a DFN matrix carrier package structure, includes carrier (1), its characterized in that, carrier (1) bottom is provided with places platform (2), carrier (1) lower part inboard is provided with etches groove (3), the quantity of placing platform (2) is four, place the space between platform (2) and carrier (1) lower part lateral wall and be etching groove (3).
A process flow of adapting a DFN matrix carrier packaging structure to a large-size chip comprises the following steps:
1) coating an etching coating on the surface of the carrier (1);
2) carrying out half etching on the carrier (1) in photoetching equipment to obtain an etching groove (3);
3) the unetched parts protrude to form placing tables (2), and the carrier (1) is etched into four independent placing tables (2) according to requirements;
4) grinding the chip to be packaged to the thickness required by packaging, and attaching a special adhesive film on the back.
5) Placing the chip on a placing table (2) of a carrier (1) by using special equipment, wherein the large-size chip (4) is positioned in the middle of the four placing tables (2).
6) The etching grooves (3) are filled with solder, so that eight pad pins for connecting circuits are formed at the bottom of the chip.
A process flow of adapting a DFN matrix carrier packaging structure to a small-size chip comprises the following steps:
1) coating an etching coating on the surface of the carrier (1);
2) carrying out half etching on the carrier (1) in photoetching equipment to obtain an etching groove (3);
3) the unetched parts protrude to form placing tables (2), and the carrier (1) is etched into four independent placing tables (2) according to requirements;
4) grinding the chip to be packaged to the thickness required by packaging, and attaching a special adhesive film on the back.
5) The chip special equipment is placed on the placing tables (2) of the carrier (1), and the small-size chips (5) are respectively positioned in the middle of the four placing tables (2).
6) The etching groove (3) is filled with solder, so that two pad pins for connecting circuits are formed at the bottom of the chip.
2. The DFN matrix carrier package according to claim 1, wherein the etching grooves (3) are formed as arc-shaped grooves, and the etching grooves (3) are independent of each other.
3. The DFN matrix carrier package according to claim 1, wherein the sidewall of the bottom end of the placement stage (2) protrudes beyond the end surface of the bottom end of the carrier (1).
4. The DFN matrix carrier package according to claim 1, wherein the carrier (1) is capable of placing one to four small-sized chips (5) or one large-sized chip (4) at the placing table (2).
5. The DFN matrix carrier package according to claim 1, wherein the carrier (1) sidewall borders and the placement table (2) sidewall borders are parallel to each other.
6. The DFN matrix carrier package according to claim 1, wherein the etched grooves (3) are square shaped by means of solder-pouring process.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011120431.3A CN112510009A (en) | 2020-10-19 | 2020-10-19 | DFN matrix carrier packaging structure and process flow |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011120431.3A CN112510009A (en) | 2020-10-19 | 2020-10-19 | DFN matrix carrier packaging structure and process flow |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN112510009A true CN112510009A (en) | 2021-03-16 |
Family
ID=74953912
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011120431.3A Pending CN112510009A (en) | 2020-10-19 | 2020-10-19 | DFN matrix carrier packaging structure and process flow |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112510009A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117238877A (en) * | 2023-11-14 | 2023-12-15 | 青岛泰睿思微电子有限公司 | DFN frame packaging structure and packaging method |
-
2020
- 2020-10-19 CN CN202011120431.3A patent/CN112510009A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117238877A (en) * | 2023-11-14 | 2023-12-15 | 青岛泰睿思微电子有限公司 | DFN frame packaging structure and packaging method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI360189B (en) | Integrated circuit package system employing device | |
| KR100854031B1 (en) | Stacked BGA Semiconductor Packages | |
| CN205984975U (en) | Filtering transient state high -voltage pulse's ultra -thin rectifier bridge | |
| CN112510009A (en) | DFN matrix carrier packaging structure and process flow | |
| US20040227223A1 (en) | Semiconductor device, electronic device, electronic apparatus, and methods for manufacturing semiconductor device and electronic device | |
| CN213026116U (en) | DFN matrix carrier packaging structure | |
| CN207753003U (en) | Encapsulating structure | |
| CN104409370A (en) | Flipping mounting method of stud bump chip and method for applying mounting pressure | |
| CN100481407C (en) | Pin ball grid array encapsulation structure of wafer | |
| KR20080067891A (en) | Multi chip package | |
| KR20120126365A (en) | Unit package and stack package having the same | |
| KR20090065433A (en) | Integrated circuit package system with package integration | |
| CN212967685U (en) | Novel DFN packaging structure | |
| CN215731695U (en) | Flip chip packaging structure | |
| CN214542219U (en) | Flip chip package structure | |
| CN218415062U (en) | Intelligent wearable device and SIP packaging module thereof | |
| CN212010939U (en) | Semiconductor packaging structure | |
| CN220189621U (en) | Chip packaging structure | |
| CN218996696U (en) | Packaging structure for improving chip pin density | |
| KR101096440B1 (en) | Dual Die Package | |
| CN216389352U (en) | Lead frame and semiconductor device | |
| CN111816624A (en) | Wafer-level chip packaging structure and packaging process thereof | |
| CN212750875U (en) | Semiconductor radiating fin device | |
| CN212625548U (en) | Heat dissipation type semiconductor packaging piece | |
| CN214705918U (en) | System-in-package of integrated multichip |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |