CN112486274B - Computer expansion card and computer system - Google Patents
Computer expansion card and computer system Download PDFInfo
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- CN112486274B CN112486274B CN202011258848.6A CN202011258848A CN112486274B CN 112486274 B CN112486274 B CN 112486274B CN 202011258848 A CN202011258848 A CN 202011258848A CN 112486274 B CN112486274 B CN 112486274B
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- 238000004891 communication Methods 0.000 claims abstract description 23
- 230000006870 function Effects 0.000 claims abstract description 6
- 230000002085 persistent effect Effects 0.000 claims description 37
- 230000002093 peripheral effect Effects 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 2
- 238000000034 method Methods 0.000 description 10
- 230000008569 process Effects 0.000 description 8
- 238000013507 mapping Methods 0.000 description 6
- 238000004364 calculation method Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000009471 action Effects 0.000 description 2
- 230000003993 interaction Effects 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/16—Constructional details or arrangements
- G06F1/18—Packaging or power distribution
- G06F1/183—Internal mounting support structures, e.g. for printed circuit boards, internal connecting means
- G06F1/185—Mounting of expansion boards
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
Abstract
The invention provides a computer expansion card and a computer system, wherein the computer expansion card comprises an expansion card circuit board, a network interface module, a bus interface module, an FPGA chip and an expansion card memory, and the computer expansion card is connected with a computer main system through the bus interface module, and is connected with a transaction system through the network interface module and a communication network; the FPGA chip is used for carrying out functional configuration according to configuration information acquired by the bus interface module from a computer main system after starting; and after the function configuration is completed, the FPGA chip is matched with the memory of the expansion card, the transaction data received by the network interface module from the transaction system is subjected to operation processing, and an operation result obtained after the operation processing is sent to the transaction system through the network interface module. The invention can improve the transaction data processing efficiency and reduce the occupation of other resources in the computer system, thereby improving the efficiency of the whole computer system.
Description
Technical Field
The present invention relates to the field of computer technology, and more particularly, to a computer expansion card and a computer system.
Background
The existing computer system mainly comprises a central processing unit (Central Processing Unit, CPU), a memory, an input/output control system, various external devices and the like. The CPU is the main component for high-speed operation processing of information, and the processing speed can reach more than hundreds of millions of operations per second; the memory is used for storing programs, data and files, and is often composed of a fast internal memory (i.e. a memory) and a slow mass external memory (i.e. a hard disk); various input-output external devices are information converters between man-machine, and information exchange between the external devices and a main memory (central processing unit) is managed by an input-output control system.
In the above computer system, the respective components work in coordination and unification under the control of the central processing unit: firstly, a program representing the calculation step and original data required in calculation are sent to a memory for storage through an input device under the control of an input command of a controller; secondly, when calculation starts, program instructions are fed into the controller one by one under the instruction fetching action; the controller decodes the instruction, sends a storage, fetch command and an operation command to the memory and the arithmetic unit according to the operation requirement of the instruction, calculates the result through the arithmetic unit of the central processing unit and stores the result in the memory; under the action of the fetch and output commands of the controller, the calculation result is output through the output equipment.
In the above computer system, all operations and operations depend on the central processing unit, which causes an excessive load on the central processing unit, especially for some tasks requiring single and repeated computation, so that the operation efficiency of the computer system is greatly reduced.
Disclosure of Invention
The invention aims to solve the technical problem that all operations in the computer system depend on a central processing unit, and provides a computer expansion card and the computer system.
The invention solves the technical scheme that the invention provides a computer expansion card, which comprises an expansion card circuit board, a network interface module, a bus interface module, an FPGA chip and an expansion card memory, wherein the computer expansion card is connected with a computer main system through the bus interface module, and is connected with a transaction system through the network interface module and a communication network;
the expansion card circuit board is provided with an expansion card bus, and the network interface module, the bus interface module, the FPGA chip and the expansion card memory are respectively assembled to the expansion card circuit board and are respectively connected with the expansion card bus;
the FPGA chip is used for carrying out functional configuration according to configuration information acquired by the bus interface module from a computer main system after starting; and after the function configuration is completed, the FPGA chip is matched with the memory of the expansion card, the transaction data received by the network interface module from the transaction system is subjected to operation processing, and an operation result obtained after the operation processing is sent to the transaction system through the network interface module.
Preferably, the expansion card memory comprises a persistent storage class memory, and a transaction data processing program is solidified in the persistent storage class memory;
and after the function configuration is completed, the FPGA chip reads the transaction data processing program from the persistent storage-level memory and executes the transaction data processing program.
Preferably, the persistent storage-level memory comprises a memory interface, a DRAM chipset, a control chip, a flash memory and an internal bus which are integrated into the same matrix, wherein the control chip is respectively connected with the memory interface, the DRAM chipset and the flash memory through the internal bus, and the memory interface is connected to the expansion card bus.
Preferably, the bus interface module comprises a PCIe interface and a PCI interface chip connected with the PCIe interface, and the FPGA chip is connected with the PCI interface chip through a peripheral circuit.
Preferably, the network interface module comprises a first network interface, a second network interface, a first communication chip connected with the first network interface and a second communication chip connected with the second network interface, and the FPGA chip is connected with the first communication chip and the second communication chip through peripheral circuits respectively;
the FPGA chip receives transaction data from the transaction system through the first network interface and the first communication chip, and returns an operation result obtained by operation processing to the transaction system through the second network interface and the second communication chip.
Preferably, the expansion card bus comprises a printed circuit on the expansion card circuit board and a signal processing chip welded to the expansion card circuit board, and the network interface module, the bus interface module, the FPGA chip and the expansion card memory are respectively welded to the expansion card circuit board.
The embodiment of the invention also provides a computer system, which comprises a main board, a central processing unit, a main memory module, a display adapter, a persistent memory and at least one computer expansion card as claimed in any one of claims 1 to 6;
the main board is provided with a system bus, and the central processing unit, the main memory module, the display adapter and the persistent memory are respectively connected to the system bus;
the main board also comprises an expansion card slot connected with the system bus, and a bus interface module of the computer expansion card is inserted into the expansion card slot.
Preferably, the FPGA chip further stores the operation result of the operation processing to the memory of the expansion card;
and the central processing unit acquires the operation result from the memory of the expansion card through the system bus and the bus interface module of the computer expansion card in a preset period or when receiving an output instruction, and sends the operation result to the display adapter for output.
Preferably, the FPGA chip further stores the operation result of the operation processing to the memory of the expansion card; and the central processing unit acquires the operation result from the memory of the expansion card through the system bus and the bus interface module of the computer expansion card and stores the operation result into the persistent memory.
Preferably, the system bus comprises a DRAM bus, a PCIe bus and a bus converter, and the DRAM bus and the PCIe bus are connected through the bus converter; the central processing unit and the main memory module are respectively connected to the DRAM bus, and the display adapter, the persistent memory and the computer expansion card are respectively connected to the PCIe bus.
According to the computer expansion card and the computer system, the configured FPGA chip is used for directly processing the transaction data received by the network interface module, the whole processing process is not needed to be participated by a central processing unit, the transaction data processing efficiency is improved, and meanwhile, the occupation of other resources of the system is reduced, so that the efficiency of the whole computer system is improved.
Drawings
FIG. 1 is a schematic diagram of a computer expansion card according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of an expansion card memory in a computer expansion card according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a computer system according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
As shown in fig. 1, a schematic diagram of a computer expansion card according to an embodiment of the present invention is provided, where the computer expansion card may be directly plugged into a general computer or a server (e.g., an IPOS server) and directly perform data processing. The computer expansion card of the present embodiment includes an expansion card circuit board 10, an FPGA chip 11, an expansion card memory 12, a network interface module 13, and a bus interface module 14, and the computer expansion card is connected to a computer main system through the bus interface module 14, the network interface module 13, and a transaction system (e.g., each client in the transaction system) via a communication network. The network interface module 13 and the bus interface module 14 include chips for performing data processing according to a communication protocol in addition to interface terminals, so as to accomplish corresponding data interaction.
The expansion card circuit board 10 is provided with an expansion card bus 101, and the fpga chip 11, the expansion card memory 12, the network interface module 13 and the bus interface module 14 are respectively assembled to the expansion card circuit board 10 and respectively connected with the expansion card bus 101. Specifically, the expansion card circuit board 10 may employ a printed circuit board (Printed Circuit Board, PCB), and the expansion card bus 101 includes a printed circuit on the expansion card circuit board 10 and a signal processing chip (which may perform data conversion processing) soldered to the expansion card circuit board 10, and the FPGA chip 11, the expansion card memory 12, the network interface module 13, and the bus interface module 14 are soldered to the expansion card circuit board 10, respectively. The expansion card circuit board 10 can obtain a power supply voltage from a computer main system through the bus interface module 14 and perform data interaction.
Of course, in practical applications, the FPGA chip 11, the expansion card memory 12, the network interface module 13, and the bus interface module 14 may be fixed to the expansion card circuit board 10 by other manners and connected to the expansion card bus 101 on the expansion card circuit board 10, for example, through a pluggable interface or the like.
The FPGA chip 11 internally includes three parts, i.e., a configurable logic module (Configurable Logic Block, CLB), an input-output module (Input Output Block, IOB), and an Interconnect (Interconnect), which can be configured to perform different logic functions. In this embodiment, after the FPGA chip 11 is started, functional configuration is performed according to configuration information obtained by the bus interface module 14 from the computer main system (for example, the FPGA chip 11 stores the configuration information into an internal static storage unit); after the functional configuration is completed, the FPGA chip 11 cooperates with the expansion card memory 12 to perform operation processing on transaction data (e.g., a transaction request including transaction data from a client) received by the network interface module 13 from the transaction system, and sends an operation result obtained after the operation processing to the transaction system (e.g., a client sending the transaction request) through the network interface module 13.
According to the computer expansion card, the FPGA chip 11 is configured only according to the configuration information from the computer main system, and the transaction data received by the network interface module 13 is directly processed through the configured FPGA chip 11, so that the whole transaction data processing process does not need the participation of a central processing unit of the computer main system, the transaction data processing efficiency is improved, and meanwhile, the occupation of other resources of the system is reduced, so that the efficiency of the whole computer system is improved.
The expansion card memory 12 includes a persistent storage class memory (Storage Class Memory, SCM) in which transaction data processing procedures are solidified, i.e., the transaction data processing procedures are not lost when the persistent storage class memory is powered down. After the functional configuration of the FPGA chip 11 is completed, the FPGA chip 11 reads the transaction data processing program from the persistent storage memory and executes (in conjunction with the operating system) the transaction data processing program to perform arithmetic processing on the transaction data. That is, after the configuration of the FPGA chip 11 is completed, the transaction data processing program is not required to be loaded from the computer main system, so that the starting speed of the computer expansion card can be increased, and the complexity of the computer main system can be reduced. The transaction data processing program can be updated or modified by the computer host system.
In addition, the persistent storage-level memory may be further cured with an operating system (e.g., an embedded operating system) for running the FPGA chip 11 after the configuration is completed. After the configuration is completed, the FPGA chip 11 sends a read-write request to the persistent storage class memory, acquires an instruction set from the persistent storage class memory, and writes execution result data to the persistent storage class memory. Specifically, the persistent storage level memory may use a 3D XPoint flash memory, and an operating system is stored in the persistent storage level memory, for example, in a Firmware (Firmware) form, so that when the computer expansion card is started, the operating system does not need to be loaded, thereby greatly accelerating the starting speed of the computer expansion card.
Of course, in practical application, the expansion card memory 12 may also use an existing DRAM chip, and the transaction data processing program and the corresponding operating system may be stored in a hard disk of the computer host system and loaded into the expansion card memory 12 of the computer expansion card through the bus interface module 14 under the control of the central processing unit of the computer host system. For example, the transaction data processing program and operating system may be retrieved from the computer host system along with configuration information.
In another embodiment of the present invention, when the expansion card memory 12 includes a persistent storage class memory as shown in fig. 2, the persistent storage class memory may further include a memory interface (not shown in the figure) integrated into the same substrate, a DRAM chipset 122, a control chip 121, a flash memory 123 and an internal bus, and the control chip 121 is connected to the memory interface, the DRAM chipset 122 and the flash memory 123 through the internal bus, respectively, and the memory interface is connected to the expansion card bus 101.
When the transaction data processing program and the operating system are cured in the persistent storage memory (specifically, may be stored in the flash memory 123), after the configuration of the FPGA chip 11 is completed, the control chip 121 carries the instruction set of the operating system and the transaction data processing program into the DRAM chipset 122 for execution by the FPGA chip 11. In the course of the transaction data processing by the computer expansion card, the control chip 121 acquires an instruction set from the DRAM chipset 122 in response to a read/write request of the FPGA chip 11, and writes execution result data of the FPGA chip 11 to the DRAM chipset 122.
In addition, in the transaction data processing process of the computer expansion card, when the instruction set waiting for the FPGA chip 11 to read in the DRAM chipset 122 meets the preset condition, the control chip 121 obtains the subsequent instruction set of the instruction set in the DRAM chipset 122 from the flash memory 123, and stores the subsequent instruction set in the DRAM chipset 122. Specifically, the DRAM chipset 122 includes at least two logic memory areas that are a main mapping area and a standby mapping area, where the logic memory area where the instruction set currently read by the FPGA chip 11 is located is the main mapping area, and other logic memory areas are standby mapping areas; the preset conditions are as follows: the number of instruction sets waiting to be read in the main mapping area is smaller than a preset value, or the time for which the instruction sets waiting to be read in the main mapping area are executed in the FPGA chip 11 is smaller than a preset time.
In this way, the control chip 121 of the persistent storage level memory can update the content in the DRAM chipset 122 directly according to the instruction set being executed by the FPGA chip 11, so that the content in the DRAM chipset 122 can be automatically updated according to the operation state of the FPGA chip 11, and thus the storage capacity of the DRAM chipset 122 is nearly infinite, the FPGA chip 11 does not need to interact with a mass storage device, so that the FPGA chip 11 can be always in a high-efficiency operation state, and the operation efficiency of the computer expansion card is greatly improved.
In addition, when the transaction data processing program is not solidified into the persistent storage class memory, the transaction data processing program may be included in the configuration information, and after the FPGA chip 11 is started, the transaction data processing program is moved to the DRAM chipset 122 through the control chip 121.
In one embodiment of the present invention, the bus interface module 14 includes a PCIe interface and a PCI interface chip connected to the PCIe interface, and the FPGA chip 11 is connected to the PCI interface chip through a peripheral circuit. Through the PCIe interface, the computer expansion card of the embodiment may be directly plugged into the PCIe slot of the computer system motherboard, without adjusting a hardware portion of the existing computer system, thereby simplifying a structure of the computer system.
The network interface module 13 may specifically include a first network interface, a second network interface, a first communication chip connected to the first network interface, and a second communication chip connected to the second network interface, where the FPGA chip 11 is connected to the first communication chip and the second communication chip through peripheral circuits, respectively. The FPGA chip 11 receives the transaction data from the transaction system through the first network interface and the first communication chip, and the FPGA chip 11 returns the operation result of the operation processing to the transaction system through the second network interface and the second communication chip.
The structure and data processing manner of the network interface module 13 and the bus interface module 14 are similar to those of the existing computer system, and will not be described herein.
As shown in fig. 3, an embodiment of the present invention further provides a computer system, which may be a server for transaction control (e.g., an IPOS server), or the like. The computer system of this embodiment includes a motherboard, a central processing unit 21, a main memory module 23 (e.g., DRAM), a display adapter 26, a persistent storage 24, and at least one computer expansion card as shown in FIG. 1. Specifically, a system bus is provided on the motherboard of the computer system, and the central processing unit 21, the main memory module 23, the display adapter 26, and the persistent storage 24 are respectively connected to the system bus. The main board also comprises an expansion card slot connected with the system bus, and a bus interface module of the computer expansion card is inserted into the expansion card slot.
In one embodiment of the present invention, the system bus may specifically include a DRAM bus 271, a PCIe bus 272, and a bus converter 273, where the DRAM bus 271 and the PCIe bus 272 are connected through the bus converter 273; the CPU 21, the main memory module 23 are each coupled to a DRAM bus 271, and the persistent storage 24, the display adapter 26, and the computer expansion card are each coupled to a PCIe bus 272.
In this embodiment, the central processing unit 21 may control the computer system to operate based on the main operating system, for example, to implement process management, storage management, device management, file management, job management, input/output, and the like. The main operating system may be an operating system of a single kernel structure such as UNIX or windows NT, or an operating system of a hierarchical structure such as SUE. Specifically, the central processing unit 21 may cooperate with the DMA (Direct Memory Access ) controller 22, the main memory module 23, the persistent storage 24, and the like to realize operation control of the computer system. The persistent storage 24 may be an HDD (Hard Disk Drive), an SSD (Solid State Disk), an SSHD (i.e., a mechanical Hard Disk with a flash memory module on a Disk body), etc., the main operating system is stored in the persistent storage 24, and when the server is started, the cpu 21 and the DMA controller 22 load an instruction set of the main operating system into the main memory module 23.
In the start-up phase of the computer system, the central processing unit 21 sends the configuration information of the FPGA chip 11 of the computer expansion card to the computer expansion card, the FPGA chip 11 performs configuration (for example, writing into the internal static storage unit thereof) after receiving the configuration information through the bus interface module 14, and after completing the configuration, the FPGA chip 11 controls the computer expansion card to access the transaction system and perform independent transaction data processing. Because the FPGA chip 11 only needs to process the transaction data, and the input and output operations of the computer system are processed by the central processing unit 21, the FPGA chip 11 only needs to process the logic operation of the transaction data, thereby greatly improving the processing speed of the transaction data, and the processing process of the transaction data does not occupy the resources of the central processing unit 21.
In one embodiment of the present invention, the FPGA chip 11 also stores the operation result of the operation processing completion into the expansion card memory 12; the central processing unit 21 obtains the operation result from the expansion card memory 12 through the system bus and the bus interface module 14 of the computer expansion card at a preset period or when receiving the output instruction, and sends the operation result to the display adapter 26 for output. By the mode, the display of the operation structure can be realized, and the display process does not need to be participated in by the FPGA chip 11 of the computer expansion card.
In addition, the central processing unit 21 can also obtain the operation result from the expansion card memory 12 through the system bus and the bus interface module 14 of the computer expansion card and store the operation result into the persistent memory 24, so that the operation such as analysis of the operation result by the central processing unit 21 can be conveniently performed later.
The present invention is not limited to the above-mentioned embodiments, and any changes or substitutions that can be easily understood by those skilled in the art within the technical scope of the present invention are intended to be included in the scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.
Claims (9)
1. The computer expansion card is characterized by comprising an expansion card circuit board, a network interface module, a bus interface module, an FPGA chip and an expansion card memory, wherein the computer expansion card is connected with a computer main system through the bus interface module, and is connected with a transaction system through the network interface module and a communication network;
the expansion card circuit board is provided with an expansion card bus, and the network interface module, the bus interface module, the FPGA chip and the expansion card memory are respectively assembled to the expansion card circuit board and are respectively connected with the expansion card bus;
the FPGA chip is used for carrying out functional configuration according to configuration information acquired by the bus interface module from a computer main system after starting; after the function configuration is completed, the FPGA chip is matched with the memory of the expansion card, operation processing is carried out on transaction data received by the network interface module from the transaction system, and an operation result obtained after the operation processing is sent to the transaction system through the network interface module;
the expansion card memory comprises a persistent storage class memory, and a transaction data processing program is solidified in the persistent storage class memory;
and after the function configuration is completed, the FPGA chip reads the transaction data processing program from the persistent storage-level memory and executes the transaction data processing program.
2. The expansion card of claim 1, wherein the persistent storage class memory comprises a memory interface, a DRAM chipset, a control chip, a flash memory, and an internal bus integrated into the same substrate, and wherein the control chip is connected to the memory interface, the DRAM chipset, the flash memory via the internal bus, respectively, the memory interface being connected to the expansion card bus.
3. The computer expansion card of claim 2, wherein the bus interface module comprises a PCIe interface and a PCI interface chip connected to the PCIe interface, and the FPGA chip is connected to the PCI interface chip through a peripheral circuit.
4. The computer expansion card of claim 2, wherein the network interface module comprises a first network interface, a second network interface, a first communication chip connected with the first network interface, and a second communication chip connected with the second network interface, and the FPGA chip is connected with the first communication chip and the second communication chip through peripheral circuits, respectively;
the FPGA chip receives transaction data from the transaction system through the first network interface and the first communication chip, and returns an operation result obtained by operation processing to the transaction system through the second network interface and the second communication chip.
5. The expansion card of claim 1, wherein said expansion card bus comprises printed circuits on said expansion card circuit board and signal processing chips soldered to said expansion card circuit board, said network interface module, bus interface module, FPGA chips and expansion card memory being soldered to said expansion card circuit board, respectively.
6. A computer system comprising a motherboard, a central processing unit, a main memory module, a display adapter, a persistent memory, and at least one computer expansion card according to any of claims 1-5;
the main board is provided with a system bus, and the central processing unit, the main memory module, the display adapter and the persistent memory are respectively connected to the system bus;
the main board also comprises an expansion card slot connected with the system bus, and a bus interface module of the computer expansion card is inserted into the expansion card slot.
7. The computer system according to claim 6, wherein the FPGA chip further stores the operation result of the operation processing completion in the expansion card memory;
and the central processing unit acquires an operation result from the memory of the expansion card through the system bus and the bus interface module of the computer expansion card in a preset period or when receiving an output instruction, and sends the operation result to the display adapter for output.
8. The computer system according to claim 6, wherein the FPGA chip further stores the operation result of the operation processing completion in the expansion card memory; and the central processing unit acquires the operation result from the memory of the expansion card through the system bus and the bus interface module of the computer expansion card and stores the operation result into the persistent memory.
9. The computer system of claim 6, wherein the system bus comprises a DRAM bus, a PCIe bus, and a bus translator, and wherein the DRAM bus and PCIe bus are connected by the bus translator; the central processing unit and the main memory module are respectively connected to the DRAM bus, and the display adapter, the persistent memory and the computer expansion card are respectively connected to the PCIe bus.
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