CN112485791A - Through-wall imaging radar double-fundamental-frequency three-channel time base control circuit - Google Patents

Abstract

The invention relates to a through-wall imaging radar double-fundamental-frequency three-channel time base control circuit, which comprises an FPGA (field programmable gate array) time sequence control circuit, a programmable time sequence control circuit, a system clock circuit, a reference clock circuit and three paths of delay pulse output circuits which are arranged in parallel; the FPGA time sequence control circuit is electrically connected with the system clock circuit and is used for outputting initial pulses, delay data, fine tuning data and channel gating signals; the programmable time sequence control circuit comprises an ECL conditioning circuit, a programmable delay chip and a fine tuning DAC chip. The invention realizes high-precision and large-range time delay control of three channels through the time sequence control circuit; the synchronous design of the two base frequency clocks reduces time jitter errors and improves the stability of the pulse signal generation module; the method can set 16-bit delay configuration control words, is flexible in parameter adjustment, can realize ultrahigh delay precision of 2ps, can realize continuous scanning of a maximum 2000ns time window, can simultaneously send three paths of delay pulses or send the delay pulses in a time-sharing manner, and has controllable time interval of time-sharing sending.

Description

Through-wall imaging radar double-fundamental-frequency three-channel time base control circuit

Technical Field

The invention relates to the technical field of radars, in particular to a through-wall imaging radar double-fundamental-frequency three-channel time base control circuit.

Background

One of the technical difficulties in the development of real-time through-wall imaging radar systems is how to obtain a stable ultra-wideband radar signal. Through-The-Wall Radar Imaging, mainly compiled by Moeness G.Amin, USA, discloses a real-time Through-Wall Imaging Radar system composed of a computer system based on PCI and a real-time sampling oscilloscope. In this system, to obtain ultra-wideband pulses of 1ns width, real-time sampling resolution is required to reach 200ps (5G/s sampling rate), and analog bandwidth of several gigahertz (GHz). This approach, while feasible, is cost prohibitive and makes the processing of real-time digital data streams of 5 x 109 samples per second difficult.

The through-wall radar system is required to have imaging and positioning functions, and has the characteristics of quasi-stability and periodicity in a short time by means of radar echo signals, so that the through-wall imaging radar time base control circuit can be realized by adopting a time equivalent method. The method has the advantages that a relatively high sampling rate can be obtained at a low real-time speed, and the requirement on data storage is reduced. According to the requirement of an equivalent sampling principle, the higher the sampling precision of the time base is, the truer the restored radar signal is, and the higher the detection precision of the target is. The time base resolution ratio used by the traditional through-wall radar is mostly 5ps to 20ps, the sampling is carried out by adopting an equal-interval cyclic scanning mode, the precision of the sampling frequency reaches the bottleneck, and more accurate detection data cannot be obtained.

Disclosure of Invention

The invention aims to solve the technical problem of providing a through-wall imaging radar double-fundamental-frequency three-channel time base control circuit with high time resolution and high detection precision.

In order to solve the technical problems, the technical scheme of the invention is as follows: a through-wall imaging radar double-fundamental-frequency three-channel time base control circuit comprises an FPGA (field programmable gate array) time sequence control circuit, a programmable time sequence control circuit, a system clock circuit, a reference clock circuit and three paths of delay pulse output circuits which are arranged in parallel;

the FPGA time sequence control circuit comprises an FPGA module, the FPGA module is electrically connected with a system clock circuit, and the FPGA module comprises:

an initial pulse output end, configured to output an initial pulse, where a delay time interval Δ T of the initial pulse is equal to one system clock period;

a 10-bit delay control data terminal for outputting delay data;

a 6-bit fine tuning control data terminal for outputting fine tuning data;

a gating signal output end for outputting a channel gating signal for controlling the gating of the three paths of delay pulse output circuits;

the programmable timing control circuit comprises: the system comprises an ECL conditioning circuit, a programmable delay chip and a fine-tuning DAC chip, wherein a 10-bit delay control data end is electrically connected with the delay chip through a data bus, and a 6-bit fine-tuning control data end is also electrically connected with the fine-tuning DAC chip through the data bus;

the reference clock circuit and the initial pulse output end are electrically connected to the ECL conditioning circuit, the ECL conditioning circuit is used for carrying out ECL level conversion on the initial pulse and synchronizing with a reference clock, the ECL conditioning circuit further comprises a second cycle delay output end used for outputting a second cycle delay pulse, the delay interval deltat of the second cycle delay pulse is equal to one period of the reference clock, and the delay interval deltat is integral multiple of the delay interval deltat;

the programmable delay chip comprises:

a delay pulse input electrically connected to said second cyclic delay output;

the fine tuning data port is electrically connected with the fine tuning data output end of the fine tuning DAC chip and is used for receiving fine tuning data output by the fine tuning DAC chip;

and the delay pulse output end is used for outputting a third cyclic delay pulse, the delay interval of the third cyclic delay pulse is delta tau, the delay interval delta t is an integral multiple of the delay interval delta tau, and the delay pulse output ends are respectively electrically connected with the three paths of delay pulse output circuits.

As a preferable technical solution, the FPGA module communicates with an upper computer through an I2C interface.

As a preferred technical solution, the reference clock circuit is an ECL differential clock circuit.

As a preferred technical solution, the initial pulse output end includes a first output end and a second output end, the first output end is electrically connected to the ECL conditioning circuit, the second output end is electrically connected to the reference clock circuit through a first synchronization circuit and a reference pulse output circuit, and the reference pulse output circuit is configured to output a synchronized initial pulse.

As a preferred technical solution, the delay pulse output end and the reference clock circuit are electrically connected to the delay pulse output circuit through a second synchronization circuit.

Preferably, the delay pulse output circuit includes a differential driver for converting the extension pulse into differential signals and a pulse driver for synthesizing the differential signals into a single pulse to be output.

Due to the adoption of the technical scheme, the invention has the beneficial effects that: the invention realizes high-precision and large-range time delay control of three channels through the time sequence control circuit; the synchronous design of the two base frequency clocks reduces time jitter errors and improves the stability of the pulse signal generation module;

the system is communicated with a radar host through an I2C interface, is realized in FPGA through software simulation, is used for receiving time base control parameters, comprises delay configuration register control words, time window range control words, channel switching frequency control words and the like, can set 16-bit delay configuration control words, is flexible in parameter adjustment, can realize ultrahigh delay precision of 2ps, and has target positioning resolution reaching 0.6 mm;

the programmable time sequence control circuit takes a high-precision programmable delay chip as a core and is provided with a fine tuning pin of the programmable delay chip, 2ps precision delay is realized through the control of an ECL conditioning circuit and a high-sensitivity DAC chip, the signal-to-noise ratio of the system is improved through the combination of fixed-point scanning and cyclic delay, the time base control with large range and high precision is realized, the continuous scanning of a maximum 2000ns time window is realized, and the imaging positioning of a plurality of moving targets in a free space within 30 meters can be realized.

Under the control of an FPGA output channel selection signal, the three paths of delay pulses can be sent simultaneously or in a time-sharing mode, and the time-sharing sending time interval is controllable.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

FIG. 1 is an electrical schematic block diagram of an embodiment of the present invention;

FIG. 2 is an electrical schematic block diagram of a programmable timing control circuit.

Detailed Description

As shown in fig. 1 and fig. 2, a through-wall imaging radar double-fundamental-frequency three-channel time-base control circuit includes an FPGA time-base control circuit, a programmable time-base control circuit, a system clock circuit, a reference clock circuit, and three paths of delay pulse output circuits arranged in parallel;

the FPGA time sequence control circuit comprises an FPGA module, the FPGA module is electrically connected with a system clock circuit, the FPGA module is communicated with an upper computer through an I2C interface, receives various time base control parameters sent by the upper computer, including time delay configuration register control words, time window range control words, channel switching frequency control words and the like, and stores parameter data, and the FPGA configures the working mode of the time base control circuit according to command parameters, so that the working mode of the through-wall imaging radar is determined.

The FPGA module includes:

the initial pulse output end is used for outputting an initial pulse, and the delay time interval Delta T of the initial pulse is equal to one system clock period;

a 10-bit delay control data terminal for outputting delay data;

a 6-bit fine tuning control data terminal for outputting fine tuning data;

and the gating signal output end is used for outputting a channel gating signal for controlling the gating of the three paths of delay pulse output circuits.

The initial pulse output end comprises a first output end and a second output end, the first output end is electrically connected with the programmable time sequence control circuit, the second output end is electrically connected with the reference clock circuit through the first synchronous circuit and the reference pulse output circuit, and the reference pulse output circuit is used for outputting synchronous initial pulses.

The implementation method for simulating I2C time sequence programming in the FPGA is as follows:

the first step is as follows: and when the FPGA is electrified, each register is emptied.

The second step is that: during the period of detecting the high level of the SCL clock line, the SDA data line represents a starting signal from the high level to the low level, one bit of data is transmitted in each clock cycle of the SCL, and 24 bits of data are transmitted in total, and the total number of the bytes is 3; during the period of detecting the high level of the SCL clock line, the change of the SDA data line from the low level to the high level indicates the termination of data transmission and represents that one time base control parameter is completely transmitted; and so on, 12 sets of control parameters need to be transmitted.

The third step: according to the first 8 bit address bits of the data parameter, the purpose of the control word of the rear 16 bit register is determined and respectively latched to the corresponding registers to respectively represent different purposes such as delay configuration, time window range, channel switching frequency and the like.

The FPGA converts the parameters into various configuration bytes including step scanning length, scanning interval, scanning starting point, scanning end point, channel switching frequency and the like through software logic programming in the FPGA according to the control word parameters latched into the register; in the embodiment, two paths of TTL level initial pulse signals are generated by frequency division of a 50MHz system clock; the output 16-bit programmable control data comprises 10-bit delay chip control bus data and 6-bit bus data of an external high-sensitivity trimming DAC chip.

A programmable timing control circuit, comprising: the ECL circuit comprises an ECL conditioning circuit, a programmable delay chip and a fine-tuning DAC chip, wherein a 10-bit delay control data end is electrically connected with the delay chip through a data bus, and a 6-bit fine-tuning control data end is also electrically connected with the fine-tuning DAC chip through the data bus.

The reference clock circuit and the initial pulse output end are electrically connected to the ECL conditioning circuit, the reference clock is a 200MHz difference ECL clock, the ECL conditioning circuit is used for carrying out ECL level conversion on the initial pulse and synchronizing with the reference clock, the ECL conditioning circuit further comprises a second cycle delay output end used for outputting a second cycle delay pulse, the delay interval Delta T of the second cycle delay pulse is equal to the period of the reference clock, and the delay interval Delta T is integral multiple of the delay interval Delta T.

In this embodiment, the ECL conditioning circuit includes a shift register and a D flip-flop, and a 200MHz reference clock is used as data terminal inputs of the shift register and the D flip-flop, and the ECL shift register controls the initial pulse to shift after N reference clock periods, so as to generate the second cyclic delay pulse.

In the present invention, the generation of the second cyclic delay pulse is not limited to the mode of generating through the shift register and the D flip-flop in this embodiment, and in the prior art, the mode of generating the clock through the internal programming or the logic circuit is applicable to the present invention.

The programmable delay chip comprises:

a delay pulse input electrically connected to the second cyclic delay output;

the fine tuning data port is electrically connected with the fine tuning data output end of the fine tuning DAC chip and used for receiving fine tuning data output by the fine tuning DAC chip;

and the delay pulse output end is used for outputting a third cyclic delay pulse, the delay interval of the third cyclic delay pulse is delta tau, the delay interval delta t is an integral multiple of the delay interval delta tau, and the delay pulse output ends are respectively electrically connected with the three paths of delay pulse output circuits.

The delay pulse output end and the reference clock circuit are electrically connected with the delay pulse output circuit through a second synchronous circuit.

The delay pulse output circuit comprises a differential driver for converting the extension pulse into a differential signal and a pulse driver for synthesizing the differential signal into a single pulse output.

In this embodiment, each of the first and second synchronization circuits includes an and gate chip, the initial pulse or the third cyclic delay pulse and the reference pulse are respectively input to two input ends of the and gate chip, and an output end of the and gate chip is electrically connected to the reference pulse output circuit or the delay pulse output circuit.

The scanning mode of the delay pulse comprises fixed-point resident scanning and large-time-window continuous scanning, and the delay pulse can be transmitted simultaneously or in a time-sharing controllable manner.

1. Fixed-point dwell scanning

The same scanning point can be subjected to resident scanning in a small time window, and the resident function is achieved by increasing the working frequency or reducing the scanning speed. The 10-bit delay control data bus of the delay chip and the 6-bit fine control data bus of the fine control DAC chip keep data unchanged, a reference pulse and a delay pulse generated by an initial pulse signal keep relatively unchanged in time difference, and the time difference of the two pulses is determined by a preset value of the 16-bit data bus. The scanning mode is used for accumulating the energy of the radar feedback signals of the through-wall radar for the target with a fixed distance and monitoring the known target at a fixed point.

2. Continuous scanning with large time window

When the scanning mode is continuous scanning with a large time window, the method needs to be realized by using a double fundamental frequency cyclic delay method. Taking a 2000ns time window as an example, when the delay precision is 2ps, the step scan length value is 1000000.

An FPGA internal program 8-bit addition counter generates an initial pulse signal by using a 50MHz system clock, uses the system clock as a counting clock, uses a scanning end point parameter 100 as a counting final value, adds 1 to a step counting value of each clock rising edge, completes the first cycle delay at intervals of 20ns in a time window, and the delay interval is expressed by delta T.

And a 200MHz reference clock is used as the data end input of a shift register and a D trigger in the ECL conditioning circuit, the clock period is 5ns, the ECL shift register controls the initial pulse to shift after N reference clock periods, the shift takes 5ns as an interval, namely the second cycle delay, and the delay interval is expressed by delta t.

The pulse signals after the first and second cyclic delay are sent to the programmable delay chip as a data end, in this embodiment, the programmable delay chip is a LVPECL level programmable delay chip, which has a fine tuning function, and the FPGA generates delay control data and fine tuning data, which are output to the programmable delay chip and the fine tuning DAC chip through a 10-bit delay control data bus and an outer 6-bit fine tuning control data bus, respectively.

The FPGA control realizes the delay steps as follows:

the first step is as follows: after the first initial pulse signal arrives, the data of the delay control data bus is kept unchanged, the input voltage of a fine tuning pin of the programmable delay chip is adjusted through the fine tuning DAC chip, and the output 2ps of the programmable delay chip is adjusted;

the second step is that: after the second initial pulse signal arrives, the data of the delay control data bus is kept unchanged, the input voltage of a fine tuning pin of the programmable delay chip is adjusted through the fine tuning DAC chip, and the output of the programmable delay chip is adjusted to be 4 ps;

the third step: after the third initial pulse signal arrives, the data of the delay control data bus is kept unchanged, the input voltage of a fine tuning pin of the programmable delay chip is adjusted through the fine tuning DAC chip, and the output 6ps of the programmable delay chip is adjusted;

the fourth step: after the fourth initial pulse signal arrives, the data of the delay control data bus is kept unchanged, the input voltage of a fine tuning pin of the programmable delay chip is adjusted through the fine tuning DAC chip, and the output of the programmable delay chip is adjusted to 8 ps;

the fifth step: and after the fifth initial pulse signal arrives, resetting and fine tuning are carried out, the data of the delay control data bus is controlled to be added by 1, and the output of the delay chip is adjusted to be 10 ps.

The five steps are circulated in sequence, so that the accurate adjustment of the resolution of 2ps is realized, and a third circulation delay pulse with the interval of 2ps is generated, wherein the delay interval is expressed by delta tau.

In this embodiment, the delay pulse signal is synchronized with a 200MHz reference clock, in order to reduce the time jitter caused by the delay circuit, the reference clock source is selected as a 200MHz differential ECL clock, the ECL clock has the advantages of small jitter and high conversion speed, and the selection of such a reference clock can greatly reduce the error caused by the system clock jitter.

The delay pulse output circuit converts the pulse signals after synchronization and delay into differential pulse signals through the differential driver, and the differential pulse signals are synthesized into single pulse signals through the pulse driver, so that the single pulse signals can be used for triggering a next stage of avalanche circuit.

According to different working modes of the radar, under the control of FPGA gating signals, three paths of delay pulses can be sent at the same time or in a time-sharing mode, and time-sharing sending time intervals can be controlled according to the geometric arrangement of through-wall radar receiving antenna arrays.

The foregoing shows and describes the general principles, essential features, and advantages of the invention. It will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, which are described in the specification and illustrated only to illustrate the principle of the present invention, but that various changes and modifications may be made therein without departing from the spirit and scope of the present invention, which fall within the scope of the invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.

Claims (6)

1. The utility model provides a two fundamental frequency three channel time base control circuit of through-wall imaging radar which characterized in that: the FPGA time sequence control circuit comprises an FPGA time sequence control circuit, a programmable time sequence control circuit, a system clock circuit, a reference clock circuit and three paths of delay pulse output circuits which are arranged in parallel;

the FPGA time sequence control circuit comprises an FPGA module, the FPGA module is electrically connected with a system clock circuit, and the FPGA module comprises:

an initial pulse output end, configured to output an initial pulse, where a delay time interval Δ T of the initial pulse is equal to one system clock period;

a 10-bit delay control data terminal for outputting delay data;

a 6-bit fine tuning control data terminal for outputting fine tuning data;

a gating signal output end for outputting a channel gating signal for controlling the gating of the three paths of delay pulse output circuits;

the programmable timing control circuit comprises: the system comprises an ECL conditioning circuit, a programmable delay chip and a fine-tuning DAC chip, wherein a 10-bit delay control data end is electrically connected with the delay chip through a data bus, and a 6-bit fine-tuning control data end is also electrically connected with the fine-tuning DAC chip through the data bus;

the reference clock circuit and the initial pulse output end are electrically connected to the ECL conditioning circuit, and the ECL conditioning circuit is used for carrying out ECL level conversion on the initial pulse and synchronizing with a reference clock;

the ECL conditioning circuit further comprises a second cyclic delay output for outputting a second cyclic delay pulse, wherein a delay interval Δ T of the second cyclic delay pulse is equal to one period of the reference clock, and the delay interval Δ T is an integer multiple of the delay interval Δ T;

the programmable delay chip comprises:

a delay pulse input electrically connected to said second cyclic delay output;

the fine tuning data port is electrically connected with the fine tuning data output end of the fine tuning DAC chip and is used for receiving fine tuning data output by the fine tuning DAC chip;

and the delay pulse output end is used for outputting a third cyclic delay pulse, the delay interval of the third cyclic delay pulse is delta tau, the delay interval delta t is an integral multiple of the delay interval delta tau, and the delay pulse output ends are respectively electrically connected with the three paths of delay pulse output circuits.

2. The through-wall imaging radar double-fundamental-frequency three-channel time base control circuit as claimed in claim 1, wherein: the FPGA module is communicated with an upper computer through an I2C interface.

3. The through-wall imaging radar double-fundamental-frequency three-channel time base control circuit as claimed in claim 1, wherein: the reference clock circuit is an ECL differential clock circuit.

4. The through-wall imaging radar double-fundamental-frequency three-channel time base control circuit as claimed in claim 1, wherein: the initial pulse output end comprises a first output end and a second output end, the first output end is electrically connected with the ECL conditioning circuit, the second output end is electrically connected with the reference clock circuit through a first synchronous circuit and a reference pulse output circuit, and the reference pulse output circuit is used for outputting synchronous initial pulses.

5. The through-wall imaging radar double-fundamental-frequency three-channel time base control circuit as claimed in claim 1, wherein: the delay pulse output end and the reference clock circuit are electrically connected with the delay pulse output circuit through a second synchronous circuit.

6. The through-wall imaging radar double-fundamental-frequency three-channel time base control circuit as claimed in claim 1, wherein: the delay pulse output circuit comprises a differential driver for converting the extension pulse into differential signals and a pulse driver for synthesizing the differential signals into a single pulse to be output.

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