CN112420595A - 半导体器件及其形成方法 - Google Patents

半导体器件及其形成方法 Download PDF

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CN112420595A
CN112420595A CN201910786558.XA CN201910786558A CN112420595A CN 112420595 A CN112420595 A CN 112420595A CN 201910786558 A CN201910786558 A CN 201910786558A CN 112420595 A CN112420595 A CN 112420595A
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dielectric layer
hole
forming
metal layer
layer
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张田田
谭晶晶
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to US16/991,732 priority patent/US11557514B2/en
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Abstract

本发明提供一种半导体器件及其形成方法，其形成方法包括：提供基底，在所述基底上形成介电层；刻蚀所述介电层，在所述介电层内形成通孔，暴露出所述基底表面；对所述通孔侧壁的所述介电层进行表面处理；在所述通孔内填充满金属层；本发明在通孔内填充金属层之前，对通孔侧壁的介电层进行表面处理，提高后续填充的金属层与通孔侧壁的介电层之间的粘附力，金属层和通孔之间具有较好的成形质量，从而提高形成的半导体器件的性能和良率。

Description

半导体器件及其形成方法
技术领域
本发明涉及半导体制造技术领域，尤其涉及一种半导体器件及其形成方法。
背景技术
随着半导体制造技术的飞速发展，半导体器件朝着更高的元件密度，以及更高的集成度的方向发展。器件作为最基本的半导体器件，目前正被广泛应用，传统的平面器件对沟道电流的控制能力变弱，产生短沟道效应而导致漏电流，最终影响半导体器件的电学性能。
在半导体器件的制作过程中，需要在介电层内形成通孔，在通孔内填充金属层以实现晶体管与金属层之间的连接。但是目前形成通孔的过程，由于填充的金属层与通孔之间的粘附力差，金属层与通孔之间具有较差的成形质量，导致在填充金属层的过程中，对通孔下面的器件造成损伤。
如何在通孔内填充质量好的金属层，从而保证形成的半导体器件具有良好的性能，这是目前急需解决的问题。
发明内容
本发明解决的问题是提供一种半导体器件及其形成方法，使得形成的金属层与通孔之间具有较好的成形质量，保证形成的半导体器件具有良好的性能和良率。
为解决上述问题，本发明提供一种半导体器件的形成方法，包括：提供基底，在所述基底上形成介电层；刻蚀所述介电层，在所述介电层内形成通孔，暴露出所述基底表面；对所述通孔侧壁的所述介电层进行表面处理；在所述通孔内填充满金属层。
可选的，所述表面处理的方法为等离子表面处理法或离子掺杂法。
可选的，所述表面处理的类型为表面钌处理或表面钨处理或表面钴处理或表面钛处理。
可选的，所述金属层的材料与所述表面处理的类型相同。
可选的，所述基底上具有导电插塞，所述通孔暴露出所述导电插塞的表面。
可选的，还包括，在形成所述介电层之前，在所述基底上形成刻蚀停止层。
可选的，在所述通孔内填充满金属层之前，刻蚀所述刻蚀停止层，直至暴露出所述导电插塞的表面。
可选的，所述介电层的材料为未掺杂氮的硅化物或掺杂氮的硅化物。
可选的，当所述介电层的材料为未掺杂氮的硅化物时，在对所述通孔侧壁的所述介电层进行表面处理之前，还包括：对所述通孔侧壁的所述介电层进行氮化表面处理。
可选的，形成所述介电层的方法为化学气相沉积法或原子层气相沉积法或物理气相沉积法。
与现有技术相比，本发明的技术方案具有以下优点：
在通孔内填充金属层之前，对通孔侧壁的介电层进行表面处理，提高后续填充的金属层与通孔侧壁的介电层之间的粘附力，使得金属层和通孔之间具有较好的成形质量，从而提高形成的半导体器件的性能和良率。这是由于对通孔侧壁的介电层进行表面处理后，通孔侧壁的介电层的材料性质与填充的金属层的材料的性质差异性小，这样在通孔内填充金属层的时候，金属层和通孔侧壁的介电层就容易结合且粘附力得到提高，从而提高了填充的金属层与通孔侧壁的介电层之间的成形质量，使得形成的半导体器件的性能和良率得到提高。
附图说明
图1至图5是一实施例中半导体器件形成过程的结构示意图；
图6至图11是本发明一实施例中半导体器件形成过程的结构示意图。
具体实施方式
在半导体器件的形成过程中，需要在通孔内填充金属层，以实现晶体管与金属层的电连接。但是在形成通孔内填充金属层后，对填充的金属层进行平坦化的时候，由于填充的金属层与通孔侧壁的介电层之间的粘附力小，在平坦化的时候，外力的作用导致金属层和通孔侧壁的介电层之间剥离开，从而在金属层与通孔侧壁之间有孔洞或缝隙的产生，这样平坦化所用的化学液或产生的杂质等会沿着孔洞或缝隙到达晶体管的表面，从而对晶体管造成损伤，降低了形成的半导体器件的性能和良率，限制了半导体器件的使用，具体的形成过程参考图1至图5。
首先参考图1，提供基底1，所述基底1上形成有层间介质层2，层间介质层2内有接触孔3，在接触孔3内填充第一金属层31。
参考图2，在所述层间介质层2以及所述第一金属层31上形成刻蚀停止层4，在所述刻蚀停止层4上形成介电层5。
参考图3，图形化所述介电层5以及所述刻蚀停止层4直至暴露出所述第一金属层31的表面，形成通孔6。
参考图4，在所述通孔6内填充第二金属层61。
参考图5，平坦化所述第二金属层61，直至所述第二金属层61的顶部表面与所述介电层5的顶部表面齐平。
发明人发现，这种方法形成的半导体器件的使用性能的稳定性差，容易出现失效等现象，限制了半导体器件的使用。这是由于形成的第二金属层61的材料性质与所述介电层5的材料性质相差较大，这样形成的所述第二金属层61和所述介电层5之间不易粘附，且所述第二金属层61与所述介电层5之间的粘附力小，导致所述第二金属层61和所述介电层5之间的成形质量差，在平坦化所述第二金属层61的时候，容易在所述第二金属层61与所述介电层5之间出现剥离的现象，从而导致平坦化过程中的化学液或杂质沿着缝隙或孔洞，到所述第一金属层31的表面，从而对所述第一金属层31造成损伤，使得形成的半导体器件具有较差的性能。
发明人研究发现，在通孔内填充金属层之前，对通孔侧壁的介电层进行表面处理，使得处理后的介电层表面具有与金属层相近的材料性质，这样在通孔内填充金属层的时候，由于金属层和介电层之间的材料性质差异小，金属层和介电层表面容易粘合在一起，从而使得金属层和介电层之间具有较好的成形质量，保证在后续平坦化金属层的过程中，金属层和介电层之间不会发生剥离，从而提高形成的半导体器件的性能和良率。
为使本发明的上述目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施例做详细地说明。
图6至图11是本发明一实施例中半导体器件形成过程的结构示意图。
首先参考图6，提供基底100，在基底100上形成介电层200。
本实施例中，所述基底100包括衬底110，以及位于所述衬底110上的层间介质层120。
本实施例中，所述衬底110上包括位于所述衬底110上存储器件和逻辑器件(图中未示出)。
本实施例中，在所述层间介质层120内形成接触孔，在所述接触孔内填充第一金属层121，形成导电插塞。
本实施例中，在形成所述介电层200之前，在所述基底100上形成刻蚀停止层130。
其他实施例中，还可不在形成所述介电层200之前形成所述刻蚀停止层130。
本实施例中，所述刻蚀停止层130的材料为氮化钨或氮化铝或氮化硅。
本实施例中，在形成所述介电层200之前，形成所述刻蚀停止层130的目的是利用所述刻蚀停止层130对下面的所述衬底110、所述层间介质层120以及第一金属层121(导电插塞)的保护作用，避免所述衬底110、所述层间介质层120以及第一金属层121(导电插塞)在后续的工艺中遭到损伤，从而提高形成的半导体器件的质量。
本实施例中，所述介电层200的材料为未掺杂氮的硅化物，包括氧化硅或碳化硅等；其他实施例中，所述介电层200的材料还可为掺杂氮的硅化物，所述介电层200的材料为氮化硅、氮硼化硅、氮碳氧化硅或氮氧化硅等。
本实施例中，所述介电层200的材料为氧化硅；其他实施例中，所述介电层200的材料还可为碳化硅等。
本实施例中，采用化学气相沉积的方式在所述基底100上形成所述介电层200。所述化学气相沉积工艺的工艺参数包括采用的气体包括氧气、氨气(NH3)、和N(SiH3)3气体，氧气的流量为20sccm～10000sccm，氨气(NH3)气体的流量为20sccm～10000sccm，N(SiH3)3气体的流量为20sccm～10000sccm，腔室压强为0.01～10托，温度为30℃～90℃。
参考图7，刻蚀所述介电层200，在所述介电层200内形成通孔210，暴露出所述刻蚀停止层130的表面。
本实施例中，采用干法刻蚀工艺形成所述通孔210；所述干法刻蚀工艺的参数包括：采用的气体包括CF4和CH3F，CF4的流量为20sccm～200sccm，CH3F的流量为20sccm～50sccm，源射频功率为200瓦～500瓦，腔室压强为1torr～10torr。
其他实施例中，还可采用湿法刻蚀形成所述通孔210。
参考图8，对所述通孔210侧壁的所述介电层200进行氮化表面处理。
图中的箭头表示注入的离子。
本实施例中，由于所述介电层200的材料为氧化硅，是未掺杂氮的硅化物的材料，所以在对所述通孔210侧壁的所述介电层200进行表面处理之前，对所述通孔210侧壁的所述介电层200进行氮化表面处理。
其他实施例中，所述介电层200的材料掺杂氮的硅化物，比如氮化硅，就不需要进行氮化表面处理。
本实施例中，氮化表面处理方法为等离子表面处理法；其他实施例中，氮化表面处理方法还可为离子掺杂法。
本实施例中，所述氮化表面处理的工艺参数包括采用氨气(NH3)作为反应气体，其中，所述氨气(NH3)的气体流量为500～20000sccm；功率为100～2000瓦；腔室压强为2～100毫托。
本实施例中，在进行表面处理之前，进行氮化表面处理的原因是一方面增强所述通孔210侧壁的所述介电层200表面的致密性，提高阻挡作用；另外一方面，对所述通孔210侧壁的所述介电层200表面进行氮化表面处理后，所述介电层200内含有氮化硅，形成的氮化硅可以用作不同材料性质之间的过渡层，从而在对所述介电层200进行表面处理时，能够获得较好的表面处理质量，从而可以获得较高质量的半导体器件。
参考图9，对所述通孔210侧壁的所述介电层200进行表面处理。
图中的箭头表示注入的离子。
本实施例中，表面处理的方法为等离子表面处理法；其他实施例中，表面处理的方法还可为离子掺杂法。
本实施例中，所述表面处理的类型为表面钨(W)处理；其他实施例中，所述表面处理的类型为表面钌(Ru)处理或表面钴(Co)处理或表面钛(Ti)处理。
本实施例中，所述表面处理的类型是指所述通孔210侧壁的所述介电层200在经过表面钌处理或表面钨处理或表面钴处理或表面钛处理后，使得所述通孔210侧壁的所述介电层200具有与金属钌或金属钨或金属钴金属钛相似或相同的材料性质，这样后续进行金属层填充的时候，所述介电层200的材料性质与金属层的性质差异小。
本实施例中，表面钨处理的工艺参数包括：采用的气体包括WF6和氢气，其中，WF6的气体流量为10～1000sccm、氢气的气体流量为50～20000sccm；反应温度为200～400℃；腔室压强为5～100毫托。
本实施例中，所述通孔210侧壁的所述介电层200进行表面钨处理后，所述介电层200的表面具有与金属钨(W)相近或相同的材料性质，为后续在通孔内填充W金属层做准备。
参考图10，沿着所述通孔210的侧壁，刻蚀所述刻蚀停止层130，直至暴露出所述导电插塞121(第一金属层)的表面。
本实施例中，刻蚀所述刻蚀停止层130，直至暴露出所述导电插塞121(第一金属层)的表面，目的是后续填充金属后，实现晶体管和金属层之间的电连接。
参考图11，在所述通孔210内填充满金属层300，并对形成的金属层300进行平坦化，直至所述金属层300的顶部表面与所述介电层200的顶部表面齐平。
所述金属层300的材料与所述表面处理的类型相同。
本实施例中，所述金属层300的材料与所述表面处理的类型相同是指，在经过表面钌处理或表面钨处理或表面钴处理或表面钛处理后的所述通孔210侧壁的所述介电层200的表面具有的材料性质与所述金属层300的材料具有的性质相同或相似。
本实施例中，所述金属层300的材料为钨(W)材料；其他实施例中，所述金属层300的材料还可为Ru或钴(Co)或钛(Ti)。
本实施例中，采用选择性生长法形成所述金属层300；其他实施例中，还可采用化学气相沉积法(CVD)或原子层气相沉积法(ALD)或物理气相沉积法(PVD)形成所述金属层300。
本实施例中，选择性生长法形成所述金属层300的参数包括：反应气体包括WF6气体和H2，其中所述WF6气体的气体流量为50～1000sccm、所述H2的气体流量为500～20000sccm；反应温度为100～400℃；腔室压强为2～100托。
本实施例中，采用选择性生长法形成所述金属层300的原因，一方面是由于选择性生长法形成的所述金属层300是从所述通孔210的底部逐步往上长，形成的所述金属层300的致密性好；另外一方面，由于所述通孔210的侧壁的所述介电层200经过前驱处理，表面带有大量的极性键或电荷等，而所述金属层300的表面也具有大量的极性键或电荷，这样所述金属层300和所述介电层200之间能够相互吸引，从而所述金属层300容易在所述通孔210底部和侧壁生长，从而形成质量好的所述金属层300。
本实施例中，所述前驱处理是对形成所述金属层300之前，对各个面进行处理的工艺。
本实施例中，由于在填充所述金属层300之前，对所述通孔210侧壁的所述介电层200进行表面处理，使得处理后的所述介电层200的表面具有与填充的所述金属层300相同的材料性质，由于所述介电层200表面的材料性质与填充的所述金属层300的材料表面性质差异性小，从而在填充所述金属层300的时候，所述金属层300表面和所述介电层200的表面之间容易粘附在一起，所述金属层300和所述介电层200之间具有较好的形成质量，这样在平坦化所述金属层300的时候，所述金属层300和所述介电层200的表面之间不易发生剥离，从而提高了形成的半导体器件的质量和良率。
本实施例中，形成所述金属层300之后，平坦化所述金属层300之前，对填充的所述金属层300进行退火处理，退火处理的温度在400～450℃，目的是便于填充的所述金属层300与所述通孔210的侧壁形成WN/W-N-Si/WSi的非晶相作为粘结层，很好地将所述金属层300与所述通孔210的侧壁进行粘结，提高所述金属层300和所述通孔210侧壁的所述介电层200之间的粘合力，避免在平坦化所述金属层300的过程中，出现所述介电层200和所述金属层300之间的剥离现象，提高形成的半导体器件的性能和良率。
相应的，利用上述方法，本发明还提供一种半导体器件，包括：基底100，由衬底110和层间介质层120组成，其中，所述层间介质层120位于所述衬底110上；导电插塞由第一金属层121组成，所述第一金属层121，位于所述层间介质层120内；刻蚀停止层130，位于所述层间介质层120上；介电层200，位于所述刻蚀停止层130上；通孔210，位于所述介电层200内，且底部暴露出所述导电插塞121(第一金属层)的表面；金属层300，填充满所述通孔210，且位于导电插塞121(第一金属层)上。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (10)

1.一种半导体器件的形成方法，其特征在于，包括：
提供基底，在所述基底上形成介电层；
刻蚀所述介电层，在所述介电层内形成通孔，暴露出所述基底表面；
对所述通孔侧壁的所述介电层进行表面处理；
在所述通孔内填充满金属层。
2.如权利要求1所述的形成方法，其特征在于，所述表面处理的方法为等离子表面处理法或离子掺杂法。
3.如权利要求1所述的形成方法，其特征在于，所述表面处理的类型为表面钌处理或表面钨处理或表面钴处理或表面钛处理。
4.如权利要求3所述的形成方法，其特征在于，所述金属层的材料与所述表面处理的类型相同。
5.如权利要求1所述的形成方法，其特征在于，所述基底上具有导电插塞，所述通孔暴露出所述导电插塞的表面。
6.如权利要求5所述的形成方法，其特征在于，还包括，在形成所述介电层之前，在所述基底上形成刻蚀停止层。
7.如权利要求6所述的形成方法，其特征在于，在所述通孔内填充满金属层之前，刻蚀所述刻蚀停止层，直至暴露出所述导电插塞的表面。
8.如权利要求1所述的形成方法，其特征在于，所述介电层的材料为未掺杂氮的硅化物或掺杂氮的硅化物。
9.如权利要求8所述的形成方法，其特征在于，当所述介电层的材料为未掺杂氮的硅化物时，在对所述通孔侧壁的所述介电层进行表面处理之前，还包括：对所述通孔侧壁的所述介电层进行氮化表面处理。
10.如权利要求1所述的形成方法，其特征在于，形成所述介电层的方法为化学气相沉积法或原子层气相沉积法或物理气相沉积法。
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