CN112415619A - High-speed big data transmission system, method, terminal and medium based on linear array detector - Google Patents
High-speed big data transmission system, method, terminal and medium based on linear array detector Download PDFInfo
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Abstract
The application provides a high-speed big data transmission system, method, terminal and medium based on a linear array detector, comprising: the control module is used for controlling the work of each module; the transmission module is used for transmitting the object to be detected; the ray source module is used for emitting rays to the transmission module according to the ray control instruction; the detection module is used for receiving rays penetrating through the object to be detected moving on the transmission module and converting the rays into data information formed by connecting digital signals end to end; and the processing and display module is used for processing and displaying the data information. The problems that in the prior art, due to the fact that the load capacity of a single number of acquisition plates is insufficient, a bus analog signal data transmission mode is adopted between a part of detection plates and the number of acquisition plates, long-term stability of a system is not facilitated, the cost of the whole machine is increased and the like are solved, the frame rate can be effectively improved, the requirement of at least 2m/s for the speed of a conveying belt is met, and the competitiveness of a product is improved; and the cost of the whole machine can be reduced, the complexity of system integration is reduced, and the stability of the whole machine system is improved.
Description
Technical Field
The present disclosure relates to the field of linear array detectors, and in particular, to a high-speed big data transmission system, method, terminal and medium based on a linear array detector.
Background
At present, for an X-ray linear array detector, detection plates applied to a security inspection machine are pseudo dual-energy linear array detection with vertically distributed probes (PD sensors). Because the channel type security inspection machine, such as a security inspection gantry or an L-shaped security inspection channel, the channel size and specification are different, and the number of the detection plates required to be cascaded is different. Meanwhile, the required conveyor belt speed and pixel size requirements are different when the detection targets are different, such as luggage, containers, trolleys or other pipelined detection-type items.
In the X-ray linear array detector in the current application, there are clear disadvantages:
(1) higher conveyor belt speed cannot be realized, matching detection can be realized generally under the condition of 0.4m/s, the frame rate of about 10 load detection plates is generally within 1K/s, and the detection requirement of higher conveyor speed cannot be supported;
(2) the wiring mode of data and signals is generally a bus mode, and when the load of a panel is increased, the impedance of a bus is increased due to the fact that the length of a wire is lengthened, the stability of transmission and communication cannot be improved by improving the clock frequency of a control signal, and downward detection of minimum integration time is limited; meanwhile, when the bus mode is applied to the field of security inspection of large-scale channels, due to the fact that the load capacity of a single number of the panels is insufficient, more panels are required to be subjected to external synchronization to be matched, the cost is further increased, and the stability of the system is reduced;
(3) the transmission of data is controlled by adopting a single-ended signal between part of the detection plate and the data acquisition plate, so that the interference of an electromagnetic environment is more easily caused, the data is abnormal or the power supply is abnormal, and the detector is halted;
(4) the bus mode cannot expand the application field, such as belt detection of mines and parcel detection of logistics, and cannot be adapted, because the detection needs to be carried out under high transmission band, the requirement on the minimum integration time under heavy load is higher;
(5) in the cascade sequencing mode among the detection plates, some detection plates need to be independently arranged, for example, non-repeated dial setting is used, and some detection plates at the last of the cascade need to be provided with additional matching resistors to ensure the effectiveness of the cascade; therefore, the working procedures and working hours of the whole machine during assembly are increased, and the repair or replacement use is not facilitated.
Content of application
In view of the above disadvantages of the prior art, an object of the present application is to provide a high-speed big data transmission system, method, terminal and medium based on a linear array detector, which are used to solve the problem that the prior art cannot support the detection requirement of higher transmission speed, the load capacity of a single digital acquisition board is insufficient, more acquisition boards are required to be externally synchronized for matching, the cost is further increased and the stability of the system is reduced, and a mode of transmitting data by bus analog signals is also adopted between part of detection boards and the digital acquisition boards, so that the data is more easily interfered by electromagnetic environment, which causes data abnormality or detector crash, and the overall cost is increased; the long-term stability of the system is not facilitated, and the problems that the detection plates need to be subjected to dial-up sequencing or the last detection plate needs to be terminated with a matching resistor to perform cascade operation are solved.
In order to achieve the above and other related objects, the present application provides a high-speed big data transmission system based on a linear array detector, including: the control module is used for controlling the work of each module; the transmission module is connected with the control module and used for transmitting the object to be detected; the ray source module is connected with the control module and used for emitting rays to the transmission module according to ray control instructions; the detection module is used for receiving rays penetrating through the object to be detected moving on the transmission module and converting the rays into data information formed by connecting digital signals end to end; and the processing and display module is connected with the detection module and used for processing and displaying the data information.
In an embodiment of the present application, the detection module includes: the induction submodule is used for respectively converting the rays acquired in each period into corresponding analog electric signals; the ASCI submodule is used for performing signal digital conversion on the analog electric signal of the current period and outputting a digital signal of the previous period; an FPGA submodule comprising: the digital signal transmission device comprises a plurality of storage units, wherein the storage units are used for receiving the digital signals of the previous period and transmitting the digital signals forward step by step until the digital signals are transmitted to the last stage so as to achieve the end-to-end connection of the digital signals.
In an embodiment of the present application, the ASCI sub-module comprises: the reset unit is used for starting a new integration time sequence of the next cycle; the CDS integral amplification unit is used for carrying out integral amplification on the analog signal of the current period; and the multi-channel data output unit is used for performing signal conversion according to the integral amplification result of the previous period while performing integral amplification and outputting a digital signal of the previous period.
In an embodiment of the present application, the ASCI sub-module further includes: and the serial shifting unit is used for shifting the digital signal of the previous period to the storage unit in the FPGA module.
In an embodiment of the present application, the FPGA sub-module includes: one or more interface units comprising: the output for receiving control signals and data and/or the detection module further comprises: an LVDS signal line module, comprising: and the LVDS pin or pins are connected with the FPGA submodule and are used for carrying out parallel transmission on the plurality of segments of data split in the FPGA submodule.
In order to achieve the above and other related objects, the present application provides a high-speed big data transmission method based on a linear array detector, which is applied to a high-speed big data transmission system based on a linear array detector, the system includes: the control module is used for controlling the work of each module; the transmission module is used for transmitting the object to be detected; the ray source module is used for emitting rays to the transmission module according to the ray control instruction; the method comprises the following steps: receiving rays penetrating the object to be detected moving on the conveying module; and converting the ray into data information formed by connecting all the digital signals end to end.
In an embodiment of the present application, a method of converting the ray into data information formed by connecting the digital signals end to end includes: respectively converting the rays acquired in each period into corresponding analog electric signals; performing digital conversion on the analog electric signal of the current period and outputting a digital signal of the previous period; and receiving the digital signals of the previous period and transmitting the digital signals forward step by step until the digital signals are transmitted to the last stage so as to achieve the end-to-end connection of the digital signals.
In order to achieve the above and other related objects, the present application provides a high-speed big data transmission terminal based on a linear array detector, including: a memory for storing a computer program; and the processor runs the computer program to execute the data transmission method based on the linear array detector.
In order to achieve the above objects and other related objects, the present application provides a computer-readable storage medium storing a computer program, which when executed, implements the method for high-speed big data transmission based on a linear array detector.
As described above, the high-speed big data transmission system, method, terminal and medium based on the linear array detector of the present application have the following beneficial effects:
1. the method has the advantages that smaller integration time is realized under a large load, the frame rate is improved, higher transmission belt speed is matched, and the application field is expanded;
2. the digital transmission has stronger anti-interference performance, reduces the requirement on hardware, can realize high-efficiency transmission by using a common flat wire, and supports higher clock frequency control of a control signal;
3. the method has the advantages that the method can better serve AI automatic identification application following the current 5G trend, and reduces labor cost and artificial misjudgment;
4. the single board loading capacity is stronger, the detection channel width is expanded, and the large and complete target and the target of compatible application are realized; one product can be basically covered, and the development and maintenance cost is reduced;
5. a more stable data transmission mechanism ensures the stability of the FPGA program, reduces the probability of abnormal image acquisition and reduces the risk of frame loss;
6. the detection plates have no cascade sequence requirement, can be combined at will, and reduces the installation and debugging difficulty of the whole machine.
In general, the method provided by the invention can effectively improve the frame rate, realize the requirement of at least 2m/s on the speed of the conveyor belt and improve the competitiveness of products; and the cost of the whole machine can be reduced, the complexity of system integration is reduced, and the stability of the whole machine system is improved.
Drawings
Fig. 1 is a schematic structural diagram of a high-speed big data transmission system based on a linear array detector in an embodiment of the present application.
Fig. 2 is a schematic structural diagram of a detection module in an embodiment of the present application.
Fig. 3 is a schematic diagram illustrating signal conditioning in an ASCI sub-module according to an embodiment of the present invention.
Fig. 4 is a schematic diagram illustrating a data transmission mode according to an embodiment of the present application.
FIG. 5 is a schematic diagram illustrating the transmission of control command signals and digital data channels of each probe module according to an embodiment of the present invention.
Fig. 6 is a schematic diagram illustrating high-speed LVDS data transmission according to an embodiment of the present application.
Fig. 7 is a schematic flowchart illustrating a data transmission method based on a linear array detector in an embodiment of the present application.
Fig. 8 is a schematic structural diagram of a data transmission terminal based on a linear array detector in an embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application is provided by way of specific examples, and other advantages and effects of the present application will be readily apparent to those skilled in the art from the disclosure herein. The present application is capable of other and different embodiments and its several details are capable of modifications and/or changes in various respects, all without departing from the spirit of the present application. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict.
It is noted that in the following description, reference is made to the accompanying drawings which illustrate several embodiments of the present application. It is to be understood that other embodiments may be utilized and that mechanical, structural, electrical, and operational changes may be made without departing from the spirit and scope of the present application. The following detailed description is not to be taken in a limiting sense, and the scope of embodiments of the present application is defined only by the claims of the issued patent. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. Spatially relative terms, such as "upper," "lower," "left," "right," "lower," "below," "lower," "over," "upper," and the like, may be used herein to facilitate describing one element or feature's relationship to another element or feature as illustrated in the figures.
Throughout the specification, when a part is referred to as being "connected" to another part, this includes not only a case of being "directly connected" but also a case of being "indirectly connected" with another element interposed therebetween. In addition, when a certain part is referred to as "including" a certain component, unless otherwise stated, other components are not excluded, but it means that other components may be included.
Also, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context indicates otherwise. It will be further understood that the terms "comprises," "comprising," and/or "comprising," when used in this specification, specify the presence of stated features, operations, elements, components, items, species, and/or groups, but do not preclude the presence, or addition of one or more other features, operations, elements, components, items, species, and/or groups thereof. The terms "or" and/or "as used herein are to be construed as inclusive or meaning any one or any combination. Thus, "A, B or C" or "A, B and/or C" means "any of the following: a; b; c; a and B; a and C; b and C; A. b and C ". An exception to this definition will occur only when a combination of elements, functions or operations are inherently mutually exclusive in some way.
At present, the detection plates applied to the security inspection machine are all pseudo dual-energy linear array detection with vertically distributed probes (PD sensors). Because the channel type security inspection machine, such as a security inspection gantry or an L-shaped security inspection channel, the channel size and specification are different, and the number of the detection plates required to be cascaded is different. Meanwhile, the required conveyor belt speed and pixel size requirements are different when the detection targets are different, such as luggage, containers, trolleys or other pipelined detection-type items.
There is a uniform and big trend in the market today: firstly, the linear array detector is required to reduce the limit of minimum integration time to the maximum extent and match a high-speed transmission belt, so that the detection efficiency is improved; secondly, the number of the load detection plates needs to be increased for one sampling plate, the requirements of different detection channel widths are met, the hardware configuration is reduced, and the cost of the whole machine is reduced; and thirdly, in the field of application of linear array detectors, the adaptive automatic AI identification application under a high frame rate is increasingly required, so that the identification efficiency is improved, and the labor cost is reduced. Therefore, the linear array detector with low speed and small loading of a single plate cannot meet the requirement.
Therefore, the application provides a high-speed big data transmission system based on a linear array detector, which solves the problems that the prior art cannot support the detection requirement of higher transmission speed, the load capacity of a single number of acquisition boards is insufficient, more acquisition boards are required to be matched in an external synchronization manner, the cost is further increased, the stability of the system is reduced, and a single-ended bus is adopted between part of detection boards and the number of acquisition boards for data transmission, so that the data is more easily interfered by an electromagnetic environment, the data is abnormal, even the detector is halted, and the cost of the whole machine is increased; the method is also not beneficial to the long-term stability of the system and the problems that the detection plates need to be dialed and sequenced or the last detection plate needs to be connected with a matching resistor for cascade connection work, and the like, the method can effectively improve the frame rate, meet the requirement of at least 2m/s on the speed of the conveyor belt, and improve the competitiveness of products; and the cost of the whole machine can be reduced, the complexity of system integration is reduced, and the stability of the whole machine system is improved.
The system comprises:
the control module is used for controlling the work of each module;
the transmission module is connected with the control module and used for transmitting the object to be detected;
the ray source module is connected with the control module and used for emitting rays to the transmission module according to ray control instructions;
the detection module is used for receiving rays penetrating through the object to be detected moving on the transmission module and converting the rays into data information formed by connecting digital signals end to end;
and the processing and display module is connected with the detection module and used for processing and displaying the data information.
The following detailed description of the embodiments of the present application will be made with reference to fig. 1 so that those skilled in the art described in the present application can easily implement the embodiments. The present application may be embodied in many different forms and is not limited to the embodiments described herein.
As shown in fig. 1, a schematic structural diagram of a data transmission system based on a linear array detector in an embodiment is shown, where the system includes:
the control module 11 is used for controlling the work of each module;
the transmission module 12 is connected to the control module 11 and is used for transmitting the object to be detected;
the ray source module 13 is connected to the control module 11, and configured to emit a ray to the transmission module according to a ray control instruction;
the detection module 14 is configured to receive the radiation penetrating through the object to be detected moving on the transmission module, and convert the radiation into data information formed by connecting digital signals end to end;
the processing and displaying module 15 is connected to the detecting module 14, and is configured to process and display the data information.
Optionally, the conveying module 12 moves the object to be detected on the conveying module 12 under the control of the control module 11; the movement may be to maintain different speeds or different states of motion. Preferably, the conveying module 12 includes a conveyor belt, and the object to be detected moves at a constant speed on the conveyor belt.
Optionally, when the control module 11 detects that the light barrier signal changes, a ray control instruction is sent to the ray source module. Specifically, the ray control instruction includes: a ray firing instruction and a ray closing instruction.
Alternatively, the radiation source module 13 may emit radiation of various shapes and intensities, and preferably, the radiation source module emits fan-shaped X-rays.
Alternatively, the radiation source module 13 is disposed on the object to be detected which can be moved on the transport module 12, that is, the radiation can penetrate the object to be detected.
Optionally, the detection module 14 is placed at a position where it can receive radiation from the inside of the object to be detected, so as to perform detection.
Optionally, the detection module 14 includes: the induction submodule is used for respectively converting the rays acquired in each period into corresponding analog electric signals; the ASCI submodule is used for performing signal digital conversion on the analog electric signal of the current period and outputting a digital signal of the previous period; an FPGA submodule comprising: the storage unit comprises a plurality of levels and is used for receiving the digital signals of the previous period and transmitting the digital signals forward step by step until the digital signals are transmitted to the last level so as to achieve the end-to-end connection of the digital signals.
In a specific embodiment, in each acquisition period, based on a multi-channel high-speed acquisition chip ASIC of a customized design, analog electric signals inductively converted by a PD sensor are subjected to multi-channel high-speed A/D conversion in an ASCI; the ASCI reads out the digital signal of the previous period while performing integral amplification, and performs caching in the FPGA RAM; the FPGA RAM on each detection board transmits the digital signals to the FPGA RAM at the previous stage step by step and finally caches the digital signals to the FPGA RAM at the last stage; after the data are spliced end to end, the real-time uploading and displaying of the data are completed through a gigabit Ethernet interface; the step-by-step synchronous transmission mode to the previous step not only shortens the transmission distance, but also facilitates the precise transmission and control of the control signal at a higher clock frequency, as shown in fig. 2, which is a schematic structural diagram of the detection module in this embodiment.
Optionally, the ASCI sub-module comprises: the reset unit is used for starting a new integration time sequence of the next cycle; the CDS integral amplification unit is used for carrying out integral amplification on the induction analog signal of the current period; and the multi-channel data output unit is used for performing signal conversion according to the integral amplification result of the previous period while performing integral amplification and outputting a digital signal of the previous period. That is, in each integration period, a signal conditioning flow of "clear reset-CDS mode integration amplification-multi-channel high-speed (LVDS mode) data readout" is included; in all detection plates in the cascade state, each pixel channel on the sensing submodule at the front end is synchronously integrated. Clearing the reset command state change starts the next new integration timing sequence, and simultaneously performs a/D conversion and digital output on the last integration result, as shown in fig. 3 as a signal conditioning schematic diagram in the ASCI sub-module and fig. 4 as a data transmission mode schematic diagram.
Optionally, the ASCI sub-module further comprises: and the serial shifting unit is used for shifting the digital signal of the previous period to the storage unit in the FPGA module.
Optionally, the serial shift unit includes: a serial shift register. The result after signal conversion is stored in the serial shift register and is shifted to a storage unit in the FPGA submodule for caching through N AD clocks; therefore, data from the ASCI submodule is directly shifted to a storage unit in the FPGA submodule, and parallel operation of data output and integration is realized based on the space time-changing principle.
Optionally, the FPGA sub-module includes: one or more interface units comprising: for receiving control signals and output and/or input commands for data. The long-distance transmission of the multiplexed control signals is realized, the quality of the control signals is ensured, and the premise that the data acquisition board realizes large load is also realized; meanwhile, data input and output can be carried out simultaneously under an instruction, and all data received by the data acquisition board are transmitted by the nearest adjacent detection board based on the principle of space time change, so that the risks and the defects (long time consumption, low clock frequency of control signals and poor interference resistance) of a remote transmission technology are avoided. Meanwhile, for the detection plates with the same number of channels, the hardware design is completely consistent, namely, when the detection plates are connected in series to form a longer linear array, the detection plates can be replaced mutually, and the integration and the repair of the whole machine are facilitated.
Optionally, there are two Link interfaces of each detection module 14, and data input and data output may be performed simultaneously under one instruction, and the control signals may also be multiplexed with each other, as shown in fig. 5, which is a schematic transmission diagram of the control instruction signal and the digital data channel of each detection module.
Optionally, the detection module further includes: an LVDS signal line module, comprising: and the LVDS pin or pins are connected with the FPGA submodule and are used for carrying out parallel transmission on the plurality of segments of data split in the FPGA submodule. The data volume of each detection plate is the same and certain, and the transmission mode is the principle that each data is transmitted forward in a serial mode; according to the invention, data is split into N sections of equal data, and parallel transmission of the N sections of data is realized through a plurality of pairs of LVDS, as shown in FIG. 6, a schematic diagram of high-speed LVDS data transmission in the embodiment is shown; based on the principle of space time conversion, the transmission time is reduced by increasing the number of LVDS pins; LVDS pin signals not only exist in ASIC sub-modules, but also exist on each Link interface unit and are butted with FPGA pins.
Optionally, the detection module 14 is a linear array detector.
The system is described below with reference to specific embodiments.
Example 1: the data transmission system is applied to the X-ray linear array detector. The system comprises:
the control module is used for controlling the work of each module;
the conveying belt is connected with the control module and is used for conveying the object to be detected;
the X-ray source is connected with the control module and used for emitting X-rays to the conveyor belt according to a ray control instruction;
the X-ray linear array detector is used for receiving the X-rays penetrating through the object to be detected moving on the conveyor belt and converting the X-rays into data information formed by connecting digital signals end to end;
and the PC and the display are connected with the detector and used for processing and displaying the data information.
The control module controls the conveyor belt to enable the detected object to move on the conveyor belt at a constant speed, when the light barrier signal changes, the control module controls the X-ray source to emit X rays, when the X rays penetrate through the detected object and reach the X-ray linear array detector, the X rays carrying the internal information of the object are received and converted into electric signals by the detector in a line-by-line scanning mode, the data acquisition and transmission system realizes interaction with a PC (personal computer), and post-processing and real-time rolling display of the image are completed; in order to completely splice images, the detection units are connected end to end in the detection direction, the speed of an X-ray imaging area is consistent with the integration time of the X-ray linear array detector, namely the speed of a conveyor belt must be matched with the scanning speed of the X-ray linear array detector, and the following formula is required:
where V is the conveyor speed, D is the pixel spacing, N is the number of pixel combinations (typically 1), T is the integration time, and M is the magnification (typically between 1 and 2).
However, when V is large, i.e. the conveyor belt speed is high, T is correspondingly small, i.e. the scanning frame rate of the X-ray linear array detector is required to be high; an ASIC with customized design is adopted, a plurality of ADC modules are contained in the ASIC, and integral amplification and A/D conversion actions are executed in parallel through an integral time sequence circuit to realize multi-channel high-speed acquisition; when the integral amplification of the current frame is performed, the digital signals of the previous frame are read out simultaneously and are shifted into the FPGA RAM at high speed through a plurality of pairs of LVDS signal lines. The time sequence workflow mode not only ensures the pixel unit on each detection plate, can synchronously acquire moving object information and prevent image distortion, but also can realize smaller shift time consumption through high data clock frequency in an ASIC (application specific integrated circuit), and ensure enough stable X-ray energy response under a small integration period.
Before the next integration period comes, digital signals cached in the FPGA in each level of detection plates need to be gathered into the FPGA on the data acquisition plate for image splicing and packaging, and uploaded to upper computer software for real-time display; the control signal is synchronously issued to each detection plate to realize the transmission of data to the previous stage, and the data is introduced from the data output end to the data input end of the previous detection plate, namely, the data transmission between two adjacent FPGAs is realized through a plurality of pairs of LVDS signal lines; according to the scheme, under the action of the control signal with the ultrahigh clock frequency, a plurality of pairs of LVDS signal wires are used as an auxiliary, the purpose of space time change is achieved, time consumption of transmission is further reduced, and data transmission is stable and reliable.
When data of one frame are gathered to the FPGA of the data acquisition board, the FPGA completes data splicing, at the moment, the RAM cache space of the FPGA is utilized, multi-frame caching can be carried out, the large bandwidth of the gigabit Ethernet is matched, the gigabit Ethernet interface is fully utilized to realize high-speed uploading of digital signals, the multi-frame uploading scheme also compresses non-integral time consumption in a scanning period to a certain extent, meanwhile, the frequency of data interaction between the FPGA and upper computer software is reduced, and the requirement for configuration of the industrial personal computer is lowered.
Similar to the principle of the foregoing embodiments, the present application provides a high-speed big data transmission method based on a linear array detector, which is applied to a high-speed big data transmission system based on a linear array detector, and the system includes: the control module is used for controlling the work of each module; the transmission module is used for transmitting the object to be detected; the ray source module is used for emitting rays to the transmission module according to the ray control instruction; the method comprises the following steps:
receiving rays penetrating the object to be detected moving on the conveying module;
and converting the ray into data information formed by connecting all the digital signals end to end.
Specific embodiments are provided below in conjunction with the attached figures:
fig. 7 is a schematic flow chart showing a high-speed big data transmission method based on a linear array detector in the embodiment of the present application.
The method comprises the following steps:
s701: receiving radiation penetrating the object to be detected moving on the transport module.
Optionally, the transmission module makes the object to be detected move on the transmission module when receiving the transmission control instruction, and when the light barrier signal changes, the control module makes the radiation source emit a radiation ray and receives the radiation ray carrying the internal information of the object.
S702: and converting the ray into data information formed by connecting all the digital signals end to end.
Optionally, the rays acquired in each period are respectively converted into corresponding analog electrical signals; performing signal digitization conversion on the analog electric signal of the current period and outputting a digital signal of the previous period; and receiving the digital signals of the previous period and transmitting the digital signals forward step by step until the digital signals are transmitted to the last stage so as to achieve the end-to-end connection of the digital signals.
Optionally, in each acquisition period, based on a multi-channel high-speed acquisition chip ASIC of a customized design, the analog electrical signal inductively converted by the PD sensor is subjected to multi-channel high-speed a/D conversion in the ASCI; the ASCI reads out the digital signal of the previous period while performing integral amplification, and performs caching in the FPGA RAM; the FPGA RAM on each detection board transmits the digital signals to the previous stage of FPGARAM step by step and finally caches the digital signals to the last stage of FPGA RAM; after the data are spliced end to end, the real-time uploading and displaying of the data are completed through a gigabit Ethernet interface; the step-by-step synchronous transmission mode is adopted, so that the transmission distance is shortened, and the accurate transmission and control of control signals at higher clock frequency are facilitated.
Optionally, starting a new integration time sequence of the next cycle; carrying out integral amplification on the induction analog signal of the current period; performing signal conversion according to the integral amplification result of the previous period while performing integral amplification, and outputting a digital signal of the previous period; that is, in each integration period, a flow of "clear reset-CDS mode integration amplification-multi-channel high-speed (LVDS mode) data readout" is included; in all detection plates in the cascade state, each pixel channel on the sensing submodule at the front end is synchronously integrated. And clearing the change of the reset instruction state, namely starting a new integration time sequence of the next round, and simultaneously carrying out A/D conversion and digital output on the integration result of the last time.
Optionally, the digital signal of the previous period is shifted to a storage unit of an upper stage of the FPGA.
Optionally, the digital signal of the previous period is shifted to the storage unit of the previous stage FPGA through the serial shift register. The result after signal conversion is stored in the serial shift register and is shifted to a storage unit in the FPGA submodule for caching through N AD clocks; therefore, data from the ASCI submodule is directly shifted to a storage unit in the FPGA submodule, and parallel operation of data output and integration is realized based on the space time-changing principle.
Optionally, the control signal and the output and/or input command of the data are received by one or more interface units. The long-distance transmission of the multiplexed control signals is realized, the quality of the control signals is ensured, and the premise that the data acquisition board realizes large load is also realized; meanwhile, data input and output can be carried out simultaneously under an instruction, and all data received by the data acquisition board are transmitted by the nearest adjacent detection board based on the principle of space time change, so that the risks and the defects (long time consumption, low clock frequency of control signals and poor interference resistance) of a remote transmission technology are avoided. Meanwhile, for the detection plates with the same number of channels, the hardware design is completely consistent, namely, when the detection plates are connected in series to form a longer linear array, the detection plates can be replaced mutually, and the integration and the repair of the whole machine are facilitated.
Optionally, the split multiple segments of data are transmitted in parallel through one or more LVDS pins. The data volume of each detection plate is the same and certain, and the transmission mode is the principle that each data is transmitted forward in a serial mode; the data is split into multiple sections of equal data, and the parallel transmission of the multiple sections of data is realized through multiple pairs of LVDS; based on the principle of space time conversion, the transmission time is reduced by increasing the number of LVDS pins; LVDS pin signals not only exist in ASIC sub-modules, but also exist on each Link interface unit and are butted with FPGA pins.
As shown in fig. 8, a schematic structural diagram of a high-speed big data transmission terminal 80 based on a linear array detector in the embodiment of the present application is shown.
The high-speed big data transmission terminal 80 based on the linear array detector includes: a memory 81 and a processor 82, the memory 81 being for storing computer programs; the processor 82 runs a computer program to implement the data transmission method based on the linear array detector as shown in fig. 1.
Optionally, the number of the memories 81 may be one or more, and the number of the processors 82 may be one or more, and fig. 8 is an example.
Optionally, the processor 82 in the high-speed large data transmission terminal 80 based on the linear array detector loads one or more instructions corresponding to the process of the application program into the memory 81 according to the steps described in fig. 7, and the processor 82 runs the application program stored in the memory 81, so as to implement various functions in the data transmission method based on the linear array detector described in fig. 7.
Optionally, the memory 81 may include, but is not limited to, a high speed random access memory, a non-volatile memory. Such as one or more magnetic disk storage devices, flash memory devices, or other non-volatile solid-state storage devices; the Processor 81 may include, but is not limited to, a Central Processing Unit (CPU), a Network Processor (NP), and the like; the Integrated Circuit may also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other Programmable logic device, a discrete Gate or transistor logic device, or a discrete hardware component.
Optionally, the Processor 82 may be a general-purpose Processor, and includes a Central Processing Unit (CPU), a Network Processor (NP), and the like; the Integrated Circuit may also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other Programmable logic device, a discrete Gate or transistor logic device, or a discrete hardware component.
The present application further provides a computer-readable storage medium, in which a computer program is stored, and when the computer program runs, the data transmission method based on the linear array detector as shown in fig. 7 is implemented. The computer-readable storage medium may include, but is not limited to, floppy diskettes, optical disks, CD-ROMs (compact disc-read only memories), magneto-optical disks, ROMs (read-only memories), RAMs (random access memories), EPROMs (erasable programmable read only memories), EEPROMs (electrically erasable programmable read only memories), magnetic or optical cards, flash memory, or other type of media/machine-readable medium suitable for storing machine-executable instructions. The computer readable storage medium may be a product that is not accessed by the computer device or may be a component that is used by an accessed computer device.
In summary, the high-speed big data transmission system, the method, the terminal and the medium based on the linear array detector solve the problems that the detection requirement of higher transmission speed cannot be supported in the prior art, the load capacity of a single acquisition board is insufficient, more acquisition boards are required to be matched only by external synchronization, the cost is further increased, the stability of the system is reduced, a mode of bus single-end data transmission is adopted between part of detection boards and the acquisition boards, the data is more easily interfered by an electromagnetic environment, the data is abnormal and even the detector is halted, and the cost of the whole machine is increased; the method is also not beneficial to the long-term stability of the system and the problems that the detection plates need to be dialed and sequenced or the last detection plate needs to be connected with a matching resistor for cascade connection work, and the like, the method can effectively improve the frame rate, meet the requirement of at least 2m/s on the speed of the conveyor belt, and improve the competitiveness of products; and the cost of the whole machine can be reduced, the complexity of system integration is reduced, and the stability of the whole machine system is improved. Therefore, the application effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles and utilities of the present application and are not intended to limit the application. Any person skilled in the art can modify or change the above-described embodiments without departing from the spirit and scope of the present application. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical concepts disclosed in the present application shall be covered by the claims of the present application.
Claims (10)
1. A high-speed big data transmission system based on linear array detector, characterized in that, the system includes:
the control module is used for controlling the work of each module;
the transmission module is connected with the control module and used for transmitting the object to be detected;
the ray source module is connected with the control module and used for emitting rays to the transmission module according to ray control instructions;
the detection module is used for receiving rays penetrating through the object to be detected moving on the transmission module and converting the rays into data information formed by connecting digital signals end to end;
and the processing and display module is connected with the detection module and used for processing and displaying the data information.
2. The high-speed big data transmission method based on the linear array detector as claimed in claim 1, wherein the detection module comprises:
the ray sensing submodule is used for respectively converting the rays acquired in each period into corresponding analog electric signals;
the ASCI submodule is used for performing signal conversion on the analog electric signal input in the current period and outputting an A/D converted digital signal in the previous period;
an FPGA submodule comprising: the storage unit comprises a plurality of levels and is used for receiving the digital signals of the previous period and transmitting the digital signals to the previous level step by step until the digital signals are transmitted to the last level so as to achieve the end-to-end connection of the digital signals.
3. The high-speed big data transmission method based on the linear array detector as claimed in claim 2, wherein the ASCI sub-module comprises:
the reset unit is used for starting a new integration time sequence of the next cycle;
the CDS integral amplification unit is used for carrying out integral amplification on the induction analog signal of the current period;
and the multi-channel data output unit is used for performing digital conversion on signals according to the integral amplification result of the previous period while performing integral amplification, and outputting the digital signals of the previous period.
4. The linear array detector-based high-speed big data transmission method according to claim 2, wherein the ASCI sub-module further comprises:
and the serial shifting unit is used for shifting the digital signal of the previous period to the storage unit in the FPGA module.
5. The high-speed big data transmission method based on the linear array detector as claimed in claim 3, wherein the FPGA sub-module comprises: a plurality of interface units comprising: for receiving control signals and output and/or input commands for data.
6. The high-speed big data transmission method based on the linear array detector as claimed in claim 1, wherein the detection module further comprises: an LVDS signal line module, comprising: and the LVDS pin or pins are connected with the FPGA submodule and are used for carrying out parallel transmission on the plurality of segments of data split in the FPGA submodule.
7. A high-speed big data transmission method based on a linear array detector is characterized in that the method is applied to a high-speed data transmission system based on the linear array detector, and the system comprises the following components: the control module is used for controlling the work of each module; the transmission module is used for transmitting the object to be detected; the ray source module is used for emitting rays to the transmission module according to the ray control instruction; the method comprises the following steps:
receiving rays penetrating the object to be detected moving on the conveying module;
and converting the ray into data information formed by connecting all the digital signals end to end.
8. The linear array detector-based high-speed big data transmission method according to claim 7, wherein the manner of converting the rays into data information formed by connecting digital signals end to end comprises:
respectively converting the rays acquired in each period into corresponding analog electric signals;
performing digital signal conversion on the analog electric signal of the current period and outputting a digital signal of the previous period;
and receiving the digital signals of the previous period and transmitting the digital signals to the previous stage step by step until the digital signals are transmitted to the last stage so as to achieve the end-to-end connection of the digital signals.
9. The utility model provides a high-speed big data transmission terminal based on linear array detector which characterized in that includes:
a memory for storing a computer program;
a processor for operating the computer program to execute the high-speed large data transmission method based on the line detector as claimed in any one of claims 6 to 7.
10. A computer storage medium, characterized in that a computer program is stored, and when the computer program runs, the method for transmitting high-speed big data based on a linear array detector according to any one of claims 6 to 7 is implemented.
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| PCT/CN2021/115929 WO2022052845A1 (en) | 2020-09-14 | 2021-09-01 | Linear array detector-based high-speed big data transmission system and method, terminal, and medium |
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