RU98311U1 - ELECTRONIC INFRARED IMAGE VISUALIZATION SYSTEM FOR MATRIX THERMAL IMAGERS - Google Patents

Abstract

 1. An electronic infrared image visualization system for matrix thermal imagers, comprising a signal pre-processing module and a digital signal processing module, characterized in that it is additionally equipped with a power supply module, said modules being made on separate boards and grouped into sets according to their functional purpose, a set of signal processing modules as part of a signal preprocessing module and a digital signal processing module, a set of electric power modules As part of the power supply module, each module is equipped with a microcontroller or microprocessor, through which all modules are end-to-end through the TWI interface, in accordance with the functionality of the modules to them from the power supply module, the voltage is traced with the end-to-end coverage of the modules in the set, with the formation of interdependent power circuits, in the set of signal processing modules between the signal preprocessing module and the digital signal processing module signal chains - control, data transmission and addresses in the form of a standard stream. ! 2. The electronic system according to claim 1, characterized in that in addition to the sets of signal processing and electric power supply modules, it additionally contains a set of control modules for the thermal imager executive systems, a microcontroller is made in each module, through the latter, the modules are end-to-end via TWI interface, in accordance with the functional the availability of the modules to them from the power supply module, the voltage tracing was performed

Description

The invention relates to a technique that registers in the infrared (IR) range of radiation, in particular, infrared image visualization systems, and can be used in thermal imagers designed for visual observation of thermal images of various objects by means of non-contact optical-digital registration of intrinsic and reflected thermal radiation and display thermal portrait in the visualization unit.

Known electronic imaging system for infrared images for matrix thermal imagers (RF patent No. 2066057 for the invention, IPC: 6 H04N 5/33), made in the following composition. Optical-mechanical unit with sources of the first and second reference radiation, optically coupled to a matrix photodetector. The signal preprocessing unit, the input of which is electrically connected to the matrix photodetector. A node for sampling the address and synchronizing the reading of signals from elements of the matrix photodetector containing a clock synchronizer electrically connected to the matrix photodetector, and an address counter with an input connected to a sync generator. A node for generating a code for compensating the background signal and signal drift for each photosensitive element of the matrix photodetector made as part of a random access memory block for storing the code for compensating the background signal and signal drift, a digital-to-analog converter (DAC), a reversible counter, an adder, a comparator, and a bus with zero voltage. At the same time, the multi-bit input of the RAM block for storing the compensation code for the background signal and signal drift is electrically connected to the node for selecting the address and synchronizing the reading of signals from the elements of the matrix photodetector, and its multi-bit output is connected to the multi-bit input of the reverse counter and DAC. The multi-bit output of the reversible counter is connected to the multi-bit input of the DAC and the multi-bit output of the RAM block to store the code for compensating the background signal and signal drift. The DAC output is connected to one of the inputs of the adder, the second input of which is connected to the output of the signal preprocessing unit. The output of the adder is connected to one of the inputs of the comparator, the second input of which is connected to the bus with zero voltage, and the output of the comparator is connected to the second input of the reversible counter. The device also has a node for generating a sensitivity correction code for each element of the matrix photodetector as part of a random access memory block for storing the sensitivity correction code, second DAC, second reverse counter, amplifier, second comparator, and reference voltage source. In this case, the multi-bit input of the random access memory block for storing the sensitivity correction code is electrically connected to the node for selecting the address and synchronizing the reading of signals from the elements of the matrix photodetector, and its multi-bit output is connected to the multi-bit input of the second reversible counter and the second DAC. The multi-bit output of the second reversible counter is connected to the multi-bit input of the second DAC and the multi-bit output of the RAM block for storing the sensitivity correction code. The output of the second DAC is connected to one of the inputs of the amplifier, the second input of which is connected to the output of the adder of the formation unit of the compensation code for the background signal and signal drift. The output of the amplifier is connected to one of the inputs of the second comparator, the second input of which is connected to a reference voltage source, and the output of the second comparator is connected to the second input of the second reversible counter. The amplifier output is designed to pick up the processed signals of the matrix photodetector. The signal preprocessing unit is configured to amplify, integrate, filter, and bias samples. The amplifier is made with the function of regulating the transmission coefficient.

The disadvantages of the known system include, firstly, insufficiently high reliability, secondly, the limitation of the possibilities of using the system in relation to the range of thermal imagers, insufficient unification, and thirdly, the high specific labor intensity during operation. The reasons for the shortcomings are as follows.

The system is characterized by a narrow functionality and low bandwidth in signal processing. Computational actions when generating a compensation code for the background signal and signal drift for each photosensitive element of the matrix photodetector and generating a sensitivity correction code for each photosensitive element of the matrix photodetector are carried out based on the use of analog elements, which, due to the limited bandwidth of the DAC and ADC, significantly reduces the possible functions. In addition, the system does not allow to realize the possibility of artificial restoration of signals from defective elements, which is one of the most important features of signal processing of a matrix photodetector. The system is characterized by the significance of mass and dimensions. Moreover, each node of the system has individual nodes of the formation of supply voltages from the total supply voltage of the system, which not only increases its mass and dimensions, but also increases the release of heat into the environment, provides additional restrictions on the use of the system in the construction of a thermal imaging device. This feature also leads to an increase in the overall energy consumption of the system as a whole.

A known technical solution, chosen as the closest analogue, is an electronic infrared image visualization system for matrix thermal imagers (I.I. Kremis, Yu.F. Only. Unified signal processing system of a multi-element infrared photodetector based on a FPGA / programmable logic chip / Applied Physics, 2007, No. 4, pp. 133-140), containing a signal preprocessing module and a digital signal processing module. The signal preprocessing module contains an amplifier, ADC, a circuit that provides the signals necessary for the operation of the photodetector, which generates control signals of the photodetector switch and provides the required supply voltage and photodetector bias. The digital signal processing module contains a microcontroller, FPGA, random access memory (RAM), read-only memory (ROM), digital-to-analog converter (DAC). The data exchange of the signal preprocessing module and the digital signal processing module occurs through a data preparation circuit that provides the transmission of digital streams in a given format.

The disadvantages of the nearest analogue include, firstly, insufficiently high reliability, secondly, the limitation of the possibilities of using the system in relation to the range of thermal imagers, insufficient unification, and thirdly, high specific labor intensity during operation. The reasons for the shortcomings are as follows.

The system is characterized by the individualization of functional units, in particular, the individualization of the supply voltage of the system modules, data transfer interfaces between the system modules, the absence of a unified control and management system for the modules. The system was built strictly on the basis of the size of a photodetector selected from a number of promising ones, having an output signal format with a minimum number of pixels per frame. When using other photodetectors with a different number of photocells, there is a need to add additional boards with the necessary resources. In this regard, the system is characterized not only by the lack of unification, but also reduced reliability and increased specific labor intensity during its operation.

The technical result of the utility model is:

- increased reliability;

- expanding the possibilities of using the system in relation to the range of thermal imagers, increasing unification;

- reduction of specific labor intensity during operation of the electronic system.

The technical result is achieved in that in an electronic infrared visualization system for matrix thermal imagers, comprising a signal pre-processing module and a digital signal processing module, additionally equipped with a power supply module, said modules being made on separate boards and grouped into sets according to their functional purpose , a set of signal processing modules as part of a signal preprocessing module and a digital signal processing module, a set of modules electrical power as part of the power supply module, in each module there is a microcontroller or microprocessor, through which all modules are end-to-end through the TWI interface, in accordance with the functionality of the modules to them from the power supply module, voltage tracing is performed with the end-to-end coverage of the modules in the set, with the formation of interdependent power circuits in the set of signal processing modules between the signal preprocessing module and the digital signal processing module the channels are implemented signal chains - control, data transmission and addresses in the form of a standard stream.

In the electronic system, in addition to the sets of signal processing and electric power supply modules, it additionally contains a set of control modules for thermal imager executive systems, a microcontroller is made in each module, through the latter, the modules are end-to-end via TWI interface, in accordance with the functionality of the modules to them from the power supply module, tracing is performed supply voltages with end-to-end coverage of the modules in the set, with the formation of interdependent supply circuits.

In the electronic system, in addition to the sets of signal processing and power supply modules, it additionally contains a set of control modules for thermal imager executive systems, made as part of the optical system control module and scanning control module, a microcontroller is made in each module, through which the modules are end-to-end via TWI interface, in accordance with the functionality of the modules to them from the power supply module, a trace of the supply voltage with through the coverage of the modules in the set, with the formation of interdependent power circuits, in the set of control modules for executive systems between the optical system control module and the scan control module, signal chains are implemented - control buses, data transmission and addresses.

In the electronic system, in the set of signal processing modules as part of the signal preprocessing module and digital signal processing module and the set of electric power modules as part of the power supply module, the microcontroller is made in the signal preprocessing module and the power source module, the microprocessor is made in the digital signal processing module; in the set of signal processing modules between the signal preprocessing module and the digital signal processing module, the signal chains are implemented - control, data and address transmission, namely, the LVDS channel, the signal preprocessing module is equipped with bi-directional control, data and address buses that connect it to the matrix photodetector, the digital signal processing module is equipped with buses for displaying images on a television monitor, the digital signal processing module is also equipped with a control interface electronic system; in accordance with the functional purpose of the modules in the set of signal processing modules for them from the power supply module, the voltage was traced with the through coverage of the modules in the set, with the formation of interdependent power circuits, namely, sequentially from the power supply module to the digital signal processing module, from the module digital signal processing to the signal preprocessing module, from the signal preprocessing module to the matrix photodetector.

In the electronic system, in the power supply module, power connectors are made based on the grouping of system modules into sets in accordance with their functional purpose and in an amount equal to the number of sets of modules.

In an electronic system, the power supply module is equipped with one or more power connectors, in an amount equal to the number of sets of modules into which the latter are grouped according to their functional purpose, excluding from the specified number of module sets the set of electric power modules, which includes the power supply module, each module, in addition to the power supply module, is equipped with two power connectors, connectors are standard for all modules, one of the connectors of a particular module is directly connected to union of the module power source, the second connector is configured to supply trace from the power supply module to other modules of the feature set is also available in all power supply system provided with two connectors contacts TWI interface.

In the electronic system, in each module, from the sets into which the modules are grouped in accordance with their functional purpose, without taking into account the set of electric power modules, which comprise the power supply module, voltage sources with a power of up to 0.6 W with a total power dissipation are formed up to 0.1 W in the form of heat from the elements forming the voltage source.

In an electronic system, the supply voltage from the power supply module for each module associated with other modules of the system not only through the TWI interface, but also by the signal, control, data and address signal circuits, is implemented through the module that is most optimally located in the system relative to the power source, - closest to the power supply module, taking into account the electromagnetic compatibility of the modules relative to each other.

In the electronic system, the digital signal processing module for connecting additional modules is equipped with expansion slots as part of one or several single-row connectors located along the perimeter of the module board and close to the edge of the board, with the number of connector pins corresponding to the number of signal lines ensuring the operability of the connected expansion cards - additional modules.

In the electronic system, the signal preprocessing module is made up of a microcontroller, an analog-to-digital converter, a reference voltage source, a programmable logic integrated circuit, a synchronous dynamic random access memory, an LVDS chip, while the microcontroller is connected to the reference power source via buses and connected to a programmable logic integrated circuit via bi-directional buses, analog-to-digital converter associated with matrix photodetector By means of bi-directional buses, by means of bidirectional buses it is connected with a programmable logic integrated circuit, the latter is connected by bidirectional control circuits with a matrix photo-successor multiplexer, and it is also connected by bidirectional buses with a synchronous dynamic random-access memory and connected by bidirectional buses with an LVDS chip that prepares exchange data over signal chains - control, data and address transmission, namely, on the LVDS channel, the reference voltage source is connected by power circuits matrix photodetector.

In the electronic system, the digital signal processing module is made up of a microprocessor, a programmable logic integrated circuit, a synchronous dynamic random access memory for storing defective elements, a synchronous dynamic random access memory for storing the coefficients of the heterogeneous sensitivity of the elements, a synchronous dynamic random access memory for storing the coefficients of correction of the dark background, synchronous dynamic operational a memory device for storing intermediate data, a television memory from the first synchronous dynamic random access memory of the image data and the second synchronous dynamic random access memory of the image data, flash memory, electrically reprogrammable read only memory, digital-to-analog converter, while on the basis of a programmable logic integrated circuit implemented the initial processing node, carrying out its own image processing functions, and the final digital processing unit, which replaces defective elements, an intermediate digital processing unit, which accumulates full-format image arrays and performs processing functions on them, is implemented on the basis of the microprocessor, the initial digital processing unit is implemented as part of an arithmetic-logic device, which is a programmable component logical integrated circuit configured to receive on it through a chain of signals - control, transmission d data and addresses, namely, the LVDS channel, digital data for processing and connected by bidirectional buses with a memory controller, also a component of a programmable logic integrated circuit, synchronous dynamic random access memory storage device for defective elements connected by individual bidirectional buses with the specified memory controller, synchronous dynamic random access memory storage device for the correction coefficients of the heterogeneous sensitivity of the elements associated individual bi-directional buses with the specified memory controller, synchronous dynamic random access memory storage device for correcting the dark background associated with individual bi-directional buses with the specified memory controller, television memory as part of the first synchronous dynamic random access memory image data storage and the second synchronous dynamic random access memory data storage device images connected to the specified to the memory controller by means of individual bi-directional buses of the first and second synchronous dynamic random-access memory devices for storing image data, configured to switch them with a frame rate of a television monitor, the intermediate digital processing unit is made up of a microprocessor directly connected to the specified memory controller and synchronous dynamic random-access memory intermediate data storage device via common address and data buses, etc. and to achieve the possibility of accessing the programmable logic integrated circuit to a synchronous dynamic random access memory for storing intermediate data and the possibility of accessing it by a microprocessor and programmable logic integrated circuit for writing and reading data, the microprocessor outputs are implemented with the ability to switch them to the third state, also in the intermediate node digital processing performed flash memory connected bidirectional buses with a microprocessor, and electric SKI reprogrammable read-only memory connected by bi-directional buses with a microprocessor, the final digital processing unit is made up of components sequentially connected to the indicated memory controller via the buses of the defective element replacement unit, the television generator, the brightness and contrast adjustment unit, the service symbol generation unit, the digital filtering unit, which are components of a programmable logic integrated circuit, each of these components being associated with seemed memory controller bidirectional buses finally with digital filtering assembly associated tires digital-analog converter supplying the image signals for output to a television monitor.

In the electronic system, the power supply module is made up of a microcontroller connected by bi-directional buses to the power supply converter, which converts the input voltage supplied through the power supply circuits to the output voltages supplied through the power supply circuits from the power supply module to other modules.

In the electronic system, the optical system control module is made up of a microcontroller, a programmable logic integrated circuit, an electric drive control circuit, flash memory, an electrically reprogrammable read-only memory device, a microcontroller connected by bi-directional buses to a programmable logic integrated circuit, which, in turn, is connected to the circuit electric drive control, the microcontroller is connected by bidirectional buses to flash memory and is connected by other bidirectional buses and electrically reprogrammable read only memory, the drive control circuit is provided with bidirectional signals flow to the tires scanning control module.

In the electronic system, the scanning control module is made up of a microcontroller, a programmable logic integrated circuit, a control field bias drive, flash memory, an electrically reprogrammable read-only memory, the microcontroller is connected by bi-directional buses with a programmable logic integrated circuit, which, in turn, is connected with the control circuit of the offset field drive, the microcontroller is connected by bidirectional buses with flash memory and is connected by other unapravlennymi tires with an electrically reprogrammable read-only memory, the field of view offset drive control circuit is provided with bidirectional buses supplying signals to the control module of the optical system.

The essence of the utility model is illustrated by the following description and the accompanying figures.

Figure 1 shows a block diagram of an electronic infrared image visualization system for matrix thermal imagers, where 1 is a signal preprocessing module; 2 - digital signal processing module; 3 - power supply module; 4 microcontroller; 5 - microprocessor; 6 - microcontroller; 7 - optical system control module; 8 - microcontroller; 9 - scanning control module; 10 - microcontroller; 11 - matrix photodetector; 12 - television monitor; 13 - power circuit; 14 - tires; 15 - channel LVDS (low-voltage differential signaling); 16 - TWI interface (Two-Wire Interface); 17 - power circuit; 18 - TWI interface; 19 - power circuit; 20 - TWI interface; 21 - power circuit; 22 - TWI interface; 23 - power circuit; 24 - tires; 25 - power circuit.

Figure 2 shows a block diagram of a signal preprocessing module, where 1 is a signal preprocessing module; 6 - microcontroller; 13 - power circuit; 14 - tires; 15 - channel LVDS; 16 - TWI interface; 17 - power circuit; 26 - ADC; 27 - voltage reference source; 28 - FPGA; 29 - SDRAM (synchronous dynamic random access memory); 30 - LVDS chip; 31, 32, 33, 34, 35 - tires.

Figure 3 shows a block diagram of a digital signal processing module, where 2 is a digital signal processing module; 5 - microprocessor; 15 - channel LVDS; 16 - TWI interface; 18 - TWI interface; 19 - power circuit; 36 - FPGA; 37 - SDRAM (synchronous dynamic random access memory storage device for defective items); 38 - SDRAM (synchronous dynamic random-access memory device for storing the correction coefficients of the heterogeneous sensitivity of the elements); 39 - SDRAM (synchronous dynamic random access memory storage device for the coefficients of the correction of the dark background); 40 - SDRAM (synchronous dynamic random access memory storage device intermediate, microprocessor - FPGA, data); 41 - SDRAM (first synchronous dynamic random access memory device for storing image data); 42 - SDRAM (second synchronous dynamic random access memory device for storing image data); 43 - flash memory, 44 - EEPROM (electrically reprogrammable read-only memory), 45 - defective element replacement unit; 46 - television generator; 47 - node brightness and contrast; 48 - node forming characters; 49 - digital filtering unit; 50 - digital-to-analog converter (DAC); 51 - ALU (arithmetic-logical device); 52 - memory controller; 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72 - tires.

Figure 4 shows a block diagram of a power supply module, where 3 is a power supply module; 4 - microcontroller; 18 - TWI interface; 19 - power circuit; 20 - TWI interface; 21 - power circuit; 25 - power circuit; 73 - converter power source; 74 - tires.

Figure 5 shows a block diagram of an optical system control module, where 7 is an optical system control module; 8 - microcontroller; 20 - TWI interface; 21 - power circuit; 22 - TWI interface; 23 - power circuit; 24 - tires; 75 - FPGA; 76 electric drive control circuit; 77 - flash memory; 78 - EEPROM (Electrically Reprogrammable Read-Only Memory); 79, 80, 81, 82 - tires.

Figure 6 shows a block diagram of a scan control module, where 9 is a scan control module; 10 - microcontroller; 22 - TWI interface; 23 - power circuit; 24 - tires; 83 - FPGA; 84 a control circuit for shifting the field of view; 85 - flash memory; 86 - EEPROM (Electrically Reprogrammable Read-Only Memory); 87, 88, 89, 90 - tires.

The achievement of the technical result in the proposed utility model is as follows.

The electronic infrared image visualization system for matrix thermal imagers is implemented on the basis of functional modules made by individual boards containing a microcontroller or microprocessor, thanks to which the modules are connected in the system via the TWI interface (Two-Wire Interface), which manage and test the modules. In this case, the power supply circuits of the modules are organized in accordance with their functional purpose, and the modules are grouped according to their functional purpose into sets; in each set, signal circuits are implemented between the modules — data, control and address transmission circuits. Data transmission circuits can be implemented in the form of any interface optimal for the system, for example, LVDS, or RS 422 (bidirectional serial interface for exchanging byte information), or any other, both serial and parallel.

The modules are grouped into the following separate functional sets: a set of signal processing modules; set of electrical power modules; a set of control modules for executive systems of a thermal imager (see Figure 1). All modules in these sets are physically separated and made in the form of separate boards. Each module is a functionally complete device, for the commissioning of which does not require the assembly of the entire system as a whole.

Moreover, a specific functional module can be performed as part of the main, or the main and additional, or the main and several additional boards. All supply and control voltages go to the main board, and on the main board there is a microcontroller (microprocessor) that controls this module and is connected to other modules via the TWI interface. The connection of all modules of the given sets is implemented through the TWI interface through microcontrollers (microprocessors) of the main boards in an end-to-end manner. Tracing of the supply voltages from the main board of the set of electric power supply modules is performed with an end-to-end coverage of all modules with respect to each set - signal processing modules and control modules of the thermal imager executive systems, with the formation of interdependent power circuits. In each set, the modules, since they perform the functions assigned to them in the aggregate, are connected by interdependent signal chains.

Depending on the requirements for a particular thermal imager, in the infrared image visualization system, all three of the above sets of modules are performed (as shown in FIG. 1) or a set of signal processing modules and a set of electric power modules are performed. The last two sets serve as the basic set of module sets, necessary and sufficient to provide visualization of the infrared image of the thermal imager. The presence of a set of control modules for executive systems of a thermal imager is not necessary to ensure image visualization, this set of modules can be present in the system and can be implemented in one or another configuration corresponding to the task to be solved, the use of a thermal imager is aimed at solving it. Additional modules are used to perform additional functions in the device that are not necessary and mandatory for the operation of the device, but improve the technical characteristics of the device as a whole and allow expanding the capabilities of the device.

Thus, in the basic version, the electronic infrared image visualization system for the matrix thermal imager is made up of a set of signal processing modules, namely, a signal preprocessing module and a digital signal processing module, and a set of electric power modules containing a power supply module in each specified module a microcontroller or microprocessor is made, these modules are connected through microcontrollers and a microprocessor available in each of the modules via the TWI interface, between Odulov preprocessing signals and digital signal processing module implemented LVDS channel - chain signals sequentially from the supply module to the digital signal processing and from the latter to the modulo pre-processing and further to a matrix imager arranged supply circuit. From the digital signal processing module along the signal circuits, the rendered image is displayed on a television monitor.

The modular construction of the visualization system allows the addition of any functional modules in order to meet the requirements for a specific thermal imager.

Each module, regardless of its belonging to a specific set of modules, has a microcontroller or microprocessor, depending on the specific functions performed by the module, its intended use. Based on a microcontroller or microprocessor, a TWI interface is implemented. The specified interface is used to test the modules and control the modules by the central processor - microprocessor. The central processor is made in a digital signal processing module.

The digital signal processing module is equipped with system control interfaces (see Figure 1), for example, USB 2.0 interface (USB is a serial data transfer interface for medium and low speed peripherals in computer technology), RS 232 (bidirectional serial interface for byte exchange information) or other similar means by which control and transmission of data to the operator from the specified module is carried out.

The power connectors of the power supply module are based on the partition of the electronic system into functional sets. Here, one or more power connectors can be made in accordance with the available functional directions.

In the General case, the implementation of an electronic system for visualizing infrared images for matrix thermal imagers, it contains (Figure 1): a module for preliminary signal processing (1), a digital signal processing module (2), a power supply module (3), a microcontroller (4) in the source module power supply, microprocessor (5) in the digital signal processing module, microcontroller (6) in the signal preprocessing module. Additionally, the electronic imaging system can be equipped with an optical system control module (7), which includes a microcontroller (8), and a scan control module (9), which includes a microcontroller (10). These modules are made in the form of separate boards.

A matrix photodetector (11) is registered with a set of signal processing modules, which detects infrared radiation from the object being monitored, - with a signal preprocessing module board (1) via power circuits (13) and buses (14), and a television monitor (12), which displays after digital processing, the visualized IR image - with the board of the module for digital signal processing via buses. Between the signal preprocessing module (1) and the digital signal processing module (2), the LVDS channel (15) is made, which provides data exchange between the signal preprocessing module (1) and the digital signal processing module (2) To reduce the number and width of digital buses, standard digital stream adopted for data exchange within the considered module of the system, which positively affects the mass-dimensional indicators and reliability indicators of the system as a whole. The data exchange between the signal processing modules is brought to a single standard, which is adopted for a particular system.

Each of the modules (1), (2), (3), (7), (9) is equipped, depending on the function it performs, with a microcontroller or microprocessor, which allows TWI to be implemented between the modules using the built-in hardware functions (if presence in the chip) or software (if there is none). Accordingly, the presence of microcontroller (4), (6), (8), (10) and microprocessor (5) is intended to provide control of modules (1), (3), (7), (9) and (2), respectively, via the TWI interface portions of the TWI interface (18), (16), (20), (22). Microcontrollers (4), (6), (8), (10) and the microprocessor (5) are connected through each other via sections of the TWI interface (18), (16), (20), (22) through each other; the microcontroller (6) is connected via the TWI interface section (16) to the microprocessor (5), the microprocessor (5) via the TWI interface section (18) to the microcontroller (4), the microcontroller (4) via the TWI interface section (20) to the microcontroller (8), the latter is connected via a portion of the TWI interface (22) to the microcontroller (10), and the order in the serial through communication of the microcontrollers and the microprocessor may differ from the above. The indicated TWI interface is intended for testing and control of system modules by a central processor - microprocessor (5). The TWI interface allows the central processor of the system to connect up to 128 different devices through one two-wire bi-directional bus, in which there is one line - the synchronization line (SCL) and the second line - the data line (SDA). Moreover, as external hardware components required for the implementation of the bus, pull-up resistors on each bus line are required. Each of the devices connected to the bus has an individual address; the procedure for determining the contents of the bus is supported by the TWI protocol. The presence of the TWI interface minimizes the number of conductors between the modules, which significantly affects positively the mass and dimensions of the modules, improving reliability, reducing unit costs during operation of the system, achieving unification, since additional elements are not required for servicing the interface except for standard transceiver microcircuits. Each module has two TWI pins on the power connector.

The power supply module (3) generates from the supply voltage of the system supplied to the module (3) via the power supply circuit (25), the basic power supply voltages for all modules supplied through the power supply circuits (19), (17) - the module power supply circuit ( 3) and (2), respectively, and along the power supply circuits (21), (23) - the power supply circuits of modules (7) and (9), respectively. The power supply module (3) is connected by power circuits (19) to the digital signal processing module (2), the latter is connected by power circuits (17) to the signal preprocessing module (1). On the other hand, the power supply module (3) is connected by power circuits (21) to the optical system control module (7), which in turn is connected by power circuits (23) to the scan control module. The procedure for communicating modules with power circuits may be different: from a power supply module (3) to a signal preprocessing module (1), from the latter to a digital signal processing module (3); from the power supply module (3) to the scanning control module (9), from which to the optical system control module (7). For each module, one internal base supply voltage is selected - the most optimal for further conversion, which is used to generate the voltages necessary for the module to function. In addition to generating power voltages for each module, the power supply module (3) also transmits TWI interface lines for connecting all modules on one two-wire bus.

The additional optical system control module (7) and the scan control module (9) are connected by buses (24). Tires (24) and tires (14) (see Figure 1) serve as data transmission, control and address buses.

The power connectors for each module are designed so that any module is equipped with two power connectors, standard for all modules. One of the connectors is used to connect the module to the power supply module (3), the connector connects the ground buses and the voltage bus lines generated by the power supply module (3), which are necessary to power the modules of a certain functional set. The second connector is used to trace power from the power supply module (3) to other modules of this functional set of modules, all the voltages that are supplied to the first connector are supplied to it. Both connectors have two TWI pins.

In each module, from a set of signal processing modules, as well as from a set of control modules for executive systems (if it is present in the electronic visualization system), voltage sources (not shown in Figs. 1-6) with a power of up to 0.6 W with total dispersion are formed power up to 0.1 W in the form of heat from the elements forming the voltage source. The feasibility of forming such individual in relation to each module power supply is due to the following. For the functioning of the module (one, several or all) it is required to provide its power, while this may necessitate different supply voltages, for example: 1.5 V; 2.5 V; 3.3 V; 5 V. In the case of supplying voltage via a cable connecting the power supply module and a specific module, the specified cable will contain a large number of conductors, which leads to cumbersomeness, inconvenience of laying the cable in the device, increase the size, because it requires a large volume of the housing in which system, such a loop is poorly bent and difficult to lay. As a result, this leads to a deterioration in reliability, as a result of a greater likelihood of wire breakage.

In the case of any of the modules connected with other modules only via the TWI interface (for testing and data transmission for module control), in the absence of an additional data bus, control and address (this case is not shown in the figures), supply voltage for the specified module is carried out directly from the power supply module in order to exclude closed circuits of the "earth", which prevents, therefore, the negative influence of the modules on each other through the ground bus.

So, when the loads receiving power supply from one power source are connected in series (the first load receives power supply from the power supply, the power supply bus of the second load is connected to the power supply to the first load, and so on), RF modulation (high frequencies) ) return currents of subsequent loads to previous ones. That is, since the common ground circuit, through which the load supply current flows, is characterized by some resistance, then with a consumption current, even the minimum, and with the minimum resistance of the ground buses, a certain voltage drop occurs at the indicated bus resistance. As a result of the presence of the indicated voltage drop in relation to each load, interference from other loads, influencing it to one degree or another, occurs. In order to minimize the negative impact of loads on each other, a star switching circuit is used. In this case, all loads are connected as close to the power supply source from one point. There will be no section (s) of the "earthen" bus with passing currents, providing voltage drops from other loads.

In our case, loads are understood as functional sets of modules — a set of processing modules and a set of control modules for executive systems.

In addition, the "star" scheme eliminates the formation of "earthen" contours. Otherwise, the return currents may have several flow paths (for example, the first load is connected to the power source, the second load is connected to the first load, the third load to the second load and the fourth to the third, which is connected to the source, as a result, the first load is affected as the second load , third, fourth, and the last is affected by the loads of the first, second, third, and so on); accordingly, interference from loads can increase significantly.

In the case of a module associated with other modules not only through the TWI interface (for testing and data transfer), but also with an additional data bus, control and address bus (as shown in Fig. 1), the power supply for it can be supplied through the module, most optimally located in the system relative to the power supply module. Here, “optimally positioned” means the module closest to the power supply module, taking into account the electromagnetic compatibility of the modules relative to each other. So, for example, the signal preprocessing module (1), which contains a highly sensitive analog circuit, is not recommended to be located near the power supply module (3), and, on the other hand, the digital signal processing module, as less sensitive to interference from the power supply module , can be selected as the power source (3) closest to the module (see Figure 1). Note that if pulse transformations are used in the power supply module (3) of the system (as in the case considered here), then significant electromagnetic interference occurs.

To connect additional modules, for example, modules (7) and (9), the digital signal processing module (2) is equipped with expansion slots. In this case, one or several single-row connectors are used, located along the perimeter of the module board (2) and close to the edge of the board. For the adapter connector, a PBS1.27 type connector is used with a pitch of 1.27 mm connector pins. The number of connector pins corresponds to the number of signal lines ensuring the operability of expansion cards (additional modules) connected to the digital signal processing module (2).

A set of signal processing modules (see Figure 1) is implemented as part of a signal preprocessing module (1) (see Figure 2) and a digital signal processing module (2) (see Figure 3).

In the particular case of the system, the signal preprocessing module (1) (see Figure 2) contains a microcontroller (6), an ADC (26), a voltage reference (27), an FPGA (28), SDRAM (29), an LVDS chip ( thirty). The module considered here is implemented in the following configuration. ATmegal28 is used as microcontroller (6), ADS850 as ADC (26), EP3C120F78017 as FPGA (28), MT48LC16M16A2BG-75 IT as SDRAM (29), up to several DS92LV18 as LVDS microcircuit (30) . The signal preprocessing module (1) may contain, instead of the SDRAM (29), an SRAM chip (static random access memory) -K.6R4016C1D. The reference voltage source (27) is based on the ADP3335ARM-5, REF193AR, AD8602AR microcircuit.

The microcontroller (6) is connected to the reference power supply (27) via buses (31) and connected to the FPGA (28) via bi-directional buses (35). The ADC (26) is connected to the matrix photodetector (11) through bidirectional buses (14), and also through bidirectional buses (32) connected to the FPGA (28). FPGA (28) is connected to the matrix photodetector multiplexer (11) by bidirectional control circuits of the photodetector multiplexer (the position in Fig. 2 is not shown), and is also connected via bidirectional buses (33) to SDRAM (29) and through bidirectional buses (34) to the microcircuit LVDS (30). The photodetector multiplexer control circuits (the position in FIG. 2 is not shown) are necessary for supplying digital signals to the photosensitive matrix (such digital signals can be a clock frequency, line and frame control pulses, in the opposite direction, to the FPGA (28), a resolution signal can be received reading data). The reference power supply (27) is connected by power circuits (13) to the matrix photodetector (11). Under the tires here should be considered control bus, data transfer and addresses.

The reference voltage source (27) generates the supply voltage and the bias of the photosensitive elements of the matrix photodetector (11) (see Figure 1) necessary for its operation. The magnitude of the bias voltage is controlled by the busbar (31) by the microcontroller (6) (see Figure 2). Also, the microcontroller (6) can control the on and off of the matrix photodetector (11) through commands on the buses (31), which is important when the thermal imaging device is turned on, since photodetectors of individual manufacturers do not allow power to be supplied to them if the crystal temperature of the photodetector has not reached the set temperature cooling. That is, first turn on the entire system of the device - all the electronic modules of the device, and only when the desired level of cooling of the crystal of the photodetector is the inclusion of the latter.

In addition to the microcontroller (6), module (1) contains the elements necessary for converting an analog signal to digital, contains a circuit that provides all the signals necessary for the functioning of the photodetector, a circuit for generating control signals of the photodetector switch, module (1) also provides the required supply voltage and photodetector bias. To exchange data with the digital signal processing module (2), there is a data preparation circuit that provides digital streams in a given format.

To ensure data exchange between the signal preprocessing module (1) and the digital signal processing module (2), LVDS transceiver microcircuits are used (LVDS microcircuit (30)). The indicated chip converts the 18-bit parallel binary code into the 18-bit serial code of the LVDS channel (15). One-way transmission, from transmitter to receiver, is carried out along two lines, which increases the reliability of the system. Each DS92LV18 chip as part of the LVDS chip (30) contains one receiver and one transmitter, which provides bidirectional data exchange on four lines. The DS92LV18 chip has a bandwidth of 2.376 Gbit / s, which corresponds to the transfer of 298 full-frame frames of 576 × 768 elements in one second.

For the LVDS transmitter, data is prepared in a strictly defined way, regardless of the frame format and the method of generating data at the output of the matrix photodetector (11). The digital standard has the following bit assignments: 0-13 bits - data, 17 - frame clock, 14-16 - service signals. The standard governs the following data transfer procedure. Data is transmitted in burst frames. The frame corresponds to the data array output from the photodetector to the signal preprocessing module (1). The frame size N × M corresponds to the format of the photodetector and contains information read from all photosensitive elements of the photodetector. N is the number of lines in a frame, M is the number of pixels in a line. The start of frame data transmission is indicated by a frame clock, bits 14 and 15 indicate the frame format. All data of the N × M frame is transmitted line by line, sequentially: line - 1, elements 1, 2, 3 ... M, line - 2, elements 1, 2, 3 ... M and so on, line - N, elements 1, 2, 3 , ... M. The standard assumes the same execution of data transmission in both directions.

The main purpose of the signal pre-processing module (1) is the processing and generation of digital-form signals prepared for further digital processing and image acquisition on a television monitor. The signal preprocessing module (1) must ensure the formation of supply voltages of the matrix photodetector (11) with the possibility of their regulation in order to achieve the optimal mode of operation of the photosensitive matrix multiplexer; ensure the implementation of the four-channel mode of operation of the multiplexer; provide amplification and signal matching for working with the ADC (26); ensure the matching of the digital signal levels of the matrix photodetector (11) and the LVDS microcircuit (30). The reference voltage source (27) provides the supply voltage of the photosensitive photodetector matrix via the supply circuits (13). The ADC (26) converts the analog signal received via the buses (14) from the photodetector array (11) into a 14-bit code, then the code is sent via the buses (32) to the FPGA (28). FPGA (28) generates control signals for the operation of the matrix photodetector (11) with the possibility of its operation in 1-channel, 2-channel and 4-channel modes. SDRAM (29) is designed to accumulate data arrays transmitted from FPGAs (28) via buses (33), for the purpose of conducting preliminary processing on them (for example, when using a microscanner, when a 384 × 288 frame is enlarged to 768 × 576). With FPGA (28), the 18-bit code of the digital standard used, in accordance with which the data for the LVDS transmitter is prepared, is transmitted via buses (34) to the LVDS chip (30), which is designed to form a bi-directional serial data stream of a given structure, which provides transmission / data reception in line and synchronous operation with the digital signal processing module (2).

In the particular case of system execution, the digital signal processing module (2) (see Figure 3) contains a microprocessor (5), FPGA (36), SDRAM (37) - (42), flash memory (43), EEPROM (44) , defective element replacement unit (45), television generator (46), brightness and contrast adjustment unit (47), symbol forming unit (48), digital filtering unit (49), DAC (50), ALU (51), memory controller (52). The module (3) considered here is implemented in the following configuration. The ADSP-BF533SBBC500 processor is used as the microprocessor (5), which is the central processor, the EP3C120F78017 chip is used as the FPGA (36), the MT48LC16M16A2BG-75 IT chip is used as the SDRAM (37) (42), and the flash memory ( 43) - chip M25P64VME6G, as EEPROM (44) - chip AT25256AN-10SI-2.7, as a node for replacing defective elements (45), a television generator (46), a unit for adjusting brightness and contrast (47), a unit for generating service characters ( 48), the digital filtering unit (49), as well as the memory controller (52) use FPGA elements (36), as the DAC (50) - AD9762ARU . Here are all the resources necessary for digital processing of the output signal of the photodetector. The necessary resources are selected taking into account the orientation towards promising photodetectors having an output signal format with a maximum number of pixels per frame. Such a digital signal processing module will maximally meet the achievement of the possibility of system unification. Due to the optimal selection of the element base and their location on the board, maximum unification is achieved with minimum dimensions of the module and minimum power consumption.

The microprocessor (5) is connected via buses (56) to the FPGA (36) through a memory controller (52), and is also connected to SDRAM (40), a synchronous dynamic random access memory device for storing intermediate ones, the microprocessor (5) - FPGA (36), data . SDRAM (40) has common address and data buses relative to the microcontroller (5) and FPGA (36), which makes it possible to access the intermediate memory SDRAM (40) of microprocessor (5) and FPGA (36) for writing and reading data. The microprocessor (5) is also connected to flash memory (43) and EEPROM (44) - an electrically reprogrammable read-only memory device, respectively, via bi-directional buses (59) and (60). SDRAM (37), synchronous dynamic random access memory for storing defective items via bidirectional buses (53), SDRAM (38), synchronous dynamic random access memory for storing the coefficients of correction of the heterogeneous sensitivity of the elements are connected to the FPGA (36) through the memory controller (52), by means of bidirectional buses (54), SDRAM (39), synchronous dynamic random-access memory for storing the correction coefficients of the dark background, through bidirectional buses (55), SDRAM (41), the first synchronous Response Dynamic random access memory image data storage device, through the bidirectional bus (57), SDRAM (42), the second synchronous dynamic random access memory device storing image data through bidirectional bus (58). Bidirectional buses (61) are connected to the memory controller (52) by a node for replacing defective elements (45), bidirectional tires (62) - a television generator (46), bidirectional buses (63) - a unit for adjusting brightness and contrast (47), bidirectional buses ( 64) - node forming characters (48), bidirectional tires (65) - node digital filtering (49), bidirectional buses (66) - ALU (51). In addition, the node for replacing defective elements (45) is connected via a bus (67) to a memory controller (52), and via a bus (68) it is connected to a television generator (46). The television generator (46) is connected via buses (69) to a brightness and contrast adjustment unit (47), while the latter is connected by buses (70) to a symbol formation unit (48). Finally, the symbol forming unit (48) is connected via buses (71) to the digital filtering unit (49), which is connected by buses (72) to the DAC (50). The DAC (50) is connected by buses (the position in FIG. 3 and FIG. 1 is not indicated) with a television monitor (12). The LVDS channel (15) connects the ALU (51) as part of the FPGA (36) of the digital signal processing module (2) with the signal preprocessing module (1). Under the tires here should be considered control bus, data transfer and addresses.

In the digital signal processing module (2), in addition to the intermediate memory - SDRAM (40), there is a television memory consisting of SDRAM (41) and SDRAM (42), as well as synchronous dynamic random access memory devices - SDRAM (37), (38) and (39 ) in an amount equal to the number of variables used in the processing algorithms.

On the basis of FPGA (36), an initial digital processing unit that implements its own image processing functions and a final digital processing unit that replaces defective elements is implemented. On the basis of microprocessor (5), an intermediate digital processing unit has been implemented that accumulates full-format image arrays and performs processing functions on them.

The intermediate digital processing unit is connected with the initial digital processing unit through an intermediate SDRAM (40), designed to store intermediate data.

The signal preprocessing module (1) is connected to the source of the digital processing. The initial digital processing unit is equipped with random-access memory devices connected to a programmable logic integrated circuit with individual address and data buses in the indicated quantity. The microcontroller (5) is configured to access any random access memory device connected to the FPGA (36). The initial digital processing unit is connected to the final digital processing unit via a television memory connected to the FPGA (36). The final digital processing unit is connected to the DAC (50).

An initial digital processing unit that performs its own image processing functions implemented on the basis of FPGA (36), in particular, is made as a part of ALU (51) FPGA (36). The initial digital processing unit is equipped with a synchronous dynamic random access memory (SDRAM) for storing defective elements (37), an SDRAM (38) and synchronous dynamic random access memory (SDRAM) for synchronizing the dynamic sensitivity of the elements, and SDRAM (39) ) ALU (51) is connected to the indicated SDRAM (37), SDRAM (38) and SDRAM (39) through the memory controller (52).

A television memory connected to the FPGA (36) is made up of the first and second synchronous dynamic random access memory devices for storing image data SDRAM (41) and SDRAM (42), respectively, which are connected to the FPGA (36) via a memory controller (52). SDRAM (41) and SDRAM (42) are made with individual address and data buses, with the possibility of switching them with a frame rate of a television monitor. The specified implementation ensures the use of one of them for recording processed by the node source digital data processing, and the other for reading data and final digital processing.

The intermediate digital processing unit, implemented on the basis of microprocessor (5), which accumulates full-format image arrays and performs processing functions on them, is made as a part of the microprocessor directly (5), flash memory (43) and EEPROM (44). The microprocessor (5) is connected to a USB controller to access a personal computer (not shown in FIG. 3). Flash memory (43) associated with the microprocessor (5) is used to store arrays of correction coefficients of inhomogeneous sensitivity and a dark background for the purpose of periodically, if necessary, rewriting them by the microprocessor (5) in the intermediate SDRAM (40). The electrically reprogrammable read-only memory EEPROM (44) associated with the microprocessor (5) is used to record the operating time by the microprocessor (5).

To achieve the possibility of accessing FPGAs (36) to the intermediate SDRAM (40) with common address and data buses and the possibility of accessing microprocessor (5) and FPGA (36) for writing and reading data, the microprocessor outputs (5) are implemented with the ability to switch them in the third state.

The microprocessor (5) is configured to access any synchronous dynamic random access memory connected to the FPGA (36): SDRAM (37), SDRAM (38) and SDRAM (39), as well as SDRAM (40), by using a memory controller (52 ) Connecting the address and data bus of the microprocessor (5) to the FPGA (36) through the memory controller (52) provides the ability to access any random access memory device connected to the FPGA (36).

The final digital processing unit implemented on the basis of FPGA (36), which replaces defective elements, is made up of sequentially connected defective element replacement unit (45), a television generator (46), a brightness and contrast adjustment unit (47), and a service character generation unit ( 48), a digital filtering unit (49). Elements (47) - (49) are FPGA components (36). The node for replacing defective elements (45) is associated with a television memory that provides the ability to read processed by the nodes of the original digital and intermediate digital data processing. The digital filtering unit (49) is connected to the DAC (50).

The signal preprocessing module (1) is connected to the initial digital processing unit, implemented on the basis of FPGA (36), by means of ALU (51), which implements processing algorithms with respect to the signals arriving at it from module (1).

In the device, the nodes of the initial, intermediate and final digital processing by the memory controller (52) are synchronized with the processed data stream.

The main purpose of the digital signal processing module (2) is the processing of the digital waveform, aimed at obtaining an image of the required quality on a television monitor.

The initial digital processing unit, to which the signal from the signal preprocessing module (1), implemented on the basis of FPGA (36), is digitally fed, is designed to perform algorithms for correcting the dark background or correcting the inhomogeneous sensitivity of elements. ALU (51) - one of the elements that make up the FPGA (36), implements algorithms for correcting the dark background or correcting the heterogeneous sensitivity of the elements. Synchronously with the value of each address bus of random-access memory devices connected to the FPGA (36), - SDRAM (37), (38) and (39), the corresponding data array is read. Each memory address corresponds to a pixel value in the data array from a matrix photodetector (11). Arrays of defective elements, correction coefficients of inhomogeneous sensitivity and correction of dark background are stored in the SDRAM microcircuits (37), (38) and (39), respectively. Data is read from the indicated random access memory devices in synchronization with the sampling rate of the matrix photodetector (11), which allows one to obtain the values of three variables for arithmetic operations for ALU (51). The television memory is intended for recording the result of arithmetic operations in one of the operative storage devices of the television output, SDRAM (41) or SDRAM (42). The address and data buses of the SDRAM (41) and SDRAM (42) random access memory devices are switched at the frame rate of the television monitor (12), which allows one of them to be used alternately for recording processed ALU (51) data, and the other for reading data and the final their processing.

Together with the source of the initial digital processing, it fulfills its purpose - the accumulation and processing of intermediate data arrays, the node of the intermediate digital processing. After processing in ALU (51), the result, in addition to the television memory (SDRAM (41) and SDRAM (42)), is written to the intermediate SDRAM (40), where this array can be accumulated the required number of times and further processed by the central processor - microprocessor (5) . After processing, the central processor - microprocessor (5) sends the data array to the synchronous dynamic random access memory devices SDRAM (37), (38) and (39). If we put 50 frames for the full cycle of intermediate data processing, then we write the SDRAM (40) into the intermediate memory, in the first frame the value of the dark background, in the second frame the value of the corrected image, and in the 48 frame we write from the intermediate SDRAM (40) into the random access memory SDRAM device (37) updated table of defective elements, in frame 49 writing from the intermediate memory SDRAM (40) to random access memory SDRAM (38) updated array of correction factors for the heterogeneous sensitivity of the elements, 50 frames per using the average dark background of the array of elements of the matrix photodetector (11) averaged over the specified number of times from the SDRAM intermediate memory SDRAM (40) to the SDRAM random access memory (39), the remaining time, including from 3 frames to 47 frames, the central processor is a microprocessor (5) performs the accumulation of a dark background a specified number of times, forms an adjusted table of defective elements and updates the correction coefficients of the inhomogeneous sensitivity depending on the temperature of the observed object. In addition, arrays of correction factors for the heterogeneous sensitivity of the photodetector elements stored in flash memory (43) are periodically, depending on external conditions, rewritten by the central processor - microprocessor (5) into the SDRAM intermediate memory (40). The microprocessor (5) also records the operating time of the system and writes this information to the electrically reprogrammable read-only memory EEPROM (44). The primary data are loaded into the indicated memory chips and the processing is controlled by using, for example, the USB 2.0 interface. The microprocessor (5) is accessed by each random access memory device thanks to the memory controller (52), which is the FPGA element (36), and allows the microprocessor (5) to be used to read and write data arrays via the USB controller – personal computer channel (in FIG. 1 and FIG. 3 not shown).

The final digital processing unit completes the digital signal processing for outputting the image to a television monitor (12).

The data processed jointly by the nodes of the initial and intermediate digital processing are read from the random access memory SDRAM (41) or SDRAM (42) of the television memory and are sent to the node for replacing defective elements (45). The defective element is set to the average value from the full-fledged elements adjacent to the right and left. The signal is fed to a television generator (46), designed to bind to television synchronization signals. Next, the signal enters the brightness and contrast adjustment unit (47), the purpose of which is to analyze the image array to form the values of the automatic brightness and contrast adjustments necessary during operation. After that, the signal arrives at the symbol forming unit (48), where service information symbols are inserted into the image array. At the end of the final digital processing, the signal enters the digital filtering unit (19), designed to directly replace the defective elements with the average value from the surrounding full elements and median image filtering.

After passing through all the stages of processing, the digital signal is fed to the DAC (50) and converted into analog form.

The next necessary component of the considered system for visualizing infrared images of matrix thermal imagers is the power supply module (3) (see Figure 4). The main purpose of the power supply module (3) is to provide power voltages for all other system modules. In the specific case of the system, the power supply module (3) (see Figure 4) contains a microcontroller (4), a power supply converter (73). The module (4) considered here is implemented in the following configuration. The ATmega 128 is used as the microcontroller (4), and the power supply converter (73) is based on LM5576 microcircuits. The microcontroller (4) is connected via bi-directional buses (74) to the converter of the power source (73). By using the microcontroller (4) using the TWI interface, control the chips of the converter of the power source (73). In addition, the microcontroller (4), using the ADCs contained in it, monitors the output voltages of the module (3) supplied to other modules through the power supply circuits (21) and (19). Under the tires here should be considered control bus, data transfer and addresses.

Further, in addition to the basic framework containing modules (1) to (3), the system may contain additional modules, in particular, an optical system control module (7) and a scanning control module (9) (see Fig. 6) included in the set control modules executive systems (see Figure 1).

The optical system control module (7) is designed for automatic correction of the lens focus change, as well as lens focus search by command from the microprocessor (5) of the digital signal processing module (2). Module (7) is made up of a microcontroller (8), FPGA (75), an electric drive control circuit (76), flash memory (77), EEPROM (78) (see Figure 5). ATmegal28 is used as a microcontroller (8), ЕРМ240Т100С4 chip is used as FPGA (75), КР1128КТ3А driver chips are used as an electric drive control circuit (76)), M25P64VME6G chip is used as flash memory (77), EEPROM (78) - chip AT25256AN-10SI-2.7. The microcontroller (8) is connected by bidirectional buses (79) to the FPGA (75), as well as bidirectional buses (81) is connected to flash memory (77) and bidirectional buses (82) to EEPROM (78). Tires (80) connect the FPGA (75) to the drive control circuit (76). The drive control signal from the drive control circuit (76) is sent to the scan control module (9) via bi-directional buses (24). Under the tires here should be considered control bus, data transfer and addresses.

Using the microcontroller (8) via the TWI interface, the drivers of the electric drive control circuit (76) are controlled via FPGA (75) microcircuits and, ultimately, the electric drive of the lens unit of the system is controlled. Flash memory (77) is designed to store the coordinates of the movement of the elements of the optical system. EEPROM (78) is used to store data on the operating time of the module (7) and the current coordinates of the movement of the elements of the optical system in case of power failure in the module (7).

Scanning control module (9) performs two-dimensional (vertical and horizontal) electronic (using piezoelectric elements that move the projection system vertically and horizontally) scanning. Scanning is carried out at a distance of ½ pixel from a specific pixel (the so-called micro-scanning). Microscanning is used to increase the resolution of the thermal imager and, accordingly, its sensitivity. The module (9) is made up of a microcontroller (10), an FPGA (83), a control circuit for the bias field of view (84), flash memory (85), EEPROM (86) (see Figure 6). The ATmega 128 is used as the microcontroller (10), the EPM7064STC44-10 chip is used as the FPGA (75), the PA12A driver chips are used as the control circuit for the bias field drive (84), and the M25P64VME6G chip is used as flash memory (85), as the EEPROM (86) - the AT25256AN-10SI-2.7 chip. The microcontroller (10) is connected by bidirectional buses (87) to the FPGA (83), and bidirectional buses (89) is connected to the flash memory (85) and bidirectional buses (90) to the EEPROM (86). Tires (88) connect the FPGA (83) to the control circuit of the bias field of view (84). The drive control signal from the field of view bias drive control circuit (84) via bidirectional buses (24) is fed to the optical system control module (7). Under the tires here should be considered control bus, data transfer and addresses.

Using the microcontroller (10), the TWI interface controls the FPGA (83) microcircuit with the drivers of the field of view bias drive control circuit (84). Flash memory (85) is designed to store initial states and module variables. EEPROM (86) is used to store data on the operating time of the module (7) and the current operating states of the module (9) during power failures.

An electronic infrared image visualization system for matrix thermal imagers (see FIG. 1) operates as follows.

The signal from the matrix photodetector (11) is fed to the signal preprocessing module (1), brought to a single standard, prepared for transmission via the LVDS channel (15), transmitted through the specified channel to the digital signal processing module (2), in which the full digital processing. The processed data is displayed on the screen of a television monitor (12). The system is controlled through control interfaces from a personal computer (see Figure 1). The power supply module (3) generates from an external voltage source connected by the power supply circuits (25) with the specified module, the supply voltage for the functional sets of modules supplied through the power supply circuits (19) and power supply circuits (21). Through a common TWI interface bus consisting of sections (16), (18), (20), (22), to which a microcontroller (6), a microprocessor (5), a microcontroller (4), a microcontroller (8), a microcontroller ( 10), the system modules are controlled, module testing and low-speed data transfer are carried out. Each module power connector has two TWI-SDA and SDL interface pins, in this regard, any module connected to the power supply circuits (17), (19), (21) (23) through this connector when connected to a single system, is connected and to the shared TWI bus.

Claims (14)

1. An electronic infrared image visualization system for matrix thermal imagers, comprising a signal pre-processing module and a digital signal processing module, characterized in that it is additionally equipped with a power supply module, said modules being made on separate boards and grouped into sets according to their functional purpose, a set of signal processing modules as part of a signal preprocessing module and a digital signal processing module, a set of electric power modules As part of the power supply module, each module is equipped with a microcontroller or microprocessor, through which all modules are end-to-end through the TWI interface, in accordance with the functionality of the modules to them from the power supply module, the voltage is traced with the end-to-end coverage of the modules in the set, with the formation of interdependent power circuits, in the set of signal processing modules between the signal preprocessing module and the digital signal processing module signal chains - control, data transmission and addresses in the form of a standard stream. 2. The electronic system according to claim 1, characterized in that in addition to the sets of signal processing and electric power supply modules, it additionally contains a set of control modules for thermal imaging actuator systems, a microcontroller is made in each module, through the latter, the modules are end-to-end via TWI interface, in accordance with the functional the availability of the modules for them from the power supply module, tracing of the supply voltages with through coverage of the modules in the set, with the formation of interdependent circuits Tania. 3. The electronic system according to claim 1, characterized in that in addition to the sets of signal processing and electric power supply modules, it further comprises a set of control modules for thermal imaging actuator systems made as a part of the optical system control module and the scanning control module, a microcontroller is made in each module, by means of which through communication of the modules via the TWI interface was carried out, in accordance with the functionality of the modules to them from the power supply module, tracing was performed power supply circuits with end-to-end coverage of the modules in the set, with the formation of interdependent power circuits, in the set of control modules for executive systems between the optical system control module and the scan control module, signal circuits are implemented - control buses, data transmission and addresses. 4. The electronic system according to claim 1, characterized in that in the set of signal processing modules as part of the signal preprocessing module and digital signal processing module and the set of electric power modules as part of the power supply module, the microcontroller is made in the signal preprocessing module and the power source module The microprocessor is made in a digital signal processing module; in the set of signal processing modules between the signal preprocessing module and the digital signal processing module, the signal chains are implemented - control, data and address transmission, namely, the LVDS channel, the signal preprocessing module is equipped with bi-directional control, data and address buses that connect it to the matrix photodetector, the digital signal processing module is equipped with buses for displaying images on a television monitor, the digital signal processing module is also equipped with a control interface electronic system; in accordance with the functional purpose of the modules in the set of signal processing modules for them from the power supply module, the voltage was traced with the through coverage of the modules in the set, with the formation of interdependent power circuits, namely, sequentially from the power supply module to the digital signal processing module, from the module digital signal processing to the signal preprocessing module, from the signal preprocessing module to the matrix photodetector. 5. The electronic system according to any one of claims 1 to 4, characterized in that the power supply module has power connectors based on the grouping of the system modules into sets in accordance with their functional purpose and in an amount equal to the number of sets of modules. 6. An electronic system according to any one of claims 1 to 4, characterized in that the power supply module is provided with one or more power connectors in an amount equal to the number of sets of modules into which the latter are grouped in accordance with their functional purpose, excluding from the specified number of sets modules a set of electric power modules, which includes a power supply module, each module, in addition to the power supply module, is equipped with two power connectors, connectors are standard for all modules, one of the connectors indiscrete module directly connected to the module power source, the second connector is configured to route power from the power supply module to other modules of the feature set is also available in all power supply system provided with two connectors contacts TWI interface. 7. An electronic system according to any one of claims 1 to 4, characterized in that in each module from the sets into which the modules are grouped according to their functional purpose, not taking into account the set of electric power modules, which comprise the power supply module voltage sources with power up to 0.6 W are formed with total power dissipation up to 0.1 W in the form of heat from the elements forming the voltage source. 8. An electronic system according to any one of claims 1 to 4, characterized in that the supply voltage from the power supply module for each module associated with other modules of the system, not only via the TWI interface, but also signal circuits - control, data and address , implemented through a module that is most optimally located in the system relative to the power source, closest to the power supply module, taking into account the electromagnetic compatibility of the modules relative to each other. 9. The electronic system according to claim 1, characterized in that the digital signal processing module for connecting additional modules is provided with expansion connectors as part of one or more single-row connectors located along the perimeter of the module board and close to the edge of the board, with the number of connector pins corresponding to the number signal lines ensuring the operability of plug-in expansion cards - additional modules. 10. An electronic system according to any one of claims 1 to 4, characterized in that the signal preprocessing module is made up of a microcontroller, an analog-to-digital converter, a voltage reference, a programmable logic integrated circuit, synchronous dynamic random access memory, LVDS microcircuit, The microcontroller is connected to the reference power supply via buses and connected to the programmable logic integrated circuit via bi-directional buses, analog-to-digital conversion The bi-directional matrix connected to the photodetector by bi-directional buses is connected to the programmable logic integrated circuit via the bi-directional buses, the latter is connected by bi-directional control circuits to the matrix photo-successor multiplexer, and is also connected by bi-directional buses with synchronous dynamic random access memory and connected by bi-directional buses with an LVDS chip preparing data exchange on signal chains - control, data and address transmission, namely, on the LVDS channel, op source voltage is connected by power circuits to the matrix photodetector. 11. The electronic system according to any one of claims 1 to 4, characterized in that the digital signal processing module is made up of a microprocessor, a programmable logic integrated circuit, a synchronous dynamic random access memory device for storing defective elements, a synchronous dynamic random access memory device for storing inhomogeneous sensitivity correction coefficients elements of synchronous dynamic random access memory storage device for the correction coefficients of the dark background, si intermediate dynamic random access memory storage device, television memory from the first synchronous dynamic random access memory device for image data storage and the second synchronous dynamic random access memory device for image data storage, flash memory, electrically reprogrammable read-only memory device, digital-to-analog converter, while on the basis of programmable logical integrated circuit implemented the source node about processing operations, which performs its own image processing functions, and a final digital processing unit that replaces defective elements, an intermediate digital processing unit is implemented on the basis of the microprocessor, which accumulates full-format image arrays and performs processing functions on them, the initial digital processing unit is implemented as part of an arithmetic-logic device , which is a component of a programmable logic integrated circuit configured to be received on it about the signal chain - control, data and address transmission, namely, the LVDS channel, digital data for processing and connected by bidirectional buses to a memory controller, also a component of a programmable logic integrated circuit, synchronous dynamic random access memory storage device for defective elements connected by individual bidirectional buses with the specified memory controller, synchronous dynamic random access memory storage device correction coefficients of a heterogeneous the sensitivity of the elements associated with the individual bidirectional tires with the specified memory controller, a synchronous dynamic random access memory storage device for correcting the dark background, associated with the individual bi-directional buses with the specified memory controller, a television memory in the first synchronous dynamic random access memory device for storing image data and the second synchronous dynamic random access memory data storage device x the image is connected to the specified memory controller through individual bi-directional buses of the first and second synchronous dynamic random access memory image data storage devices, configured to switch them with a frame rate of a television monitor, the intermediate digital processing unit is made up directly of a microprocessor associated with the specified memory controller and synchronous dynamic random access memory device for storing intermediate data by means of common address and data buses, in order to achieve the possibility of accessing the programmable logic integrated circuit to the synchronous dynamic random access memory device for storing intermediate data and the possibility of accessing it by the microprocessor and the programmable logic integrated circuit for writing and reading data, the microprocessor outputs are implemented with the ability to switch them to the third state, also in the node of the intermediate digital processing flash memory connected bidirectional and tires with a microprocessor, and an electrically reprogrammable read-only memory connected to bidirectional buses with a microprocessor, the final digital processing unit is made up of serial devices connected to the specified memory controller via the buses of the defective element replacement unit, a television generator, a brightness and contrast adjustment unit, and an office forming unit characters, digital filtering node, which are components of a programmable logic integrated circuit, each one of the listed components is connected to the indicated memory controller by bi-directional buses; finally, a digital-to-analog converter is connected to the digital filtering unit by buses, which supplies image signals for output to a television monitor. 12. The electronic system according to any one of claims 1 to 4, characterized in that the power supply module is made up of a microcontroller connected by bidirectional buses to a power supply converter, which converts the input voltage supplied through the power circuits to the output voltages supplied through the power circuits from the module power supply to other modules. 13. The electronic system according to claim 3, characterized in that the optical system control module is made up of a microcontroller, a programmable logic integrated circuit, an electric drive control circuit, flash memory, an electrically reprogrammable read-only memory device, and the microcontroller is connected by bi-directional buses with a programmable logic integrated circuit , which, in turn, is connected to the drive control circuit, the microcontroller is connected by bidirectional buses to flash memory and is connected to gimi bidirectional buses with electrically reprogrammable read-only memory, the drive control circuit is provided with bidirectional signals flow to the tires scanning control module. 14. The electronic system according to claim 3, characterized in that the scanning control module is made up of a microcontroller, a programmable logic integrated circuit, a control circuit for the bias field of view, flash memory, electrically reprogrammable read-only memory, the microcontroller is connected by bi-directional buses with programmable logic an integrated circuit, which, in turn, is connected to the control circuit of the drive to shift the field of view, the microcontroller is connected by bidirectional buses to the w-memory and is connected by other bi-directional buses to an electrically reprogrammable read-only memory, the control circuit of the bias field of view drive is equipped with bi-directional buses for supplying signals to the optical system control module.