WO2022052845A1

WO2022052845A1 - Linear array detector-based high-speed big data transmission system and method, terminal, and medium

Info

Publication number: WO2022052845A1
Application number: PCT/CN2021/115929
Authority: WO
Inventors: 王�锋; 方志强; 陶晨斌
Original assignee: 上海奕瑞光电子科技股份有限公司
Priority date: 2020-09-14
Filing date: 2021-09-01
Publication date: 2022-03-17
Also published as: CN112415619B; CN112415619A

Abstract

A linear array detector-based high-speed big data transmission system, comprising: a control module (11), configured to control all modules to work; a conveying module (12), configured to convey an object to be detected; a ray source module (13), configured to emit rays to the conveying module (12) according to a ray control instruction; a detection module (14), configured to receive rays penetrating through the object moving on the conveying module (12) and convert the rays into data information formed by connecting digital signals end to end; and a processing and display module (15), configured to process and display the data information. The system solves the problems that in the prior art, the load capacity of a single data acquisition board is insufficient, and a bus analog signal data transmission mode is further adopted between some detection boards and the data acquisition board, which is adverse to long-term stability of a system, and increases the costs of the whole machine. Also provided are a linear array detector-based high-speed big data transmission method, a linear array detector-based high-speed big data transmission terminal, and a computer storage medium.

Description

High-speed big data transmission system, method, terminal and medium based on linear array detector

technical field

The present application relates to the technical field of linear array detectors, and in particular, to a high-speed big data transmission system, method, terminal and medium based on a linear array detector.

Background technique

At present, for X-ray linear array detectors, the detection boards used in security inspection machines are pseudo dual-energy linear array detection with vertically distributed probes (PD sensors). Since the channel-type security inspection machines, such as security inspection gantry or L-shaped security inspection channels, have different channel sizes and specifications, the number of cascaded detection boards required is also different. At the same time, different detection targets, such as luggage, containers, trolleys or other pipeline-type detection items, require different conveyor belt speeds and pixel size requirements.

X-ray line array detectors in current applications have clear disadvantages:

(1) Higher conveyor speed cannot be achieved, and matching detection can be achieved generally under the condition of 0.4m/s. The frame rate of the detection board with a load of about 10 is generally within 1K/s, which cannot support the detection requirements of higher transmission speed. ;

(2) The wiring mode of data and signals is generally the bus mode. In this way, when the load of the data acquisition board increases, the impedance of the bus will increase after the line length becomes longer, and it is impossible to increase the clock frequency of the control signal. It can improve the stability of transmission and communication, and limit the detection of the minimum integration time; at the same time, when the bus mode is used in the security inspection field of large-scale channels, due to the insufficient load capacity of a single data acquisition board, more data acquisition boards are required. External synchronization can only be matched, which further increases the cost and reduces the stability of the system;

(3) Some detection boards and data acquisition boards also use single-ended signals to control data transmission, which is more susceptible to electromagnetic environment interference, resulting in abnormal data or abnormal power supply, resulting in detector crash, which actually affects the resistance of the whole system. The interference design puts forward requirements, which also increases the cost of the whole machine, and is not conducive to the long-term stability of the system;

(4) The bus mode cannot expand the application field, such as belt detection in mines and parcel detection in logistics, which cannot be adapted, because such detection needs to be carried out under a high transmission belt, and the minimum integration time under heavy load is required. higher;

(5) The cascading sorting method between the detection boards, some need to be set independently on the detection board, such as the use of non-repetitive DIP settings, and some need to set an additional matching resistor on the last detection board of the cascade to ensure the level This increases the process and man-hours during assembly of the whole machine, and is not conducive to repair or replacement.

Application content

In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a high-speed big data transmission system, method, terminal and medium based on a linear array detector, which is used to solve the problem that the prior art cannot support higher transmission speed. For detection requirements, the load capacity of a single data mining board is insufficient, and more data mining boards are required for external synchronization to match, which further increases the cost and reduces the stability of the system. Bus simulation is also used between some detection boards and data mining boards. The mode of signal transmission data is more susceptible to the interference of electromagnetic environment, resulting in abnormal data or detector crash, and increasing the cost of the whole machine; it is also not conducive to the long-term stability of the system and the detection board needs to be dialed in order or the last detection board needs Termination matching resistors can work in cascade and other issues.

In order to achieve the above purpose and other related purposes, the present application provides a high-speed big data transmission system based on a linear array detector, comprising: a control module for controlling the work of each module; a transmission module for connecting the control module for transmitting the object to be detected; a ray source module, connected to the control module, for sending out rays to the transmission module according to a ray control instruction; a detection module for receiving the to-be-detected object that penetrates and moves on the transmission module The ray of the object is converted into data information formed by connecting end-to-end digital signals; the processing and display module is connected to the detection module for processing and displaying the data information.

In an embodiment of the present application, the detection module includes: an induction sub-module for converting the rays collected in each cycle into corresponding analog electrical signals; ASCI sub-module for converting the analog electrical signals of the current cycle. The signal is digitally converted and the digital signal of the previous cycle is output; the FPGA sub-module includes: including a plurality of storage units for receiving the digital signal of the previous cycle and transmitting it forward step by step until it is transmitted to the last level In order to achieve end-to-end connection of each digital signal.

In an embodiment of the present application, the ASCI sub-module includes: a reset unit for starting a new integration sequence for the next cycle; a CDS integration amplifying unit for integrating and amplifying the analog signal of the current cycle; a multi-channel The data output unit is configured to perform signal conversion according to the integration and amplification result of the previous cycle while the integration and amplification are performed, and output the digital signal of the previous cycle.

In an embodiment of the present application, the ASCI sub-module further includes: a serial shift unit for shifting the digital signal of the previous cycle to a storage unit in the FPGA module.

In an embodiment of the present application, the FPGA sub-module includes: one or more interface units, including: an output for receiving control signals and data and/or the detection module further includes: an LVDS signal line module, including : One or more LVDS pins are connected to the FPGA sub-module for parallel transmission of the multi-segment data split in the FPGA sub-module.

In order to achieve the above purpose and other related purposes, the present application provides a high-speed big data transmission method based on a linear array detector, which is applied to a high-speed big data transmission system based on a linear array detector. The system includes: a control module for Control each module to work; a transmission module, used to transmit the object to be detected; a ray source module, used to send rays to the transmission module according to a ray control instruction; the method includes: receiving penetration and moving on the transmission module The ray of the object to be detected; convert the ray into data information formed by connecting each digital signal end to end.

In an embodiment of the present application, the method of converting the rays into data information formed by connecting digital signals end to end includes: converting the rays collected in each cycle into corresponding analog electrical signals; converting the current The periodic analog electrical signal performs digital conversion of the signal and outputs the digital signal of the previous cycle; receives the digital signal of the previous cycle and transmits it forward step by step until it is transmitted to the last stage to achieve the end-to-end connection of each digital signal .

In order to achieve the above purpose and other related purposes, the present application provides a high-speed large data transmission terminal based on a linear array detector, comprising: a memory for storing a computer program; a processor for running the computer program to execute the Data transmission method for line array detectors.

In order to achieve the above object and other related objects, the present application provides a computer-readable storage medium storing a computer program, and when the computer program is run, the high-speed big data transmission method based on the linear array detector is implemented.

As described above, the high-speed big data transmission system, method, terminal and medium based on the linear array detector of the present application have the following beneficial effects:

1. Achieve smaller integration time under heavy load, improve frame rate, match higher transmission belt speed, and expand application fields;

2. Digital transmission, stronger anti-interference, lower requirements for hardware, ordinary flat wire can achieve efficient transmission, and at the same time, support higher clock frequency control of control signals;

3. Keep up with the current 5G trend, better service AI automatic identification applications, reduce labor costs and human misjudgment;

4. The stronger single-board load capacity expands the width of the detection channel, and achieves the goal of being large and complete, and the goal of compatible applications; one product can basically cover the whole, reducing development and maintenance costs;

5. A more stable data transmission mechanism ensures the stability of the FPGA program, reduces the probability of abnormal image acquisition, and reduces the risk of frame loss;

6. There is no cascading sequence requirement between the detection boards, which can be combined at will, reducing the difficulty of installation and debugging of the whole machine.

In general, using the method proposed by the present invention can effectively improve the frame rate, realize the conveyor belt speed requirement of at least 2m/s, and improve the competitiveness of products; and can reduce the cost of the whole machine, reduce the complexity of system integration, and improve the The stability of the whole system.

Description of drawings

FIG. 1 is a schematic structural diagram of a high-speed big data transmission system based on a linear array detector according to an embodiment of the present application.

FIG. 2 is a schematic structural diagram of a detection module in an embodiment of the present application.

FIG. 3 is a schematic diagram of signal conditioning in an ASCI sub-module in an embodiment of the present application.

FIG. 4 is a schematic diagram of a data transmission mode in an embodiment of the present application.

FIG. 5 is a schematic diagram showing the transmission of control command signals and digital data channels of each detection module in an embodiment of the present application.

FIG. 6 is a schematic diagram of high-speed LVDS data transmission in an embodiment of the present application.

FIG. 7 is a schematic flowchart of a data transmission method based on a line array detector according to an embodiment of the present application.

FIG. 8 is a schematic structural diagram of a data transmission terminal based on a line array detector according to an embodiment of the present application.

detailed description

The embodiments of the present application are described below through specific specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. The present application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments may be combined with each other under the condition of no conflict.

It should be noted that, in the following description, reference is made to the accompanying drawings, which describe several embodiments of the present application. It is to be understood that other embodiments may be utilized and mechanical, structural, electrical, as well as operational changes may be made without departing from the spirit and scope of the present application. The following detailed description should not be considered limiting, and the scope of embodiments of the present application is limited only by the claims of the issued patent. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the application. Spatially related terms, such as "upper," "lower," "left," "right," "below," "below," "lower," "above," "upper," etc., may be used herein for convenience Describe the relationship of one element or feature shown in the figures to another element or feature.

Throughout the specification, when a part is said to be "connected" to another part, this includes not only the case of "direct connection" but also the case of "indirect connection" with other elements interposed therebetween. In addition, when it says that a certain part "includes" a certain constituent element, unless there is particularly no description to the contrary, it does not exclude other constituent elements, but means that other constituent elements may also be included.

Also, as used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context dictates otherwise. It should be further understood that the terms "comprising", "comprising" indicate the presence of a stated feature, operation, element, component, item, kind, and/or group, but do not exclude one or more other features, operations, elements, components, The existence, appearance or addition of items, categories, and/or groups. The terms "or" and "and/or" as used herein are to be construed to be inclusive or to mean any one or any combination. Thus, "A, B or C" or "A, B and/or C" means "any of the following: A; B; C; A and B; A and C; B and C; A, B and C" . Exceptions to this definition arise only when combinations of elements, functions, or operations are inherently mutually exclusive in some way.

At present, the detection boards used in security inspection machines are pseudo-dual-energy linear array detection with vertically distributed probes (PD sensors). Since the channel-type security inspection machine, such as the security inspection gantry or L-shaped security inspection channel, has different channel sizes and specifications, the number of cascaded detection boards required is also different. At the same time, different inspection targets, such as luggage, containers, trolleys or other pipeline inspection items, require different conveyor belt speeds and pixel size requirements.

There is a general trend in the market today: first, linear array detectors are required to minimize the limitation of the minimum integration time and match high-speed conveyor belts to improve detection efficiency; second, a data acquisition board needs to increase The number of large-load detection boards is compatible with the requirements of different detection channel widths, reducing hardware configuration and reducing the cost of the whole machine; third, in the application field of line array detectors, it is increasingly required to adapt to AI automatic identification applications at high frame rates, improving Identify efficiency and reduce labor costs. Therefore, the low-speed type, the linear array detector with a small load of a single data mining board can no longer be satisfied.

Therefore, the present application provides a high-speed big data transmission system based on a linear array detector, which solves the detection requirement that the prior art cannot support higher transmission speed, the load capacity of a single data mining board is insufficient, and more data mining boards are required. Only external synchronization can be performed to match, which further increases the cost and reduces the stability of the system. Some detection boards and data acquisition boards also use single-ended bus for data transmission, which is more susceptible to electromagnetic environment interference, resulting in abnormal data and even detectors. It crashes and increases the cost of the whole machine; it is also not conducive to the long-term stability of the system, and the detection board needs to be dialed in order or the last detection board needs to be terminated with matching resistors to work in cascade. This application can effectively improve the frame rate, To achieve the conveyor belt speed requirement of at least 2m/s, improve the competitiveness of the product; and can reduce the cost of the whole machine, reduce the complexity of system integration, and improve the stability of the whole machine system.

The system includes:

The control module is used to control the work of each module;

a transmission module, connected to the control module, for transmitting the object to be detected;

a ray source module, connected to the control module, for sending out rays to the transmission module according to the ray control instruction;

a detection module, configured to receive the ray penetrating the object to be detected moving on the transmission module, and convert it into data information formed by connecting digital signals end to end;

The processing and display module is connected to the detection module for processing and displaying the data information.

Referring to FIG. 1 as a reference below, the embodiments of the present application will be described in detail, so that those skilled in the technical field of the present application can easily implement them. The present application may be embodied in many different forms and is not limited to the embodiments described herein.

As shown in FIG. 1, a schematic structural diagram of a data transmission system based on a line array detector in an embodiment is shown, and the system includes:

The control module 11 is used to control the work of each module;

The transmission module 12 is connected to the control module 11 for transmitting the object to be detected;

The ray source module 13 is connected to the control module 11, and is used to send rays to the transmission module according to the ray control instruction;

Described detection module 14, is used for receiving the ray that penetrates the described object to be detected that moves on described transmission module, and converts it into the data information formed by each digital signal end-to-end;

The processing and display module 15 is connected to the detection module 14 for processing and displaying the data information.

Optionally, the conveying module 12 makes the object to be detected move on the conveying module 12 under the control of the control module 11 ; the movement may be maintaining different speeds or different motion states. Preferably, the conveying module 12 includes a conveying belt, and the object to be detected moves at a constant speed on the conveying belt.

Optionally, when the control module 11 detects that the light barrier signal changes, it sends a ray control instruction to the ray source module. Specifically, the ray control instruction includes: a ray emission instruction and a ray closing instruction.

Optionally, the ray source module 13 can emit rays of various shapes, types and intensities. Preferably, the ray source module emits fan-shaped X-rays.

Optionally, the radiation source module 13 is placed on the object to be detected that can be irradiated on the transmission module 12 and moved, that is, the radiation can pass through the object to be detected.

Optionally, the detection module 14 is placed at a position where the radiation from the inside of the object to be detected can be received for detection.

Optionally, the detection module 14 includes: an induction sub-module, which is used to convert the rays collected in each cycle into corresponding analog electrical signals; ASCI sub-module, which is used to digitize the analog electrical signals of the current cycle. Convert and output the digital signal of the previous cycle; the FPGA sub-module includes: a storage unit including a plurality of levels, used to receive the digital signal of the previous cycle and transmit it forward step by step until it is transmitted to the last level to achieve The digital signals are connected end to end.

In a specific embodiment, in each acquisition cycle, based on a custom-designed multi-channel high-speed acquisition chip ASIC, the analog electrical signal induced by the PD sensor undergoes multi-channel high-speed A/D conversion in ASCI; ASCI is doing integral amplification. At the same time, the digital signal of the previous cycle is read out and cached in the FPGA RAM; the FPGA RAM on each detection board transmits the digital signal to the previous level of FPGA RAM step by step, and finally caches it to the last level of FPGA RAM ; After the end-to-end splicing of the data is completed, the real-time upload and display of the data is completed through the Gigabit Ethernet interface; the forward-level transmission is synchronized step by step, which not only shortens the transmission distance, but also facilitates the control signal at a higher clock frequency As shown in FIG. 2, a schematic structural diagram of the detection module in this embodiment is described.

Optionally, the ASCI sub-module includes: a reset unit, used to start a new integration sequence for the next cycle; a CDS integration amplifying unit, used to integrate and amplify the induction analog signal of the current cycle; a multi-channel data output unit, It is used for performing signal conversion according to the integral amplification result of the previous cycle while the integral amplification is performed, and outputting the digital signal of the previous cycle. That is to say, in each integration period, it includes the signal conditioning process of "clear reset-CDS mode integration amplification-multi-channel high-speed (LVDS mode) data readout"; Each pixel channel on the sensing sub-module is integrated synchronously. The change of clearing the reset command state starts a new integration sequence for the next round, and at the same time performs A/D conversion and digital output on the previous integration result. Figure 3 shows the schematic diagram of the signal conditioning in the ASCI sub-module and Figure 4 Shown as a schematic diagram of the data transmission mode.

Optionally, the ASCI sub-module further includes: a serial shift unit for shifting the digital signal of the previous cycle to the storage unit in the FPGA module.

Optionally, the serial shift unit includes: a serial shift register. The result after signal conversion is stored in the serial shift register, and is shifted to the storage unit in the FPGA sub-module for buffering through N AD clocks; therefore, the data from the ASCI sub-module is directly shifted to the FPGA The storage unit in the sub-module realizes the parallel operation of data output and integration based on the principle of changing space for time.

Optionally, the FPGA sub-module includes: one or more interface units, including output and/or input instructions for receiving control signals and data. It realizes the long-distance transmission of multiplexed control signals and ensures the quality of the control signals, which is also the premise of the large load of the data acquisition board; at the same time, the input and output of data can be carried out simultaneously under one command, based on space-to-time conversion. The principle ensures that all data received by the data acquisition board is transmitted by the nearest adjacent detection board, avoiding the risks and shortcomings of long-distance transmission technology (long time consuming, low clock frequency of control signals, and poor anti-interference) . At the same time, for the detection boards with the same number of channels, the hardware design is completely consistent, that is, when the detection boards are connected in series to form a long line array, each detection board can be replaced with each other, which is convenient for the integration and repair of the whole machine.

Optionally, the number of Link interfaces of each detection module 14 is two, the input and output of data can be carried out simultaneously under one command, and the control signals can also be multiplexed with each other. As shown in FIG. 5 , for each detection module Schematic diagram of the transmission of the control command signal and digital data channel.

Optionally, the detection module further includes: an LVDS signal line module, including: one or more LVDS pins connected to the FPGA sub-module for parallel transmission of multiple pieces of data split in the FPGA sub-module. The data amount of each detection board is the same and fixed, and the transmission mode is the principle that each data is forwarded in a serial manner; the present invention splits the data into N segments of equal data first, and then passes through multiple pairs of LVDS Parallel transmission of N-segment data is realized, as shown in FIG. 6 , a schematic diagram of high-speed LVDS data transmission in this embodiment; based on the principle of changing space for time, less transmission time is achieved by increasing the number of LVDS pins; LVDS pins The signal exists not only in the ASIC sub-module, but also on each Link interface unit, which is connected to the FPGA pins.

Optionally, the detection module 14 is a linear array detector.

The system is described below with reference to specific embodiments.

Embodiment 1: A data transmission system applied to an X-ray linear array detector. The system includes:

The control module is used to control the work of each module;

a conveyor belt, connected to the control module, for conveying the object to be detected;

The X-ray source is connected to the control module for sending X-rays to the conveyor belt according to the ray control instruction;

The X-ray linear array detector is used for receiving the X-ray penetrating the object to be detected moving on the conveyor belt, and converting it into data information formed by connecting the digital signals end to end;

The PC and the display are connected to the detector for processing and displaying the data information.

The control module controls the conveyor belt so that the detected object moves at a constant speed on the conveyor belt. When the light barrier signal changes, the control module controls the X-ray source to emit X-rays. When the X-ray penetrates the detected object and reaches the X-ray linear array detector, it carries The X-ray of the internal information of the object is received and converted into electrical signals by the detector according to the progressive scanning method. The data acquisition and transmission system realizes the interaction with the PC, and completes the post-processing and real-time scrolling display of the image. The detection units are connected end to end in the detection direction, and the speed of the X-ray imaging area is consistent with the integration time of the X-ray linear array detector, that is, the conveyor belt speed and the scanning speed of the X-ray linear array detector must match, and must meet the following requirements formula:

Among them, V is the speed of the conveyor belt, D is the pixel interval, N is the number of pixel combinations (usually 1), T is the integration time, and M is the magnification (usually between 1 and 2).

However, when V is large, that is, the speed of the conveyor belt increases, T will decrease accordingly, that is, the scanning frame rate of the X-ray linear array detector is required to increase; a custom-designed ASIC is used, which contains multiple ADCs. The module, through the integral sequential circuit, executes integral amplification and A/D conversion in parallel to achieve multi-channel high-speed acquisition; when executing the integral amplification of the current frame, the digital signal of the previous frame will be read out at the same time, through multiple pairs of LVDS signals line, shifted into FPGA RAM at high speed. This time-series workflow method not only ensures that the pixel units on each detection board can synchronously collect the information of moving objects to prevent image distortion, but also can achieve less time-consuming shift through the high data clock frequency inside the ASIC , to ensure a sufficiently stable X-ray energy response under a small integration period.

Before the next integration period comes, it is necessary to summarize the digital signals buffered in the FPGA on the detection boards at all levels to the FPGA on the data acquisition board for image splicing, package and upload the host computer software for real-time display; the control signal is sent synchronously To each detection board, the data is transmitted to the previous stage, and the data is introduced from the data output end to the data input end of the previous stage detection board, that is, through multiple pairs of LVDS signal lines, the data between two adjacent FPGAs can be transmitted to each other. ; Under the action of the control signal of the ultra-high clock frequency, the scheme is supplemented by multiple pairs of LVDS signal lines, which realizes the purpose of changing the space for time, further compresses the transmission time, and the data transmission is stable and reliable.

When the data of one frame is aggregated to the FPGA of the data acquisition board, the FPGA completes the data splicing. At this time, the RAM buffer space of the FPGA can be used to perform multi-frame buffering, so as to match the large bandwidth of Gigabit Ethernet and make full use of it. The Gigabit Ethernet interface realizes high-speed upload of digital signals, and the multi-frame upload scheme also compresses the non-integration time-consuming in a scan cycle to a certain extent, and also reduces the number of data exchanges between the FPGA and the host computer software. Reduce the requirements for IPC configuration.

Similar to the principle of the above-mentioned embodiment, the present application provides a high-speed big data transmission method based on a linear array detector, which is applied to a high-speed big data transmission system based on a linear array detector. The system includes: a control module for Control each module to work; a transmission module, used to transmit the object to be detected; a ray source module, used to send rays to the transmission module according to the ray control instruction; the steps of the method are as follows:

receiving rays penetrating the object to be detected moving on the transmission module;

The rays are converted into data information formed by connecting the digital signals end to end.

Specific embodiments are provided below in conjunction with the accompanying drawings:

As shown in FIG. 7 , a schematic flowchart of a high-speed big data transmission method based on a linear array detector in an embodiment of the present application is shown.

The method includes:

S701: Receive rays that penetrate the object to be detected moving on the transmission module.

Optionally, when the transmission module receives the transmission control command, it makes the object to be detected move on the transmission module, and when the light barrier signal changes, the control module instructs the radiation source to emit radiation and receives the A ray that carries information inside an object.

S702: Convert the rays into data information formed by connecting the digital signals end to end.

Optionally, convert the rays collected in each cycle into corresponding analog electrical signals; digitally convert the analog electrical signals of the current cycle and output the digital signals of the previous cycle; receive the digital signals of the previous cycle And it is transmitted forward stage by stage until it is transmitted to the last stage to achieve end-to-end connection of each digital signal.

Optionally, in each acquisition cycle, based on the custom-designed multi-channel high-speed acquisition chip ASIC, the analog electrical signal induced by the PD sensor undergoes multi-channel high-speed A/D conversion in the ASCI; while the ASCI is doing integral amplification, The digital signal of the previous cycle is read out and cached in the FPGA RAM; the FPGA RAM on each detection board transfers the digital signal to the previous level of FPGARAM step by step, and finally caches it to the last level of FPGA RAM; when the data is completed After the end-to-end splicing, the real-time upload and display of data is completed through the Gigabit Ethernet interface; the transmission method of the previous stage is synchronized step by step, which not only shortens the transmission distance, but also is more conducive to the precise transmission and transmission of control signals at higher clock frequencies. control.

Optionally, start a new integration sequence for the next cycle; perform integration amplification on the induction analog signal of the current cycle; at the same time as the integration amplification, perform signal conversion according to the integration amplification result of the previous cycle, and output the previous cycle That is to say, in each integration period, it includes the process of "clear reset-CDS mode integration amplification-multi-channel high-speed (LVDS mode) data readout"; all detection boards in cascaded state, its Each pixel channel on the front-end sensing sub-module is integrated synchronously. The change of the state of the clear reset command starts the next round of new integration sequence, and at the same time performs A/D conversion and digital output on the previous integration result.

Optionally, the digital signal of the previous cycle is shifted to the storage unit of the upper-level FPGA.

Optionally, the digital signal of the previous cycle is shifted by the serial shift register to the storage unit of the upper-level FPGA. The result after signal conversion is stored in the serial shift register, and is shifted to the storage unit in the FPGA sub-module for buffering through N AD clocks; therefore, the data from the ASCI sub-module is directly shifted to the FPGA The storage unit in the sub-module realizes the parallel operation of data output and integration based on the principle of changing space for time.

Optionally, control signals and data output and/or input instructions are received through one or more interface units. It realizes the long-distance transmission of multiplexed control signals and ensures the quality of the control signals, which is also the premise for the data acquisition board to achieve a large load; at the same time, the input and output of data can be carried out simultaneously under one command, based on space-to-time change. The principle ensures that all data received by the data acquisition board is transmitted by the nearest adjacent detection board, avoiding the risks and shortcomings of long-distance transmission technology (long time consuming, low clock frequency of control signals, and poor anti-interference) . At the same time, for the detection boards with the same number of channels, the hardware design is completely consistent, that is, when the detection boards are connected in series to form a long line array, each detection board can be replaced with each other, which is convenient for the integration and repair of the whole machine.

Optionally, the split multi-segment data is transmitted in parallel through one or more LVDS pins. The data volume of each detection board is the same and fixed, and the transmission mode is the principle that each data is forwarded in a serial manner; the present invention splits the data into multiple segments of equal data, and realizes it through multiple pairs of LVDS. Parallel transmission of multi-segment data; based on the principle of space-for-time, by increasing the number of LVDS pins to achieve less transmission time; LVDS pin signals exist not only in ASIC sub-modules, but also on each Link interface unit. Connect to FPGA pins.

As shown in FIG. 8 , a schematic structural diagram of a high-speed big data transmission terminal 80 based on a linear array detector in an embodiment of the present application is shown.

The high-speed big data transmission terminal 80 based on the linear array detector includes: a memory 81 and a processor 82. The memory 81 is used to store computer programs; The detector's data transfer method.

Optionally, the number of the memories 81 may be one or more, the number of the processors 82 may be one or more, and one is taken as an example in FIG. 8 .

Optionally, the processor 82 in the high-speed big data transmission terminal 80 based on the linear array detector will load one or more instructions corresponding to the process of the application program into the memory 81 according to the steps described in FIG. 7 . , and the processor 82 runs the application program stored in the memory 81, thereby realizing various functions in the data transmission method based on the line array detector as described in FIG. 7 .

Optionally, the memory 81 may include but is not limited to high-speed random access memory and non-volatile memory. For example, one or more disk storage devices, flash memory devices or other non-volatile solid-state storage devices; the processor 81 may include, but is not limited to, a central processing unit (Central Processing Unit, CPU for short), a network processor (Network Processor) , referred to as NP), etc.; it can also be a digital signal processor (Digital Signal Processing, referred to as DSP), application specific integrated circuit (Application Specific Integrated Circuit, referred to as ASIC), Field Programmable Gate Array (Field-Programmable Gate Array, referred to as FPGA) Or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.

Optionally, the processor 82 can be a general-purpose processor, including a central processing unit (Central Processing Unit, referred to as CPU), a network processor (Network Processor, referred to as NP), etc.; it can also be a digital signal processor (Digital Signal processor). Processing, DSP for short), Application Specific Integrated Circuit (ASIC), Field-Programmable Gate Array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.

The present application also provides a computer-readable storage medium storing a computer program, and when the computer program runs, the data transmission method based on the line array detector as shown in FIG. 7 is implemented. The computer-readable storage medium may include, but is not limited to, floppy disks, optical disks, CD-ROMs (compact disk read only memory), magneto-optical disks, ROM (read only memory), RAM (random access memory), EPROM (erasable memory) except programmable read-only memory), EEPROM (electrically erasable programmable read-only memory), magnetic or optical cards, flash memory, or other types of media/machine-readable media suitable for storing machine-executable instructions. The computer-readable storage medium may be a product that is not connected to the computer device, or may be a component that is connected to the computer device for use.

To sum up, the high-speed big data transmission system, method, terminal and medium of the present application based on linear array detectors solve the detection requirements that cannot support higher transmission speed in the prior art, and the load capacity of a single data mining board is solved. Insufficient, more data mining boards are required for external synchronization to match, which further increases the cost and reduces the stability of the system. Some detection boards and data mining boards also use a single-ended bus transmission mode, which is more susceptible to electromagnetic environment. It is not conducive to the long-term stability of the system, and the detection board needs to be dialed in order or the last detection board needs to be terminated with matching resistors to work in cascade. The application can effectively improve the frame rate, meet the conveyor belt speed requirement of at least 2m/s, and improve the competitiveness of the product; and can reduce the cost of the whole machine, reduce the complexity of system integration, and improve the stability of the whole machine system. Therefore, the present application effectively overcomes various shortcomings in the prior art and has high industrial application value.

The above-mentioned embodiments merely illustrate the principles and effects of the present application, but are not intended to limit the present application. Anyone skilled in the art can make modifications or changes to the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed in this application should still be covered by the claims of this application.

Claims

A high-speed big data transmission system based on a linear array detector, characterized in that the system includes:

The control module is used to control the work of each module;

a transmission module, connected to the control module, for transmitting the object to be detected;

a ray source module, connected to the control module, for sending out rays to the transmission module according to the ray control instruction;

a detection module, configured to receive the ray penetrating the object to be detected moving on the transmission module, and convert it into data information formed by connecting digital signals end to end;

The processing and display module is connected to the detection module for processing and displaying the data information.
The high-speed big data transmission method based on a linear array detector according to claim 1, wherein the detection module comprises:

The ray sensing sub-module is used to convert the rays collected in each cycle into corresponding analog electrical signals respectively;

The ASCI sub-module is used to convert the analog electrical signal input in the current cycle and output the digital signal after the A/D conversion of the previous cycle;

The FPGA sub-module includes: a storage unit including a plurality of levels for receiving the digital signal of the previous cycle and transmitting it to the previous level step by step until it is transmitted to the last level to achieve end-to-end connection of the digital signals.
The high-speed big data transmission method based on a linear array detector according to claim 2, wherein the ASCI sub-module comprises:

The reset unit is used to start a new integration sequence for the next cycle;

The CDS integral amplifying unit is used to integrally amplify the induced analog signal of the current cycle;

The multi-channel data output unit is configured to perform digital conversion of the signal according to the integral amplification result of the previous cycle while the integral amplification is performed, and output the digital signal of the previous cycle.
The high-speed big data transmission method based on a linear array detector according to claim 2, wherein the ASCI sub-module further comprises:

The serial shift unit is used for shifting the digital signal of the previous cycle to the storage unit in the FPGA module.
The high-speed big data transmission method based on a linear array detector according to claim 3, wherein the FPGA sub-module comprises: a plurality of interface units, including: output and/or input for receiving control signals and data instruction.
The high-speed big data transmission method based on a linear array detector according to claim 1, wherein the detection module further comprises: an LVDS signal line module, comprising: one or more LVDS pins connected to the FPGA sub-module The module is used for parallel transmission of multiple pieces of data split in the FPGA sub-module.
A high-speed big data transmission method based on a linear array detector is characterized in that it is applied to a high-speed data transmission system based on a linear array detector, the system comprising: a control module for controlling the work of each module; a transmission module for using for transmitting the object to be detected; a ray source module for sending out rays to the transmission module according to a ray control instruction; the method includes:

receiving rays that penetrate the object to be detected moving on the transmission module;

The rays are converted into data information formed by connecting the digital signals end to end.
The high-speed big data transmission method based on a linear array detector according to claim 7, wherein the method of converting the rays into data information formed by connecting the digital signals end to end comprises:

Convert the rays collected in each cycle into corresponding analog electrical signals respectively;

Convert the analog electrical signal of the current cycle to digital signal and output the digital signal of the previous cycle;

Receive the digital signal of the previous cycle and transmit it to the previous stage step by step until it is transmitted to the last stage to achieve end-to-end connection of the digital signals.
A high-speed big data transmission terminal based on a linear array detector, characterized in that it includes:

memory for storing computer programs;

The processor is used for running the computer program to execute the high-speed big data transmission method based on the line array detector according to any one of claims 6 to 7.
A computer storage medium, characterized in that a computer program is stored, and when the computer program runs, the high-speed big data transmission method based on a linear array detector according to any one of claims 6 to 7 is implemented.