CN112383365B - Zero intermediate frequency automatic calibration method and system - Google Patents
Zero intermediate frequency automatic calibration method and system Download PDFInfo
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- CN112383365B CN112383365B CN202011291400.4A CN202011291400A CN112383365B CN 112383365 B CN112383365 B CN 112383365B CN 202011291400 A CN202011291400 A CN 202011291400A CN 112383365 B CN112383365 B CN 112383365B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
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- H04B17/00—Monitoring; Testing
- H04B17/10—Monitoring; Testing of transmitters
- H04B17/11—Monitoring; Testing of transmitters for calibration
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B17/00—Monitoring; Testing
- H04B17/20—Monitoring; Testing of receivers
- H04B17/21—Monitoring; Testing of receivers for calibration; for correcting measurements
Abstract
The invention provides a zero intermediate frequency automatic calibration method and a system, comprising the following steps: acquiring a zero intermediate frequency transmitting signal; transmitting the zero intermediate frequency transmitting signal to an FPGA (field programmable gate array), and analyzing the zero intermediate frequency transmitting signal by the FPGA to obtain the size of a mirror image signal of the transmitting signal and a corresponding calibration parameter; sending the size of the mirror image signal and the calibration parameter to an ARM memory, traversing the IQ signal phase sent to the DAC, and obtaining an optimal calibration result; and sending the optimal calibration result to a zero intermediate frequency compensation circuit by the FPGA for calibration compensation. By adopting the automatic calibration method, the automatic calibration is realized when the equipment is started, instruments and manual intervention are not needed, and the zero intermediate frequency optimal calibration parameter can be obtained without high and low temperature tests, so that the test efficiency is obviously improved.
Description
Technical Field
The invention relates to the technical field of wireless communication, in particular to a zero intermediate frequency automatic calibration method and a zero intermediate frequency automatic calibration system.
Background
In the field of traditional communications, radio frequency transceiving is built by using discrete devices, a specific framework is shown in fig. 1, and discrete schemes widely adopt a transmitting link by using a DAC, an intermediate frequency filter, intermediate frequency amplification, a mixer, radio frequency amplification and a radio frequency filter. As communication systems have higher and higher requirements for rate transmission, bandwidth requirements are wider and lower power consumption is required.
In order to reduce the size of the board and the power consumption of the board, and facilitate chip integration, the radio frequency transceiving with zero intermediate frequency architecture gradually replaces the traditional discrete radio frequency transceiving link, and the radio frequency transceiver frame with zero intermediate frequency is shown in fig. 2. The zero intermediate frequency radio frequency transceiver directly shifts the baseband signal to the radio frequency signal without intermediate frequency amplification, filtering and secondary frequency conversion. However, the zero-if scheme is not a perfect solution, and the zero-if integrated transceiver adopts an analog circuit, the analog circuit cannot make the DC OFFSET and the phase of the analog IQ signal completely consistent, which may cause local oscillator leakage and mirror image at the output of the zero-if transmission link, and the DC OFFSET may drift with the temperature, which may cause the leakage of the DCOFFSET to vary continuously with the temperature, which may cause the output frequency spectrum of the transmitter to be stray, which may affect the radio frequency index of the transmitter, which may cause the radio frequency index not to satisfy the 3GPP standard.
The traditional zero intermediate frequency scheme-based calibration mainly adopts the following two methods:
the method comprises the following steps: the method comprises the steps that an artificial calibration method is adopted, an instrument is used for testing the effects of local oscillator leakage and image rejection of output signals of a zero intermediate frequency transceiver, and the local oscillator leakage and image rejection capability of a zero intermediate frequency transmitting chip are adjusted by adjusting the DC OFFSET and the phase of IQ (or using a DC OFFSET and a phase adjusting chip which are provided with chips and support IQ) of a baseband to the zero intermediate frequency transmitter; and transmitting the related records of the traversed IQ to the DC OFFSET and the phase deviation value of the zero intermediate frequency transmitter IQ each time, traversing the related values of the IQ, and storing the traversed related values in a storage of the single board. Simultaneously, each device carries out high and low temperature same tests, and stores the optimal DC OFFSET value of high and low temperature in a memory; and 3, selecting an optimal value by the single-board CPU to ensure that the single-board CPU can be used in each working process.
The second method comprises the following steps: selecting an IQ-supporting DC OFFSET and a phase adjusting chip, externally arranging an additional feedback signal link, and spontaneously generating a single-tone signal when equipment is started; and the transmitting signal is acquired and analyzed through an external feedback signal acquisition link. Obtaining local oscillator leakage and mirror images of the transmitting signals; in the baseband processing unit, the local oscillator leakage signal and the mirror image are calculated, the calibration parameters of the chip are adjusted, and the local oscillator leakage signal and the mirror image optimal value are selected and stored in a memory. And when the temperature is high or low, repeatedly calculating to obtain the optimal DCOFFSET parameter value of the high temperature and the low temperature.
The drawbacks of the above method are as follows:
in the first method, an expensive signal source and a spectrometer are adopted for testing in a matching manner, the predicted traversing work task needs 20 minutes, high and low temperature testing links are added, and particularly during batch production, the efficiency of batch production is reduced by 40 percent as each testing time is increased by about 40 minutes;
in the second method, the DC OFFSET and the phase chip can be adjusted by adopting the support chip, and meanwhile, high and low temperature testing links are required to be added, so that the mass production testing work is complicated, and the testing efficiency is reduced by more than 20% in large-scale production.
Disclosure of Invention
The invention provides a zero intermediate frequency automatic calibration method and a zero intermediate frequency automatic calibration system, which are used for solving the defects that external equipment is required to be used when zero intermediate frequency calibration is carried out in the prior art, and high and low temperature tests cannot be avoided.
In a first aspect, the present invention provides a zero intermediate frequency automatic calibration method, including:
collecting a zero intermediate frequency transmitting signal;
transmitting the zero intermediate frequency transmitting signal to an FPGA (field programmable gate array), and analyzing the zero intermediate frequency transmitting signal by the FPGA to obtain the size of a mirror image signal of the transmitting signal and a corresponding calibration parameter;
sending the size of the mirror image signal and the calibration parameter to an ARM memory, traversing the IQ signal phase sent to the DAC, and obtaining an optimal calibration result;
and sending the optimal calibration result to a zero intermediate frequency compensation circuit by the FPGA for calibration compensation.
Further, the acquiring the zero intermediate frequency transmission signal specifically includes:
when the single board is started, the FPGA baseband part generates a single-tone point frequency test signal which has a preset deviation from a preset central frequency point, and the single-tone point frequency test signal is sent to a zero intermediate frequency transmitting part;
and acquiring the zero intermediate frequency transmitting signal generated by the zero intermediate frequency transmitting part by a signal feedback acquisition circuit.
Further, the zero intermediate frequency transmission signal includes an I signal and a Q signal, wherein:
the I signal includes a first amplitude and a first DC OFFSET value;
the Q signal includes a second amplitude, a second DC OFFSET value, and a phase error.
Further, the transmitting the zero intermediate frequency transmitting signal to the FPGA, and the FPGA analyzing the zero intermediate frequency transmitting signal to obtain the size of the mirror image signal of the transmitting signal and the corresponding calibration parameter specifically include:
and carrying out FFT analysis on the zero intermediate frequency transmitting signal to obtain the I signal image leakage size and the Q signal image leakage size, and adjusting the phase error.
Further, the sending the size of the image signal and the calibration parameter to an ARM memory, traversing the IQ signal phase sent to the DAC, and obtaining an optimal calibration result specifically includes:
recalculating the I signal image leakage magnitude and the Q signal image leakage magnitude to obtain an optimal image magnitude value and a corresponding phase error;
storing the optimal mirror size value and the corresponding phase error in the ARM memory;
traversing the phase of the IQ signal, acquiring a high-pass filter with a preset bandwidth, and filtering a direct-current part in a DC OFFSET in the IQ signal;
adjusting the first DC OFFSET value and the second DC OFFSET value by an external feedback hardware channel by adopting a low-pass filter in the reverse direction of the high-pass filter with the preset bandwidth;
and transmitting the adjusted first DC OFFSET value and the second DC OFFSET value to the FPGA baseband part to obtain the optimal DC OFFSET value, and updating in real time.
In a second aspect, the present invention further provides a zero intermediate frequency automatic calibration system, including:
the acquisition module is used for acquiring a zero intermediate frequency transmission signal;
the analysis module is used for transmitting the zero intermediate frequency transmitting signal to the FPGA, and the FPGA analyzes the zero intermediate frequency transmitting signal to obtain the size of a mirror image signal of the transmitting signal and a corresponding calibration parameter;
the processing module is used for sending the size of the mirror image signal and the calibration parameter to an ARM memory, traversing the IQ signal phase sent to the DAC and obtaining an optimal calibration result;
and the compensation module is used for sending the optimal calibration result to the zero intermediate frequency compensation circuit by the FPGA for calibration compensation.
Further, the acquisition module is specifically configured to:
when the single board is started, the FPGA baseband part generates a single-tone point frequency test signal which has a preset deviation from a preset central frequency point, and the single-tone point frequency test signal is sent to a zero intermediate frequency transmitting part;
and acquiring the zero intermediate frequency transmitting signal generated by the zero intermediate frequency transmitting part by a signal feedback acquisition circuit.
Further, the analysis module is specifically configured to:
and carrying out FFT analysis on the zero intermediate frequency transmitting signal to obtain the I signal image leakage magnitude and the Q signal image leakage magnitude, and adjusting the phase error.
In a third aspect, the present invention further provides an electronic device, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the zero intermediate frequency automatic calibration method according to any one of the above descriptions.
In a fourth aspect, the present invention also provides a non-transitory computer readable storage medium having stored thereon a computer program which, when executed by a processor, performs the steps of the zero intermediate frequency auto-calibration method as described in any of the above.
According to the zero intermediate frequency automatic calibration method and the zero intermediate frequency automatic calibration system, the automatic calibration is realized when the equipment is started by adopting the automatic calibration method, the instrument and the manual intervention are not needed, the zero intermediate frequency optimal calibration parameter can be obtained without high and low temperature tests, and the test efficiency is obviously improved.
Drawings
In order to more clearly illustrate the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a block diagram of a conventional radio frequency transmission link device provided in the prior art;
fig. 2 is a block diagram of a conventional rf zero if transmission link device provided in the prior art;
FIG. 3 is a schematic flow chart of a zero intermediate frequency automatic calibration method provided by the present invention;
FIG. 4 is a block diagram of a zero intermediate frequency internal link provided by the present invention;
FIG. 5 is a block diagram of a radio frequency zero IF transmission link apparatus using an automatic calibration algorithm according to the present invention;
FIG. 6 is a schematic diagram of the normal spectrum and DC OFFSET position waveforms provided by the present invention;
FIG. 7 is a schematic diagram of a frequency spectrum waveform filtered by a high-pass filter according to the present invention;
FIG. 8 is a schematic diagram of the waveform of the spectrum after the inverse low-pass filter processing provided by the present invention;
FIG. 9 is a schematic diagram of a zero-IF automatic calibration system provided by the present invention;
fig. 10 is a schematic structural diagram of an electronic device provided by the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Aiming at the problems that manual calibration is needed, the calibration of the output signal of a test transceiver is realized by means of instruments and meters, and the optimal parameters are obtained by adopting high-temperature and low-temperature tests in the prior art, the invention provides a zero intermediate frequency automatic calibration method.
Fig. 3 is a schematic flow chart of the zero intermediate frequency automatic calibration method provided by the present invention, as shown in fig. 3, including:
s1, acquiring a zero intermediate frequency transmitting signal;
s2, transmitting the zero intermediate frequency transmitting signal to an FPGA (field programmable gate array), and analyzing the zero intermediate frequency transmitting signal by the FPGA to obtain the size of a mirror image signal of the transmitting signal and a corresponding calibration parameter;
s3, sending the size of the image signal and the calibration parameter to an ARM memory, traversing the IQ signal phase sent to the DAC, and obtaining an optimal calibration result;
and S4, the FPGA sends the optimal calibration result to a zero intermediate frequency compensation circuit for calibration compensation.
Specifically, because the DAC outputs an IQ signal to the IQ modulator as an analog IQ signal, and a hardware block diagram is as shown in fig. 4, it is theoretically required that the IQ signal is completely orthogonal, but the IQ signal cannot be guaranteed to be completely orthogonal by an analog IQ signal theory, the IQ signal has OFFSET of DCOFFSET, and meanwhile, the DC OFFSET drifts along with temperature change, which may cause local oscillator leakage and mirror image at the output of a zero intermediate frequency transmission link, which may cause spurs in the output spectrum of the transmitter, and particularly, the DC OFFSET affects the radio frequency index of the transmitter along with high and low temperature changes, which may cause the radio frequency index not to satisfy the 3GPP standard, which may cause differences in signal consistency, and the local oscillator leakage and the mirror image signal of each device are different in size, which may cause high and low temperature individual calibration of each device, which may increase about 40 minutes in each test time during batch production, and may reduce the efficiency of batch production by 30%.
Increase the transmission signal feedback acquisition circuit through the hardware, gather zero intermediate frequency transmission chip transmission signal, gather through zero intermediate frequency receiver and transmit for FPGA, FPGA baseband part carries out FFT analysis to the signal of sampling, and the local oscillator of assay emission signal reveals and mirror image signal size, and during calibration DC OFFSET, baseband FPGA increases the wave filter, and accurate discernment DC OFFSET reveals the value, real-time calibration. Meanwhile, the corresponding size of the image signal is transmitted to a storage device of the ARM, then IQ signal phases sent to the DAC are traversed, then analysis is carried out, finally, the value obtained by the calculation of the ARM of the optimal result is sent to the FPGA, and the FPGA sends the value to the zero intermediate frequency compensation circuit.
Meanwhile, in order to solve the problem that the DC OFFSET changes due to the temperature change of the equipment, the DC OFFSET is calibrated in real time, and the problem that the calibration work can be finished only by manually carrying out high and low temperatures in the traditional method is solved. And roughly processing the flow, carrying out real-time statistics on the power in the sending direction and the power fed back by peripheral hardware by the baseband FPGA, calculating the minimum value of the DC OFFSET, and updating the optimal DC OFFSET calibration parameter value in real time.
By adopting the automatic calibration method, the invention realizes automatic calibration when the equipment is started, does not need instrument and manual intervention, and can obtain the zero intermediate frequency optimal calibration parameter without high and low temperature tests, thereby obviously improving the test efficiency.
Based on the above embodiment, step S1 in the method specifically includes:
when the single board is started, the FPGA baseband part generates a single-tone point frequency test signal which has a preset deviation from a preset central frequency point, and the single-tone point frequency test signal is sent to a zero intermediate frequency transmitting part;
and acquiring the zero intermediate frequency transmitting signal generated by the zero intermediate frequency transmitting part by a signal feedback acquisition circuit.
Wherein the zero intermediate frequency transmit signal comprises an I signal and a Q signal, wherein:
the I signal includes a first amplitude and a first DC OFFSET value;
the Q signal includes a second amplitude, a second DC OFFSET value, and a phase error.
Specifically, when the single board is started each time, the FPGA part sends a single-tone dot-frequency test signal to be output to the zero intermediate frequency transmitter, the hardware is additionally provided with a transmission signal feedback acquisition circuit to acquire a transmission signal of a zero intermediate frequency transmission chip, the transmission signal is acquired and transmitted to the FPGA through the zero intermediate frequency receiver, the FPGA baseband part carries out FFT analysis on the sampled signal to obtain mirror images of I and Q signals, and relevant parameters of I and Q sent by the FPGA are adjusted as follows:
I(n)＝AI cos(2πfn+θ)+d1
wherein A isIAnd AQThe amplitudes of the I and Q signals are respectively,
as phase error, d1、d2The DC OFFSET values of the I path and the Q path are respectively.
Based on any of the above embodiments, step S2 in the method specifically includes:
and carrying out FFT analysis on the zero intermediate frequency transmitting signal to obtain the I signal image leakage size and the Q signal image leakage size, and adjusting the phase error.
Specifically, the FPGA carries out FFT analysis on the signal transmitted by the zero intermediate frequency receiver to obtain the mirror leakage magnitude of the I and Q signals, and adjusts the phase error
Based on any of the above embodiments, step S3 in the method specifically includes:
recalculating the I signal image leakage and the Q signal image leakage to obtain an optimal image size value and a corresponding phase error;
storing the optimal mirror size value and the corresponding phase error in the ARM memory;
traversing the phase of the IQ signal, acquiring a high-pass filter with a preset bandwidth, and filtering a direct-current part in a DC OFFSET in the IQ signal;
adjusting the first DC OFFSET value and the second DC OFFSET value by an external feedback hardware channel by adopting a low-pass filter in reverse direction to the high-pass filter with the preset bandwidth;
and transmitting the adjusted first DC OFFSET value and the second DC OFFSET value to the FPGA baseband part to obtain the optimal DC OFFSET value, and updating in real time.
Specifically, a new image leakage value is obtained by repeated calculation, and an optimal image leakage value and a corresponding image leakage value are obtained by calculation
The value is obtained. Stored in a memory device on board for the device to recall when it is operational. And sending the value obtained by the calculation of the optimal result through the ARM to the FPGA, and sending the value to the zero intermediate frequency compensation circuit by the FPGA, as shown in figure 5.
When the single board works in real time, a baseband sends broadband signals to the FPGA, similar waveforms are shown in figure 6, and it can be seen from the figure that because the DC OFFSET theory is at the central frequency point of the signals, the actual whole signal frequency spectrum covers the position of the DC OFFSET, if the signals are not processed, the signals acquired by external feedback cannot be distinguished from the leakage of the actual frequency spectrum signals and the DC OFFSET behind the DAC, in order to solve the problem, a part of the sending part of the FPGA adds a high-pass filter with the bandwidth of 1KHZ on a normal signal link, and the direct current position is completely filtered. The amplitude-frequency response of a particular filter is shown in fig. 7.
Through an external feedback hardware channel, a baseband FPGA receives signals, a reverse 1KHZ low-pass filter is adopted, the specific amplitude-frequency characteristic is shown in figure 8, the calculated value is DC OFFSET leakage generated by a zero intermediate frequency transmitter, and d is adjusted1，d2Re-counting the fed-back DC OFFSET value, and real-time calculating the minimum DC OFFSET value and the corresponding d1，d2And the baseband FPGA is given again to ensure that the DC OFFSET value is always optimal, and meanwhile, the real-time updating ensures that the optimal DC OFFSET calibration parameter is not required to be obtained by each high-temperature and low-temperature device.
The invention adopts an automatic calibration method, the equipment can be automatically calibrated when being started, instruments and other human interventions are not needed, the optimal calibration parameters are not needed to be obtained by each equipment at high and low temperatures, and the test efficiency can be improved by more than 20 percent.
The zero intermediate frequency automatic calibration system provided by the present invention is described below, and the zero intermediate frequency automatic calibration system described below and the zero intermediate frequency automatic calibration method described above may be referred to in a corresponding manner.
Fig. 9 is a schematic structural diagram of the zero intermediate frequency automatic calibration system provided by the present invention, as shown in fig. 9, including: the system comprises an acquisition module 91, an analysis module 92, a processing module 93 and a compensation module 94;
the acquisition module 91 is used for acquiring a zero intermediate frequency transmission signal; the analysis module 92 is configured to transmit the zero intermediate frequency transmit signal to the FPGA, and the FPGA analyzes the zero intermediate frequency transmit signal to obtain a size of an image signal of the transmit signal and a corresponding calibration parameter; the processing module 93 is configured to send the size of the image signal and the calibration parameter to an ARM memory, traverse the IQ signal phase sent to the DAC, and obtain an optimal calibration result; the compensation module 94 is configured to send the optimal calibration result to the zero intermediate frequency compensation circuit for calibration compensation by the FPGA.
By adopting the automatic calibration method, the invention realizes automatic calibration when the equipment is started, does not need instrument and manual intervention, and can obtain the zero intermediate frequency optimal calibration parameter without high and low temperature tests, thereby obviously improving the test efficiency.
Based on the above embodiment, the acquisition module 91 is specifically configured to:
when the single board is started, the FPGA baseband part generates a single-tone point frequency test signal which has a preset deviation from a preset central frequency point, and the single-tone point frequency test signal is sent to a zero intermediate frequency transmitting part;
and acquiring the zero intermediate frequency transmitting signal generated by the zero intermediate frequency transmitting part by a signal feedback acquisition circuit.
Based on any of the above embodiments, the analysis module 92 is specifically configured to:
and carrying out FFT analysis on the zero intermediate frequency transmitting signal to obtain the I signal image leakage magnitude and the Q signal image leakage magnitude, and adjusting the phase error.
Fig. 10 illustrates a physical structure diagram of an electronic device, and as shown in fig. 10, the electronic device may include: a processor (processor) 1010, a communication interface (communication interface) 1020, a memory (memory) 1030, and a communication bus 1040, wherein the processor 1010, the communication interface 1020, and the memory 1030 communicate with each other via the communication bus 1040. Processor 1010 may invoke logic instructions in memory 1030 to perform a zero intermediate frequency auto-calibration method comprising: acquiring a zero intermediate frequency transmitting signal; transmitting the zero intermediate frequency transmitting signal to an FPGA (field programmable gate array), and analyzing the zero intermediate frequency transmitting signal by the FPGA to obtain the size of a mirror image signal of the transmitting signal and a corresponding calibration parameter; sending the size of the mirror image signal and the calibration parameter to an ARM memory, traversing the IQ signal phase sent to the DAC, and obtaining an optimal calibration result; and sending the optimal calibration result to a zero intermediate frequency compensation circuit by the FPGA for calibration compensation.
Furthermore, the logic instructions in the memory 1030 can be implemented in software functional units and stored in a computer readable storage medium when the logic instructions are sold or used as independent products. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-only memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.
In another aspect, the present invention also provides a computer program product, the computer program product comprising a computer program stored on a non-transitory computer-readable storage medium, the computer program comprising program instructions, which when executed by a computer, enable the computer to perform the zero intermediate frequency auto-calibration method provided by the above methods, the method comprising: acquiring a zero intermediate frequency transmitting signal; transmitting the zero intermediate frequency transmitting signal to an FPGA (field programmable gate array), and analyzing the zero intermediate frequency transmitting signal by the FPGA to obtain the size of a mirror image signal of the transmitting signal and a corresponding calibration parameter; sending the size of the mirror image signal and the calibration parameter to an ARM memory, traversing the IQ signal phase sent to the DAC, and obtaining an optimal calibration result; and sending the optimal calibration result to a zero intermediate frequency compensation circuit by the FPGA for calibration compensation.
In yet another aspect, the present invention also provides a non-transitory computer readable storage medium having stored thereon a computer program, which when executed by a processor is implemented to perform the zero intermediate frequency auto-calibration method provided above, the method comprising: collecting a zero intermediate frequency transmitting signal; transmitting the zero intermediate frequency transmitting signal to an FPGA (field programmable gate array), and analyzing the zero intermediate frequency transmitting signal by the FPGA to obtain the size of a mirror image signal of the transmitting signal and a corresponding calibration parameter; sending the size of the mirror image signal and the calibration parameter to an ARM memory, traversing the IQ signal phase sent to the DAC, and obtaining an optimal calibration result; and sending the optimal calibration result to a zero intermediate frequency compensation circuit by the FPGA for calibration compensation.
The above-described embodiments of the apparatus are merely illustrative, and the units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment. One of ordinary skill in the art can understand and implement it without inventive effort.
Through the above description of the embodiments, those skilled in the art will clearly understand that each embodiment can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware. With this understanding in mind, the above-described technical solutions may be embodied in the form of a software product, which can be stored in a computer-readable storage medium such as ROM/RAM, magnetic disk, optical disk, etc., and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the methods described in the embodiments or some parts of the embodiments.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (4)
1. A zero intermediate frequency automatic calibration method is characterized by comprising the following steps:
acquiring a zero intermediate frequency transmitting signal;
transmitting the zero intermediate frequency transmitting signal to an FPGA (field programmable gate array), and analyzing the zero intermediate frequency transmitting signal by the FPGA to obtain the size of a mirror image signal of the transmitting signal and a corresponding calibration parameter;
sending the size of the mirror image signal and the calibration parameter to an ARM memory, traversing the IQ signal phase sent to the DAC, and obtaining an optimal calibration result;
the FPGA sends the optimal calibration result to a zero intermediate frequency compensation circuit for calibration compensation;
the zero intermediate frequency emission signal acquisition specifically comprises:
when the single board is started, the FPGA baseband part generates a single-tone point frequency test signal which has a preset deviation from a preset central frequency point, and the single-tone point frequency test signal is sent to a zero intermediate frequency transmitting part;
acquiring the zero intermediate frequency transmitting signal generated by the zero intermediate frequency transmitting part by a signal feedback acquisition circuit;
the zero intermediate frequency transmission signal comprises an I signal and a Q signal, wherein:
the I signal includes a first amplitude and a first DC OFFSET value;
the Q signal includes a second amplitude, a second DC OFFSET value, and a phase error;
the zero intermediate frequency transmitting signal is transmitted to the FPGA, the FPGA analyzes the zero intermediate frequency transmitting signal to obtain the size of the mirror image signal of the transmitting signal and the corresponding calibration parameter, and the method specifically comprises the following steps:
performing FFT analysis on the zero intermediate frequency transmitting signal to obtain the I signal image leakage size and the Q signal image leakage size, and adjusting the phase error;
the sending the size of the mirror image signal and the calibration parameter to an ARM memory, traversing the IQ signal phase sent to the DAC, and obtaining an optimal calibration result specifically comprises:
recalculating the I signal image leakage and the Q signal image leakage to obtain an optimal image size value and a corresponding phase error;
storing the optimal mirror size value and the corresponding phase error in the ARM memory;
traversing the phase of the IQ signal, acquiring a high-pass filter with a preset bandwidth, and filtering a direct current part in a DC OFFSET in the IQ signal;
adjusting the first DC OFFSET value and the second DC OFFSET value by an external feedback hardware channel by adopting a low-pass filter in the reverse direction of the high-pass filter with the preset bandwidth;
and transmitting the adjusted first DC OFFSET value and the second DC OFFSET value to the FPGA baseband part to obtain an optimal DC OFFSET value, and updating in real time.
2. A zero intermediate frequency automatic calibration system, comprising:
the acquisition module is used for acquiring a zero intermediate frequency transmission signal;
the analysis module is used for transmitting the zero intermediate frequency transmitting signal to the FPGA, and the FPGA analyzes the zero intermediate frequency transmitting signal to obtain the size of a mirror image signal of the transmitting signal and a corresponding calibration parameter;
the processing module is used for sending the size of the mirror image signal and the calibration parameter to an ARM memory, traversing the IQ signal phase sent to the DAC and obtaining an optimal calibration result;
the compensation module is used for sending the optimal calibration result to the zero intermediate frequency compensation circuit by the FPGA for calibration compensation;
the acquisition module is specifically configured to:
when the single board is started, the FPGA baseband part generates a single-tone point frequency test signal which has a preset deviation from a preset central frequency point, and the single-tone point frequency test signal is sent to a zero intermediate frequency transmitting part;
acquiring the zero intermediate frequency transmitting signal generated by the zero intermediate frequency transmitting part by a signal feedback acquisition circuit;
the zero intermediate frequency transmission signal comprises an I signal and a Q signal, wherein:
the I signal includes a first amplitude and a first DC OFFSET value;
the Q signal comprises a second amplitude, a second DC OFFSET value, and a phase error;
the analysis module is specifically configured to:
performing FFT analysis on the zero intermediate frequency transmitting signal to obtain the I signal image leakage size and the Q signal image leakage size, and adjusting the phase error;
the processing module is specifically configured to:
recalculating the I signal image leakage magnitude and the Q signal image leakage magnitude to obtain an optimal image magnitude value and a corresponding phase error;
storing the optimal mirror size value and the corresponding phase error in the ARM memory;
traversing the phase of the IQ signal, acquiring a high-pass filter with a preset bandwidth, and filtering a direct-current part in a DC OFFSET in the IQ signal;
adjusting the first DC OFFSET value and the second DC OFFSET value by an external feedback hardware channel by adopting a low-pass filter in reverse direction to the high-pass filter with the preset bandwidth;
and transmitting the adjusted first DC OFFSET value and the second DC OFFSET value to the FPGA baseband part to obtain the optimal DC OFFSET value, and updating in real time.
3. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor when executing the computer program implements the steps of the zero intermediate frequency auto-calibration method according to claim 1.
4. A non-transitory computer-readable storage medium, having stored thereon a computer program, wherein the computer program, when executed by a processor, performs the steps of the zero intermediate frequency auto-calibration method according to claim 1.
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