automatic calibration method for local oscillator mirror image of RF chip
Technical Field
the invention relates to an automatic calibration method for local oscillator mirror images of integrated broadband RF (radio frequency) transceiver chips, which is mainly used for wireless transceivers.
background
the super-heterodyne architecture is considered the most reliable transceiver topology because excellent selectivity and sensitivity can be obtained by properly selecting the intermediate frequency filter. Due to the fact that the frequency conversion stages are arranged, the performance of the receiver cannot be affected by the direct current deviation and the local oscillator leakage problem. However, the image rejection filter and the channel selection filter are high-Q bandpass filters, which can only be implemented off-chip, thereby increasing the cost and size of the receiver. Currently, there are great difficulties in integrating these two filters together with other radio frequency circuits on one chip using integrated circuit manufacturing processes. Therefore, monolithic integration of a superheterodyne receiver is difficult to achieve due to limitations in process technology.
Because the zero intermediate frequency transceiver does not need an off-chip high-Q value band-pass filter, single-chip integration can be realized, which is widely regarded, and the structure of the zero intermediate frequency transceiver is much simpler than that of a superheterodyne transceiver. The received radio frequency signal is amplified by a filter and a low noise amplifier, and then mixed with two paths of local oscillator signals which are orthogonal to each other to generate an in-phase baseband signal and an orthogonal baseband signal respectively. Because the frequency of the local oscillation signal is the same as that of the radio frequency signal, the baseband signal is directly generated after frequency mixing, and channel selection and gain adjustment are carried out on the baseband and are completed by a low-pass filter and a variable gain amplifier on a chip.
Although the architecture of the zero-if transceiver has the advantages of high integration and low power consumption, the zero-if architecture itself is not perfect, and has some problems, such as: local oscillator leakage, even order distortion, DC offset, flicker noise, I/Q mismatch, etc.
Disclosure of Invention
The invention provides a method for automatically calibrating local oscillator leakage stray and mirror image stray of a sending end by using a combination of an MCU (single chip microcomputer), an FPGA (field programmable gate array) and an integrated broadband RF transceiver chip (zero intermediate frequency transceiver chip). By using the method, the MCU can finish the calibration of local oscillator leakage stray and mirror stray of the transmitting end of the zero intermediate frequency transceiver chip only by electrifying the equipment and turning on the calibration switch. Because the calibration scheme of the transceiver chip cannot meet the radio frequency index requirement, the calibration needs to be manually carried out to meet the index; when manual calibration is carried out, time and labor are consumed, and instruments and meters are used, so that the overall production efficiency is low and the cost is high.
the technical solution adopted by the invention is as follows: when the hardware is designed, the radio frequency signal sent from the RF chip Transmission (TX) port is returned to the RF chip Receiving (RX) port through a line. The configuration of the RF chip at the transmitting end keeps the normal configuration thereof all the time in the using process, and the configuration of the RF chip at the receiving end carries out corresponding local oscillation adjustment according to the frequency band of the received radio frequency signal. The FPGA program is written to send a single-tone signal to the sending end RF chip, the receiving end RF chip changes the received RF signal into a baseband signal, and the baseband signal enters the FPGA and then is subjected to narrow-band filtering to obtain a main signal, a local oscillator signal and a mirror image signal. The local oscillator calibration register and the mirror image calibration register in the transmitting end RF chip (TX) are adjusted to obtain the optimal result, so that the local oscillator signal and the mirror image signal are as small as possible, and the modified configuration of the transmitting end RF chip TX is stored.
The specific technical scheme of the invention is as follows:
an automatic calibration system for local oscillator mirror images of an RF chip comprises an MCU, an FPGA, a transmitting end RF chip TX, a receiving end RF chip RX, a transmitting antenna and a receiving antenna; the FPGA, the transmitting end RF chip TX and the transmitting antenna are sequentially connected, the receiving antenna, the receiving end RF chip RX and the FPGA are sequentially connected, and the MCU is respectively connected with the FPGA, the transmitting end RF chip TX and the receiving end RF chip RX; the FPGA comprises a DDS module, an MCU interface, a frequency conversion module, a narrow-band filtering module and a power statistics module; the DDS module is connected with the transmitting end RF chip TX, and the receiving end RF chip RX, the frequency conversion module, the narrow band filtering module and the power statistics module are sequentially connected.
The MCU is used for configuring a transmitting end RF chip TX, a receiving end RF chip RX and a register of a read-write FPGA, and the local oscillator mirror image calibration function of the RF chip is completed by reading the power value counted by the FPGA power counting module and then adjusting the configuration of the transmitting end RF chip TX;
The transmitting end RF chip TX and the receiving end RF chip RX are RF chips, the transmitting end RF chip TX is used for transmitting radio frequency signals, and the receiving end RF chip RX is used for receiving radio frequency signals;
The transmitting antenna is used for converting a radio frequency signal sent by the transmitting end RF chip into a wireless signal;
The receiving antenna is used for converting the air wireless signal into a radio frequency signal and sending the radio frequency signal to the RF chip of the receiving end;
Flow direction of calibration signal: the FPGA sends a calibration signal, the calibration signal is changed into a radio frequency signal through a transmitting end RF chip TX, the radio frequency signal is changed into a baseband signal through a receiving end RF chip RX, and the FPGA receives the baseband signal.
The FPGA chip generates single-tone signals and is output by a transmitting end RF chip TX, a radio frequency link switch of a receiving end RF chip RX is switched through the MCU, main signals transmitted by the transmitting end RF chip TX, local oscillator leakage stray and mirror image stray are given to the receiving end RF chip RX and then transmitted to the FPGA chip, the radio frequency signals received by the FPGA chip are subjected to narrow-band filtering, main signal power is obtained, local oscillator leakage stray power and mirror image stray power are obtained, and the local oscillator leakage stray power and the mirror image stray power are minimized by repeatedly adjusting corresponding register values in the transmitting end RF chip TX through the MCU.
The method specifically comprises the following steps:
(1) after the equipment is normally powered on, entering a local oscillator and mirror image calibration mode through the MCU;
(2) the transmitting end RF chip TX performs chip self calibration, and the MCU configures the receiving end RF chip RX so that the receiving end RF chip RX and the transmitting end RF chip TX are on the same frequency band and can receive a returned radio frequency signal;
(3) The MCU controls a DDS module of the FPGA, and sends a single-tone signal with fixed frequency to the RF chip TX at the transmitting end through the TX interface;
(4) The MCU controls a radio frequency link switch of the receiving end RF chip RX, so that a radio frequency signal sent by the transmitting end RF chip TX enters a receiving link after passing through a radio frequency link and then returns to the receiving end RF chip RX, and the whole signal is sent and received to form a loop;
(5) The FPGA carries out frequency conversion, narrow-band filtering and power statistics on the received RX signal to respectively obtain calibration signal power, local oscillator signal power and mirror image signal power; the FPGA receives baseband signals, frequency conversion is carried out by adopting a complex multiplier, narrow-band filtering is carried out by adopting an integral comb filter, and the power statistics module is realized by adopting a method of averaging after accumulative summation;
(6) The MCU carries out local oscillator mirror image calibration through a calibration algorithm, the calibration algorithm comprises coarse calibration and fine calibration, the calibration algorithm is carried out repeatedly, the register values of the local oscillator calibration and the mirror image calibration in the RF chip TX at the transmitting end are modified for multiple times, the local oscillator signal power and the mirror image signal power are minimum, and then the corresponding register values are stored.
in the step (6), the sequence of the local oscillator mirror calibration performed by the MCU is as follows: i path local oscillator coarse calibration, I path local oscillator fine calibration, Q path local oscillator coarse calibration and Q path local oscillator fine calibration are carried out, and then I path local oscillator fine calibration and Q path local oscillator fine calibration are carried out; performing I path mirror image coarse calibration, I path mirror image fine calibration, Q path mirror image coarse calibration and Q path mirror image fine calibration, and then performing I path mirror image fine calibration and Q path mirror image fine calibration;
Rewriting the calibration register at a certain interval on the basis of the register value after the TX self-calibration of the RF chip, and then finding out the value of the register corresponding to the minimum power value as a coarse tuning value;
And on the basis of the coarse tuning value, the value of the register is adjusted left and right, and the value corresponding to the minimum power is found to be the fine tuning value.
The radio frequency signal output by the transmitting end RF chip TX is within the output bandwidth of the RF chip and is not at the local oscillation position.
Compared with a manual calibration method, the method can be automatically completed, saves the labor cost, has high accuracy, and can be simultaneously performed in large batch. The instruments required by manual calibration comprise a signal source and a frequency spectrometer, the instruments are expensive and cannot be purchased in large quantities by companies, and the instruments are not required to be used for automatic calibration; only one device is calibrated by manual calibration at a time, and a person is required to stare at the spectrometer for frequent operation, so that multiple devices can be calibrated simultaneously by automatic calibration at a time, and the operation is simple.
Drawings
Fig. 1 is a schematic diagram of the system structure of the present invention, signals are transmitted according to the schematic diagram, and single-tone signals sent by the FPGA are returned to the FPGA after passing through a radio frequency link.
Fig. 2 is a schematic diagram of a module structure for completing the calibration function inside the FPGA.
fig. 3 is a calibration flow chart of the method of the present invention.
Detailed Description
The present invention will be described in further detail below with reference to the accompanying drawings, but the embodiments of the present invention are not limited thereto.
The invention relates to an automatic calibration method of local oscillator mirror images, which comprises the following steps:
(7) after the equipment is normally powered on, entering a local oscillator and mirror image calibration mode through the MCU;
(8) A software (MCU) configures a receiving end RF chip (RX) to enable the receiving end RF chip (RX) and the sending end RF chip (TX) to be on the same frequency band and can normally receive a returned radio frequency signal; otherwise, if the received signals are not in the same frequency band, the received signals are filtered by a filter in an RF chip (RX) of the receiving end;
(9) The software (MCU) controls the radio frequency link switch to make the transmitted radio frequency signal enter the receiving link and return to the RF chip (RX) after passing through the radio frequency link, so that the whole signal transmission and reception form a loop;
(10) A software (MCU) controls a DDS (direct digital frequency synthesis) module of the FPGA to send a single-tone signal with fixed frequency, the FPGA switches a corresponding switch to enable the TX to send the single-tone signal, and the frequency of the required single-tone signal can be changed at any time according to the design requirement by adopting the DDS module;
(11) the FPGA carries out frequency conversion, narrow-band filtering and power statistics on the received RX signal to respectively obtain calibration signal power, local oscillator signal power and mirror image signal power; the FPGA receives baseband signals, frequency conversion is carried out by adopting a complex multiplier, narrow-band filter design is carried out by adopting CIC (integrated comb filter), and the maximum half-slot power in a wireless frame is adopted for power statistics;
(12) Software (MCU) carries out local oscillator mirror calibration through a calibration algorithm, the calibration algorithm can carry out coarse calibration and fine calibration, the coarse calibration and the fine calibration are carried out repeatedly, the local oscillator calibration and mirror calibration register values in the RF chip of the transmitting end are modified for multiple times, the local oscillator signal power and the mirror signal power are enabled to be minimum, and then the corresponding register values are stored.
Fig. 1 shows a calibration signal flow process, in which a calibration signal (single tone signal) sent by the FPGA passes through the RF chip (TX) to the antenna port, and is also fed back to the RF chip (RX) and then returned to the FPGA. The feedback back into the RF chip (RX) signal (hereinafter referred to as feedback signal) includes a calibration signal (main signal), a local oscillator signal, and an image signal. Whether the feedback signal enters the RF chip (RX) or not is controlled by MCU software, the RF chip (RX) is allowed to enter in the local oscillator image calibration mode, and the RF chip (RX) is not allowed to enter in the normal mode. The flow direction design of signals in fig. 1 is reduced to a hardware circuit design.
fig. 2 is a schematic diagram of modules inside the FPGA, where the DDS module may be implemented by an FPGA IP Core (intelligent performance Core), the frequency conversion module is implemented by an IP Core of a complex multiplier, the narrowband filtering module is implemented by a CIC (integrated comb filter) filter, and the power statistics module is implemented by an averaging method after accumulation and summation. The design of each module in fig. 2 is reduced to the code design of the FPGA.
Fig. 3 is a calibration flow chart of the present invention, in which the calibration start MCU allows the RF chip (TX) to perform self calibration, after the self calibration is completed, the RF chip (RX) is configured, then the RX receive link switch is turned on, the DDS module sends a single tone signal, the MUC writes a register of the RF chip (TX) to calibrate the local oscillator signal and the image signal, and finally, the register value after the calibration is completed is stored. The register method of MUC write RF chip (TX) is described in the calibration algorithm that follows.
in the above local oscillator image automatic calibration method, since the single tone signal sent by the FPGA needs to return to the FPGA again after passing through the peripheral integrated broadband RF transceiver chip, the hardware needs to be designed for compatibility. Under normal conditions, the signal of the sending link directly reaches the radio frequency antenna port after passing through the radio frequency link; in order to perform local oscillator mirror calibration automatic calibration, the radio frequency signal on the transmission link is led back to the receiving link again, and meanwhile, it is required to ensure that normal use of the receiving link is not affected.
In the method for automatically calibrating the local oscillator image, because the sending and receiving links are in different frequency bands under general conditions, when the local oscillator signals and the image signals of the RF transceiver chip at the sending end are calibrated, the configuration of the chip (TX) at the sending end is kept unchanged, and the configuration of the chip (RX) at the receiving end is modified according to the frequency bands of the received signals, so that the signals which can be fed back can be normally received.
in the method for automatically calibrating the local oscillator mirror image, the bandwidth is fixed after the RF chip (TX) is configured, and simultaneously, in order to reflect the actual use condition most truly, a transmitted single tone signal is required to be on a used frequency band; the signal can be introduced into a frequency spectrograph at an antenna port of the TX, and the size change of a local oscillator signal and a mirror image signal in the calibration process is checked by using the instrument.
in the method for automatically calibrating the local oscillator image, because the transmitted local oscillator signal is a single-tone signal, and the received local oscillator signal and the received image signal are also single-tone signals, a CIC (integrated comb filter) filter can be adopted to design a narrow-band filter, and the CIC filter can save multiplier resources of an FPGA (field programmable gate array).
In the method for automatically calibrating the local oscillator mirror image, the calibration algorithm is adopted as follows: the RF chip (TX) is powered up to perform chip self-calibration and then MCU calibration. Rewriting the calibration register at certain intervals on the basis of the register value after the RF chip is subjected to self calibration, and then finding out the value of the register corresponding to the minimum power value, namely the coarse tuning value; and on the basis of the coarse tuning value, the value of the register is adjusted left and right, and the value corresponding to the minimum power is found out to be the fine tuning value. The MCU calibration sequence is as follows: i path local oscillator coarse calibration, I path local oscillator fine calibration, Q path local oscillator coarse calibration and Q path local oscillator fine calibration are carried out, and then I path local oscillator fine calibration and Q path local oscillator fine calibration are carried out; the method comprises the following steps of I-path mirror image coarse calibration, I-path mirror image fine calibration, Q-path mirror image coarse calibration, Q-path mirror image fine calibration, I-path mirror image fine calibration and Q-path mirror image fine calibration.
in the above local oscillator mirror image automatic calibration method, because the temperature of the device is fixed in a certain range under the normal use condition, only one local oscillator mirror image automatic calibration needs to be performed when the device leaves the factory, the calibrated TX chip configuration value is stored in Flash (Flash memory), and the TX chip configuration value can be directly configured during normal use; the calibration can be repeated when low or high temperature conditions are encountered.
the above examples are illustrative of the preferred embodiments of the present invention, but the present invention is not limited to the above examples, and any other changes, modifications, substitutions, combinations, and simplifications which do not depart from the spirit and principle of the present invention should be construed as equivalents thereof, and they are intended to be included in the scope of the present invention.