CN112382323A - Static random access memory, processor and data reading method - Google Patents

Static random access memory, processor and data reading method Download PDF

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Publication number
CN112382323A
CN112382323A CN202011259379.XA CN202011259379A CN112382323A CN 112382323 A CN112382323 A CN 112382323A CN 202011259379 A CN202011259379 A CN 202011259379A CN 112382323 A CN112382323 A CN 112382323A
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operator
read
circuit
row
level signal
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CN112382323B (en
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杨昌楷
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Haiguang Information Technology Co Ltd
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Haiguang Information Technology Co Ltd
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

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  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)

Abstract

The application provides a static random access memory, a processor and a data reading method, comprising a memory cell array, a reading detection circuit and a reading control circuit; the memory cell array comprises m columns and n rows of memory cells, m switch groups and m BL charging circuits; the read detection circuit is to: when the static random access memory is detected to continuously read data from the memory cells in different columns of the same row, outputting a high-level signal to a read control circuit; the read control circuit is used for maintaining the WL driving signal corresponding to the row where the memory cell is located to be low and maintaining the m BL charging circuits to be in a charging stop state when receiving the high level signal of the read detection circuit, so as to keep the voltage difference corresponding to the m memory cells which are located in the same row and different columns unchanged. According to the embodiment of the application, after the voltage difference is pulled out once, the voltage difference of a plurality of storage units in the same row and different columns can be read for a plurality of times, and the cycle process of pulling out the voltage difference and charging does not need to be executed frequently.

Description

Static random access memory, processor and data reading method
Technical Field
The present application relates to the field of computers, and in particular, to a static random access memory, a processor, and a data reading method.
Background
In the prior art, when the sram reads data from a target memory cell (bit cell) of the memory cell array, the target memory cell is set to 1 in a Word Line (WL) corresponding to a row to which the memory cell array belongs, and set to 0 in a WL corresponding to another row of the memory cell array. And WL 1, pulling out voltage difference between BL lines and BLB lines respectively connected with all memory cells in the row of the target memory cell, and WL 0 after the BL lines and BLB lines corresponding to all the memory cells in the same row are pulled out voltage difference.
The selector turns on the switch corresponding to the column to which the target memory cell belongs, so that the sense amplifier amplifies the voltage difference between the BL line and the BLB line corresponding to the target memory cell, and after the sense amplifier amplifies the voltage difference, the static random access memory controls the charging circuit to charge the BL line and the BLB line corresponding to each column of memory cells.
When voltage differences are continuously read from the memory cells in different rows and columns of the memory cell array, the WL will pull out the voltage differences between the BL and BLB corresponding to all the memory cells in the row, and the charging circuit charges the BL lines and BLB lines corresponding to the memory cells in each column, thereby wasting electric energy.
Disclosure of Invention
An object of the embodiments of the present invention is to provide a static random access memory, a processor and a data reading method, so as to solve the problem of power waste in the prior art.
In a first aspect, an embodiment of the present application provides a static random access memory, including a memory cell array, a read detection circuit, and a read control circuit; the memory cell array comprises m columns and n rows of memory cells, m switch groups and m BL charging circuits, wherein the m columns of memory cells correspond to the m switch groups one by one, and each column of memory cells is controlled by the corresponding switch group; the m BL charging circuits are in one-to-one correspondence with the m rows of storage units, and are used for charging BL lines and BLB lines connected with the storage units in the corresponding rows according to the control of the read control circuit; the read probe circuit is to: when the static random access memory is detected to continuously read data from the memory cells in different columns of the same row, outputting a high-level signal representing continuous reading confirmation to the reading control circuit; the read control circuit is used for maintaining the WL driving signal corresponding to the row where the memory cell is located to be low and maintaining the m BL charging circuits to be in a charging stop state when receiving the high level signal output by the read detection circuit, so as to keep the voltage difference between the BL line and the BLB line corresponding to the m memory cells which are located in the same row and different columns unchanged.
In the above-described embodiment, the read detection circuit outputs a high level signal to the read control circuit when detecting that the sram continuously reads data from memory cells located in different columns in the same row. When receiving a high-level signal transmitted by the reading detection circuit, the reading control circuit maintains the WL driving signal of the row where the storage unit is located to be low, so that after a voltage difference is pulled out between a BL line and a BLB line which are connected with the storage unit, the voltage difference between the BL line and the BLB line is maintained; the m BL charging circuits are maintained in a charging stop state, the charging of the BL lines and the BLB lines can be avoided, and therefore after the voltage difference is pulled out once, the voltage difference of a plurality of storage units in the same row and different columns can be read for a plurality of times, and the cycle process of pulling out the voltage difference and charging does not need to be executed frequently.
In one possible design, the read detection circuit includes a column detection sub-circuit, a row detection sub-circuit, a continuous read detection sub-circuit, and a first and operator, and the column detection sub-circuit, the row detection sub-circuit, and the continuous read detection sub-circuit are all connected to the first and operator; the column detection sub-circuit is used for comparing a column address received in a current clock cycle with a column address received in a previous clock cycle, and outputting a high-level signal to the first AND operator when the column address of the current clock cycle is different from the column address of the previous clock cycle; the row detection sub-circuit is used for comparing a row address received in a current clock cycle with a row address received in a previous clock cycle, and outputting a high-level signal to the first AND operator when the row address of the current clock cycle is the same as the row address of the previous clock cycle; the continuous reading detection sub-circuit is used for judging whether a current clock period and a previous clock period both receive reading signals or not, and outputting high-level signals to the first AND operator when the current clock period and the previous clock period both receive the reading signals; the first AND operator is used for outputting a high-level signal to the reading control circuit when receiving high-level signals representing different column addresses, high-level signals representing the same row address and high-level signals representing reading signals received in two continuous clock cycles.
In the above-described embodiments, the read detection circuit includes a column detection sub-circuit, a row detection sub-circuit, and a continuous read detection sub-circuit. The column detection sub-circuit is used for detecting whether column addresses of two continuous clock cycles are the same or not, and if the column addresses are the same, outputting a low level; when the column addresses are different, a high level is output. The row detection sub-circuit is used for detecting whether the row addresses of two continuous clock cycles are the same or not, and if the row addresses are different, outputting a low level; the row address is the same, and a high level is output. The continuous reading detection sub-circuit is used for judging whether reading signals are received in two continuous clock cycles or not, and if so, outputting a high level; otherwise, outputting low level. The first and operator performs an and operation on the output results of the three sub-circuits, and the obtained operation result is the output result of the read detection circuit. The read detection circuit detects whether the column address, the row address and the continuous reading are carried out through the three sub-circuits respectively, the detection processes of the three sub-circuits are mutually independent, and the possibility of detection errors is reduced.
In one possible design, the column detection subcircuit includes a first flip-flop and an exclusive or operator; the input end of the first trigger is used for receiving column address data, and the output end of the first trigger is connected with the first input end of the XOR operator; the second input end of the exclusive-or operator is used for receiving the column address data, and the output end of the exclusive-or operator is connected with the first and operator.
In the above embodiment, the input terminal of the first flip-flop receives column address data, and may delay the column address data by one clock cycle, the first input terminal of the xor operator receives the column address data delayed by one clock cycle, the second input terminal of the xor operator receives the column address data not delayed by one clock cycle, the xor operator is configured to perform an xor operation on the two column addresses, and if the operation result is 1, it indicates that the two column addresses are different; if the operation result is 0, it indicates that the two column addresses are the same.
In one possible design, the row detection subcircuit includes a second flip-flop and an exclusive nor operator; the input end of the second trigger is used for receiving row address data, and the output end of the second trigger is connected with the first input end of the exclusive-nor operator; the second input end of the exclusive OR operator is used for receiving the row address data, and the output end of the exclusive OR operator is connected with the first exclusive OR operator.
In the above embodiment, the input terminal of the second flip-flop receives the row address data and may delay the row address data by one clock cycle, and the first input terminal of the exclusive-nor operator receives the row address data delayed by one clock cycle. The second input end of the exclusive-nor operator receives row address data of a non-delayed clock cycle, the exclusive-nor operator is used for carrying out exclusive-nor operation on the two row addresses, and if the operation result is 1, the two row addresses are the same; if the operation result is 0, it indicates that the two row addresses are different.
In one possible design, the continuous read detection sub-circuit includes a third flip-flop and a second and operator; the input end of the third trigger is used for receiving the reading signal, and the output end of the third trigger is connected with the first input end of the second AND operator; the second input end of the second and operator is used for receiving the reading signal, and the output end of the second and operator is connected with the first and operator.
In the above embodiment, the input terminal of the third flip-flop receives the read signal and may delay the read signal by one clock cycle, the first input terminal of the second and operator receives the read signal delayed by one clock cycle, and the second input terminal of the second and operator receives the read signal not delayed by one clock cycle. The second AND operator is used for carrying out AND operation on two continuous read signals. If two continuous reading signals are both high level, the operation result is 1; if at least one of the two consecutive read signals is not at a high level, the operation result is 0.
In one possible design, the read detection circuit further includes a latch, and an input terminal of the latch is connected to an output terminal of the first and operator.
In the above-described embodiment, the latch may lock the output result of the first and operator when the clock signal is at a high level, and may change the output result of the first and operator when the clock signal is at a low level, thereby improving the operation stability of the entire circuit.
In one possible design, the read control circuit includes an inverter, a third and operator, and an or operator; the inverter is used for inverting the level signal output by the reading detection circuit and transmitting the inverted level signal to the third AND operator; the third and operator is configured to perform and operation on the level signal output by the inverter and the level signal of the WL line to obtain a first processing result, where the first processing result is the WL driving signal; the or arithmetic unit is configured to perform or arithmetic on the level signal output by the read detection circuit and the charging control signal to obtain a second processing result, where the second processing result is a control signal for switching m BL charging circuits to charge or stop charging.
In the above embodiment, the level signal output by the read detection circuit may be inverted and then phase-anded with the WL line, and the level signal output by the read detection circuit is phase-anded with the charge control signal, so that the level signal output by the read detection circuit and the charge control signal are used to influence the level signal of the WL line, and the level signal of the WL line and the charge control signal are not changed when the level signal output by the read detection circuit is high, regardless of the level signal of the WL line and the charge control signal.
In one possible design, the mobile terminal further includes a selector, the selector is connected to the m switch groups, and the selector is configured to select one switch group from the m switch groups according to a received address and turn on the selected switch group.
In the above-described embodiment, the switch group selected by the selector is turned on, so that the voltage difference between the BL line and the BLB line drawn by the memory cell corresponding to the turned-on switch group can be transmitted to the sense amplifier of the lower stage.
In a second aspect, an embodiment of the present application provides a processor, including the static random access memory according to the first aspect and any possible design of the first aspect.
In the above embodiment, the processor including the sram can perform multiple readings of the voltage differences of the memory cells in different columns and rows after pulling out the voltage difference once, and the cycle of pulling out the voltage difference and charging does not need to be performed frequently, thereby saving electric energy.
In a third aspect, the present application provides a data reading method, including: when a read detection circuit in the static random access memory detects that the static random access memory continuously reads data from memory cells which are positioned in the same row and different columns, a high-level signal representing continuous read confirmation is transmitted to a read control circuit in the static random access memory; after receiving a high-level signal output by the reading detection circuit, the reading control circuit maintains that the WL driving signal corresponding to the row where the storage units in the same row and different columns are located is low, and maintains that the BL charging circuits corresponding to the storage units in the same row and different columns are in a charging stop state, so as to keep the voltage difference between the BL lines and the BLB lines corresponding to the storage units in the same row and different columns unchanged, wherein the number of the BL charging circuits is the same as the number of the columns of the storage units.
In the above-described embodiment, the read detection circuit outputs a high level signal to the read control circuit when detecting that the sram continuously reads data from memory cells located in different columns in the same row. When receiving a high-level signal transmitted by the reading detection circuit, the reading control circuit maintains the WL driving signal of the row where the storage unit is located to be low, so that after a voltage difference is pulled out between a BL line and a BLB line which are connected with the storage unit, the voltage difference between the BL line and the BLB line is maintained; the m BL charging circuits are maintained in a charging stop state, the charging of the BL lines and the BLB lines can be avoided, and therefore after the voltage difference is pulled out once, the voltage difference of a plurality of storage units in the same row and different columns can be read for a plurality of times, and the cycle process of pulling out the voltage difference and charging does not need to be executed frequently.
In one possible design, the read detection circuit includes a column detection sub-circuit, a row detection sub-circuit, a continuous read detection sub-circuit, and a first and operator, and the column detection sub-circuit, the row detection sub-circuit, and the continuous read detection sub-circuit are all connected to the first and operator; the read probe circuit detects that: when the static random access memory continuously reads data from the memory cells which are positioned in the same row and different columns, the static random access memory outputs a high level signal representing continuous read confirmation, and the method comprises the following steps: and the first AND operator outputs a high-level signal when receiving high-level signals which are sent by the column detection subcircuit and are different in representing column addresses, high-level signals which are sent by the row detection subcircuit and are same in representing row addresses, and high-level signals which are sent by the continuous reading detection subcircuit and are used for representing reading signals received in two continuous clock cycles.
In the above embodiment, the first and operator performs an and operation on the output results of the three sub-circuits, and the obtained operation result is the output result of the read detection circuit. The read detection circuit detects whether the column address, the row address and the continuous reading are carried out through the three sub-circuits respectively, the detection processes of the three sub-circuits are mutually independent, and the possibility of detection errors is reduced.
In one possible design, the column detection subcircuit includes a first flip-flop and an exclusive or operator; the input end of the first trigger is used for receiving column address data, and the output end of the first trigger is connected with the first input end of the XOR operator; a second input of the exclusive or operator is configured to receive the column address data; before the first and operator outputs a high level signal when receiving a high level signal sent by the column detection sub-circuit and indicating that a column address is different, a high level signal sent by the row detection sub-circuit and indicating that a row address is the same, and a high level signal sent by the continuous read detection sub-circuit and indicating that a read signal is received in two consecutive clock cycles, the method further includes: the column detection sub-circuit compares a column address of a current clock cycle with a column address of a previous clock cycle, and outputs a high level signal to the first and operator when the column address of the current clock cycle is different from the column address of the previous clock cycle.
In the above embodiment, the input terminal of the first flip-flop receives column address data, and may delay the column address data by one clock cycle, the first input terminal of the xor operator receives the column address data delayed by one clock cycle, the second input terminal of the xor operator receives the column address data not delayed by one clock cycle, the xor operator is configured to perform an xor operation on the two column addresses, and if the operation result is 1, it indicates that the two column addresses are different; if the operation result is 0, it indicates that the two column addresses are the same.
In one possible design, the row detection subcircuit includes a second flip-flop and an exclusive nor operator; the input end of the second trigger is used for receiving row address data, and the output end of the second trigger is connected with the first input end of the exclusive-nor operator; a second input terminal of the exclusive-nor operator is used for receiving the row address data; before the first and operator outputs a high level signal when receiving a high level signal sent by the column detection sub-circuit and indicating that a column address is different, a high level signal sent by the row detection sub-circuit and indicating that a row address is the same, and a high level signal sent by the continuous read detection sub-circuit and indicating that a read signal is received in two consecutive clock cycles, the method further includes: the row detection sub-circuit compares a row address of a current clock cycle with a row address of a previous clock cycle, and outputs a high level signal to the first and operator when the row address of the current clock cycle is the same as the row address of the previous clock cycle.
In the above embodiment, the input terminal of the second flip-flop receives the row address data and may delay the row address data by one clock cycle, and the first input terminal of the exclusive-nor operator receives the row address data delayed by one clock cycle. The second input end of the exclusive-nor operator receives row address data of a non-delayed clock cycle, the exclusive-nor operator is used for carrying out exclusive-nor operation on the two row addresses, and if the operation result is 1, the two row addresses are the same; if the operation result is 0, it indicates that the two row addresses are different.
In one possible design, the continuous read detection sub-circuit includes a third flip-flop and a second and operator; the input end of the third trigger is used for receiving the reading signal, and the output end of the third trigger is connected with the first input end of the second AND operator; a second input terminal of the second and operator is configured to receive the read signal; before the first and operator outputs a high level signal when receiving a high level signal sent by the column detection sub-circuit and indicating that a column address is different, a high level signal sent by the row detection sub-circuit and indicating that a row address is the same, and a high level signal sent by the continuous read detection sub-circuit and indicating that a read signal is received in two consecutive clock cycles, the method further includes: the continuous reading detection sub-circuit judges whether the current clock period and the previous clock period both receive reading signals, and outputs high-level signals to the first AND operator when the current clock period and the previous clock period both receive the reading signals.
In the above embodiment, the input terminal of the third flip-flop receives the read signal and may delay the read signal by one clock cycle, the first input terminal of the second and operator receives the read signal delayed by one clock cycle, and the second input terminal of the second and operator receives the read signal not delayed by one clock cycle. The second AND operator is used for carrying out AND operation on two continuous read signals. If two continuous reading signals are both high level, the operation result is 1; if at least one of the two consecutive read signals is not at a high level, the operation result is 0.
In one possible design, the read control circuit includes an inverter, a third and operator, and an or operator; when the read control circuit receives a high level signal output by the read detection circuit, the read control circuit maintains the WL driving signal corresponding to the row where the storage unit is located to be low, and maintains m BL charging circuits to be in a charging stop state, including: the inverter inverts the level signal output by the reading detection circuit and transmits the inverted level signal to the third AND operator; the third and operator performs and operation on the level signal output by the inverter and the level signal of the WL line to obtain a first processing result, wherein the first processing result is the WL driving signal; and the OR operator performs OR operation on the level signal output by the read detection circuit and the charging control signal to obtain a second processing result, wherein the second processing result is a control signal for switching m BL charging circuits to charge or stopping charging.
In the above embodiment, the level signal output by the read detection circuit may be inverted and then phase-anded with the WL line, and the level signal output by the read detection circuit is phase-anded with the charge control signal, so that the level signal output by the read detection circuit and the charge control signal are used to influence the level signal of the WL line, and the level signal of the WL line and the charge control signal are not changed when the level signal output by the read detection circuit is high, regardless of the level signal of the WL line and the charge control signal.
In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments of the present application will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and that those skilled in the art can also obtain other related drawings based on the drawings without inventive efforts.
FIG. 1 is a schematic block diagram of a prior art SRAM;
FIG. 2 is a schematic structural block diagram of a static random access memory provided in an embodiment of the present application;
FIG. 3 shows a schematic block diagram of the read probe circuit of FIG. 2;
FIG. 4 is a block diagram showing a schematic configuration of the read control circuit in FIG. 2;
FIG. 5 is a diagram illustrating a partial operation waveform of a static random access memory provided by an embodiment of the present application;
FIG. 6 is a flow chart illustrating a data reading method according to an embodiment of the present disclosure;
fig. 7 shows a flowchart illustrating a specific step of step S120 in fig. 6.
Detailed Description
Referring to fig. 1, fig. 1 is a schematic diagram illustrating a memory cell array composed of memory cells 110(bit cells) in a comparative embodiment, where the memory cell array illustrated in fig. 1 has n rows and 4 columns, where n is a positive integer. In the memory cell array, memory cells 110 in the same row share the same Word Line (WL), and if memory cells 110 in different rows correspond to respective WLs, n rows of memory cells 110 correspond to n WLs. The memory cells 110 in the same column are connected to the same BL line and BLB line, a BL charging circuit 120 is connected between the BL line and the BLB line, and the memory cells 110 in 4 columns are in one-to-one correspondence with the 4 BL charging circuits 120.
The memory cells 110 in different columns are associated with respective switches, which can be selected by the selector 200 according to the address signal, the switches selected by the selector 200 being closed, and the switches not selected by the selector 200 being open. Referring to FIG. 1, the 4 columns of memory cells 110 have four switches Y0, Y1, Y2 and Y3, which can be selected by two-bit addresses Addr [0] and Addr [1 ]. Addr [0], Addr [1] have four address combinations: 00. 01, 10, 11, the four address combinations may correspond to one switch of the four switches, and the correspondence between the address combinations and the switches should not be construed as limiting the present application. The four switches can be PMOS tubes.
One end of the switch, which is far from the BL charging circuit 120, is further connected with 4 data charging circuits 130, for details, referring to fig. 1, the 4 data charging circuits 130 are respectively connected between the DL and DLB corresponding to each other, and the 4 data charging circuits 130 are all connected with the controller, and can charge the DL and DLB corresponding to each other under the control of the DL _ Pre signal of the controller.
In some embodiments, the memory cell array may further include more than 4 columns, and may also include less than 4 columns, and the specific number of columns of the memory cells 110 of the memory cell array should not be construed as limiting the present application.
For convenience of description, the data reading process will be described by taking the example of reading data from the target memory cell 110 corresponding to the row and column 0 corresponding to WL [0 ]:
first, let WL [0] set to 1, WL [1], WL [2] … WL [ n-1] set to 0, then in the row corresponding to WL [0 ]:
the target memory cell corresponding to column 0 pulls out the voltage difference between BL0 and BLB 0;
the memory cell corresponding to column 1 will also pull a voltage difference between BL1 and BLB 1;
the memory cells corresponding to the 2 columns will also pull a voltage difference between BL2 and BLB 2;
the 3 columns of corresponding memory cells will also pull a voltage difference between BL3 and BLB 3.
After a voltage difference is pulled between BL and BLB corresponding to each column, WL [0] is set to 0.
The selector 200 selects Y0 to be on and Y1, Y2, and Y3 to be off. At this time, DL is BL0, and DLB is BLB 0.
The sense amplifier SA amplifies the voltage difference between DL and DLB to a logic level, and transmits the logic level to the Latch, which latches the logic level.
After the logic level is latched in Latch, Y0 is turned off. Then, BL _ Pre charges BL, BLB corresponding to each column, and DL _ Pre charges DL, DLB, so that the levels of BL, BLB, DL, DLB are all charged to the original level vdd.
If data is read from a certain memory cell 110 again next time, the above process is repeatedly performed.
In the process of reading data, if the voltage difference is read from the memory cells 110 corresponding to different columns in the same row, the WL will pull out the voltage difference between the BL and the BLB for multiple times, and the BL _ Pre charges the BL and BLB corresponding to each column, which results in waste of power.
The static random access memory provided by the embodiment of the application can realize that after a voltage difference is pulled out once, the voltage difference corresponding to a plurality of storage units 110 in the same row and different columns can be read for a plurality of times by influencing the WL driving signal and the m BL charging circuits 120, and the cycle process of pulling out the voltage difference and charging does not need to be frequently executed, so that the electric energy is saved, and the power consumption is reduced.
The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.
Referring to fig. 2, fig. 2 shows a static random access memory provided by an embodiment of the present application, and the static random access memory includes a memory cell array, a selector 200, a read detection circuit 300, and a read control circuit 400.
The memory cells 110 include m columns and n rows of memory cells 110, and for convenience of explanation, m is not set to 4, and only one of the n rows is shown in fig. 2.
The read probe circuit 300 is configured to detect: when the static random access memory continuously reads data from the memory cells 110 in the same row and different columns, a high level signal representing continuous read confirmation is output.
The read control circuit 400 is configured to maintain the WL driving signal corresponding to the row of the memory cells 110 low and maintain the m BL charging circuits 120 in the charging-stopped state when receiving the high level signal output by the read detection circuit 300.
The read detection circuit 300 outputs a high level signal to the read control circuit 400 when detecting that the sram continuously reads data from the memory cells 110 located in different columns in the same row. The read control circuit 400 maintains the WL driving signal of the row in which the memory cell 110 is located low when receiving the high level signal transmitted from the read detection circuit 300, thereby maintaining the voltage difference between the BL line and the BLB line after pulling out the voltage difference between the BL line and the BLB line connected to the memory cell 110; the m BL charging circuits 120 are maintained in the stop state, and the BL lines and the BLB lines can be prevented from being charged. The static random access memory provided by the embodiment of the application can read the voltage difference of the plurality of memory cells 110 in the same row and different columns for a plurality of times after the voltage difference is pulled out once, and the cycle process of pulling out the voltage difference and charging does not need to be executed frequently.
The read probe circuit 300 includes a column probe sub-circuit 310, a row probe sub-circuit 320, a continuous read probe sub-circuit 330, a first AND operator I4, and a latch I5. Referring to fig. 3, the output terminal of the column probe sub-circuit 310, the output terminal of the row probe sub-circuit 320 and the output terminal of the continuous read probe sub-circuit 330 are respectively connected to the input terminal of the first and operator I4, and the output terminal of the first and operator I4 is connected to the input terminal of the latch I5.
The latch I5 can lock the output result of the first AND operator I4 when the clock signal is high; when the clock signal is at a low level, the output result is changed according to the input of the first and operator I4, thereby improving the operation stability of the whole circuit.
The column probe sub-circuit 310 includes a first flip-flop I6 and an exclusive or operator I7. The input end of the first flip-flop I6 is used for receiving column address data, and the output end of the first flip-flop I6 is connected with the first input end of the XOR operator I7; a second input of the xor operator I7 is for receiving the column address data.
The input end of the first flip-flop I6 receives column address data and can delay the column address data by one clock cycle, the first input end of the XOR operator I7 receives the column address data delayed by one clock cycle, the second input end of the XOR operator I7 receives the column address data not delayed by one clock cycle, the XOR operator I7 is used for carrying out XOR operation on the two column addresses, and if the operation result is 1, the two column addresses are different; if the operation result is 0, it indicates that the two column addresses are the same. The column detection sub-circuit 310 compares the column address of the current clock cycle with the column address of the previous clock cycle, and outputs a high signal to the first and operator I4 when the column address of the current clock cycle is different from the column address of the previous clock cycle.
The row detection sub-circuit 320 includes a second flip-flop I2 and an exclusive nor operator I3. The input end of the second flip-flop I2 is used for receiving row address data, and the output end of the second flip-flop I2 is connected with the first input end of the exclusive-nor operator I3; a second input of the exclusive or operator I3 is for receiving the row address data.
The input terminal of the second flip-flop I2 receives the row address data and may delay the row address data by one clock cycle, and the first input terminal of the exclusive-nor I3 receives the row address data delayed by one clock cycle. The second input terminal of the exclusive nor operator I3 receives the row address data without delaying the clock cycle, the exclusive nor operator I3 is configured to perform an exclusive nor operation on the two row addresses, and if the operation result is 1, it indicates that the two row addresses are the same; if the operation result is 0, it indicates that the two row addresses are different. The row detection sub-circuit 320 compares the row address of the current clock cycle with the row address of the previous clock cycle, and outputs a high signal to the first and operator I4 when the row address of the current clock cycle is the same as the row address of the previous clock cycle.
Alternatively, in the above embodiment, the column address data may be a lower address, and the row address data may be an upper address, and since the number of columns is 4 in the above embodiment, the column address data may be specifically represented by a lower 2-bit address Addr [1:0], and Addr [1:0] has four cases of 00, 01, 10, and 11, and may just correspond to 4 columns. Accordingly, the row address data may be represented by the upper 6-bit address Addr [7:2 ].
It should be understood that if the number of columns of the memory cell array of the sram exceeds 4, the column address needs to be represented by a lower address of more bits. For example, in another embodiment, where the number of columns in the memory cell array is 6, the column address can be represented by the lower 3-bit address Addr [2:0 ]. Addr [2:0] has eight cases of 000, 001, 010, 011, 100, 101, 110, 111, and 6 cases among them can be selected to correspond to the above-mentioned 6 columns, respectively.
The continuous read probe sub-circuit 330 includes a third flip-flop I0 and a second and operator I1; the input end of the third flip-flop I0 is used for receiving the read signal RD, and the output end of the third flip-flop I0 is connected with the first input end of the second AND operator I1; a second input of the second and operator I1 is for receiving the read signal RD. Wherein RD is 1, which indicates that data is to be read; RD is 0, indicating no data is read.
The input terminal of the third flip-flop I0 receives the read signal RD and may delay the read signal RD by one clock cycle. A first input of the second AND operator I1 receives the read signal RD delayed by one clock cycle, and a second input of the second AND operator I1 receives the read signal RD not delayed by one clock cycle. The second and operator I1 is used for performing an and operation on two consecutive read signals RD. If two continuous reading signals RD are both high level, the operation result is 1; if at least one of the two consecutive read signals RD is not at a high level, the operation result is 0.
The continuous read detecting sub-circuit 330 is configured to determine whether the read signal RD is received in both the current clock cycle and the previous clock cycle, and output a high level signal to the first and operator I4 when the read signal RD is received in both the current clock cycle and the previous clock cycle.
The first and operator I4 is configured to output a high level signal Burst _ en when receiving a high level signal indicating that the column address is different, a high level signal indicating that the row address is the same, and a high level signal indicating that the read signal RD is received for two consecutive clock cycles.
The read control circuit 400 includes an inverter I10, a third and operator I8 and an or operator I9. referring to fig. 4, the inverter I10 is used for inverting the level signal Burst _ en outputted from the read probe circuit 300 and transmitting the inverted signal to the third and operator I8.
The third and operator I8 is configured to and the level signal output from the inverter I10 and the level signal WL of the WL line to obtain a first processing result, where the first processing result is the WL driving signal WL _ 1.
The or operator I9 is configured to perform an or operation on the level signal Burst _ en output by the read detection circuit 300 and the charging control signal BL _ Pre to obtain a second processing result, where the second processing result is the control signal BL _ Pre _1 for switching the m BL charging circuits 120 to charge or stop charging.
After the level signal output by the read detection circuit 300 is inverted, the level signal is subjected to phase-inversion with the WL line, and the level signal output by the read detection circuit 300 is subjected to phase-inversion with the charge control signal, so that the level signal and the charge control signal of the WL line are influenced by the level signal output by the read detection circuit 300, and when the level signal output by the read detection circuit 300 is high, the level signal and the charge control signal of the WL line cannot cause the change of the WL driving signal WL _1 and the control signal BL _ Pre _1 no matter the level signal and the charge control signal are high or low.
Referring to fig. 5, fig. 5 is a schematic diagram illustrating a partial operation waveform of a static random access memory according to an embodiment of the present application. Addr [7:0] has a total of 8-bit addresses, where the upper 6 bits of Addr [7:2] are the row address and the lower 2 bits of Addr [1:0] are the column address.
Among the 5 addresses shown in fig. 5: 11110000, 11110001, 11110010, 11110011, 11100011, and they were found to:
11110001 is the same as the row address of 11110000 (i.e., 111100), and the column address (i.e., 01 and 00) is different;
11110010 is the same as the row address of 11110001 (i.e., 111100), and the column addresses (i.e., 10 and 01) are different;
11110011 and 11110010 have the same row address (i.e., 111100) and different column addresses (i.e., 11 and 10);
the row addresses of 11100011 and 11110011 (i.e., 111000 and 111100) are different, and the column addresses (i.e., 11) are the same.
Therefore, referring to fig. 5 in detail, in the case where the same row address, the different column addresses, and the read signal RD is 1 are satisfied, the output signal Burst _ en of the read detection circuit 300 is 1. In the case where the row addresses are different, or the column addresses are the same, or the read signal RD is 0, the output signal Burst _ en of the read detection circuit 300 is 0.
Referring to fig. 5, in a time period corresponding to Burst _ en being 1, Burst _ en adjusts both low levels of the charging control signal BL _ Pre to high levels, and the adjusted waveform is the control signal BL _ Pre _ 1. The control signal BL _ Pre _1 is high, which may cause the BL charging circuit 120 to be in a stop charging state.
In a time period corresponding to Burst _ en being 1, Burst _ en adjusts both high levels of the level signals WL of the WL lines to low levels, and the adjusted waveform is the WL drive signal WL _ 1. The WL driving signal WL _1 is low, and can maintain the voltage difference between the BL line and the BLB line corresponding to each column of the memory cells 110, as shown in the following four waveforms in fig. 5: BL0/BLB0, BLB1/BL1, BL2/BLB2 and BLB3/BL 3. In a time period corresponding to Burst _ en being 1, the four waveforms are all pulled out of the voltage difference and held.
Waveforms corresponding to four switches Y0, Y1, Y2 and Y3 shown in fig. 5 show specific correspondence between column addresses and switches, the four switches Y0, Y1, Y2 and Y3 are all PMOS transistors, the switch corresponding to the high level is turned on, and the switch corresponding to the low level is turned off. Thus, column address 00 corresponds to switch Y0 being conductive; column address 01 corresponds to switch Y1 being on; column address 10 corresponds to switch Y2 being on; column address 11 corresponds to switch Y3 being conductive. The last high level of the waveform corresponding to the switch Y3 in fig. 5 corresponds to the turning on of the memory cell 110 in the column where the switch Y3 of a different row (i.e., the row with the row address of 111000) is located.
The embodiment of the application also provides a processor which can comprise the static random access memory.
Referring to fig. 6, fig. 6 is a schematic flow chart of a data reading method according to an embodiment of the present application, where the method is executed by the sram, and specifically includes the following steps S110 to S120:
step S110, when the read detection circuit in the static random access memory detects that the static random access memory continuously reads data from the memory cells located in the same row and different columns, the read detection circuit transmits a high level signal representing continuous read confirmation to the read control circuit in the static random access memory.
Step S120, after receiving the high level signal output by the read detection circuit, the read control circuit maintains the WL driving signal corresponding to the row where the memory cells in the same row and different columns are located is low, and maintains the BL charging circuits corresponding to the memory cells in the same row and different columns in a charging stop state, so as to keep the voltage difference between the BL lines and the BLB lines corresponding to the memory cells in the same row and different columns unchanged, where the number of the BL charging circuits is the same as the number of the columns of the memory cells.
Maintaining the WL driving signal of the row in which the memory cell 110 is located low, thereby maintaining a voltage difference between the BL line and the BLB line after pulling out the voltage difference between the BL line and the BLB line connected to the memory cell 110; the m BL charging circuits 120 are maintained in the charging stop state, and the BL lines and the BLB lines can be prevented from being charged, so that after a voltage difference is pulled out once, the voltage differences of the plurality of memory cells 110 in the same row and different columns can be read for a plurality of times, and the cycle of pulling out the voltage differences and charging does not need to be frequently executed.
In a specific embodiment, step S110 specifically includes:
step A: the first and operator I4 outputs a high level signal when receiving a high level signal sent by the column detection sub-circuit 310 and indicating that the column address is different, a high level signal sent by the row detection sub-circuit 320 and indicating that the row address is the same, and a high level signal sent by the continuous read detection sub-circuit 330 and indicating that the read signal is received in two consecutive clock cycles.
The first and operator I4 performs an and operation on the output results of the three sub-circuits, and the obtained operation result is the output result of the read detection circuit 300. The read detection circuit 300 detects the column address, the row address and whether to read continuously through three sub-circuits, and detection processes of the three are independent from each other, so that the possibility of detection errors is reduced.
In one embodiment, before step a, the method may further comprise: the column detection sub-circuit 310 compares the column address of the current clock cycle with the column address of the previous clock cycle, and outputs a high signal to the first and operator I4 when the column address of the current clock cycle is different from the column address of the previous clock cycle.
In one embodiment, before step a, the method may further comprise: the row detection sub-circuit 320 compares the row address of the current clock cycle with the row address of the previous clock cycle, and outputs a high level signal to the first and operator I4 when the row address of the current clock cycle is the same as the row address of the previous clock cycle.
In one embodiment, before step a, the method may further comprise: the continuous read detection sub-circuit 330 determines whether the current clock cycle and the previous clock cycle both receive the read signal, and outputs a high level signal to the first and operator I4 when the current clock cycle and the previous clock cycle both receive the read signal.
Referring to fig. 7, in an embodiment, the step S120 specifically includes the following steps S121 to S123:
in step S121, the inverter inverts the level signal output by the read sensing circuit 300 and transmits the inverted level signal to the third and operator.
In step S122, the third and operator performs and operation on the level signal output by the inverter and the level signal of the WL line to obtain a first processing result, where the first processing result is the WL driving signal.
In step S123, the or operator performs an or operation on the level signal output by the read detection circuit 300 and the charging control signal to obtain a second processing result, where the second processing result is a control signal for switching the m BL charging circuits 120 to charge or stop charging.
After the level signal output by the read detection circuit 300 is inverted, the level signal is subjected to phase-inversion with the WL line, and the level signal output by the read detection circuit 300 is subjected to phase-inversion with the charge control signal, so that the level signal and the charge control signal of the WL line are influenced by the level signal output by the read detection circuit 300, and when the level signal output by the read detection circuit 300 is high, the level signal and the charge control signal of the WL line cannot cause the change of the WL driving signal and the control signal no matter the level signal and the charge control signal are high or low.
The static random access memory provided by the embodiment of the application can only perform one-time pre-charging when the voltage difference between the corresponding BL and the corresponding BLB is continuously read from the memory cells 110 in the same row and different columns, and the voltage difference established during the pre-charging can be directly read in the subsequent reading process of the memory cells 110 in different columns, so that the power consumption of multiple times of charging and discharging can be saved, and the purpose of saving the power consumption is achieved.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one logical division, and there may be other divisions when actually implemented, and for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or units through some communication interfaces, and may be in an electrical, mechanical or other form.
In addition, units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
Furthermore, the functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.
In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims (10)

1. A static random access memory is characterized by comprising a memory cell array, a read detection circuit and a read control circuit;
the memory cell array comprises m columns and n rows of memory cells, m switch groups and m BL charging circuits, wherein the m columns of memory cells correspond to the m switch groups one by one, and each column of memory cells is controlled by the corresponding switch group; the m BL charging circuits are in one-to-one correspondence with the m rows of storage units, and are used for charging BL lines and BLB lines connected with the storage units in the corresponding rows according to the control of the read control circuit;
the read probe circuit is to: when the static random access memory is detected to continuously read data from the memory cells in different columns of the same row, outputting a high-level signal representing continuous reading confirmation to the reading control circuit;
the read control circuit is used for maintaining the WL driving signal corresponding to the row where the memory cell is located to be low and maintaining the m BL charging circuits to be in a charging stop state when receiving the high level signal output by the read detection circuit, so as to keep the voltage difference between the BL line and the BLB line corresponding to the m memory cells which are located in the same row and different columns unchanged.
2. The SRAM of claim 1 wherein the read probe circuit comprises a column probe sub-circuit, a row probe sub-circuit, a sequential read probe sub-circuit, and a first AND operator, the column probe sub-circuit, the row probe sub-circuit, and the sequential read probe sub-circuit all being connected to the first AND operator;
the column detection sub-circuit is used for comparing a column address received in a current clock cycle with a column address received in a previous clock cycle, and outputting a high-level signal to the first AND operator when the column address of the current clock cycle is different from the column address of the previous clock cycle;
the row detection sub-circuit is used for comparing a row address received in a current clock cycle with a row address received in a previous clock cycle, and outputting a high-level signal to the first AND operator when the row address of the current clock cycle is the same as the row address of the previous clock cycle;
the continuous reading detection sub-circuit is used for judging whether a current clock period and a previous clock period both receive reading signals or not, and outputting high-level signals to the first AND operator when the current clock period and the previous clock period both receive the reading signals;
the first AND operator is used for outputting a high-level signal to the reading control circuit when receiving high-level signals representing different column addresses, high-level signals representing the same row address and high-level signals representing reading signals received in two continuous clock cycles.
3. The static random access memory of claim 2 wherein the column probe subcircuit includes a first flip-flop and an exclusive or operator;
the input end of the first trigger is used for receiving column address data, and the output end of the first trigger is connected with the first input end of the XOR operator;
the second input end of the exclusive-or operator is used for receiving the column address data, and the output end of the exclusive-or operator is connected with the first and operator.
4. The SRAM of claim 2 wherein said row-detect subcircuit includes a second flip-flop and an XNOR operator;
the input end of the second trigger is used for receiving row address data, and the output end of the second trigger is connected with the first input end of the exclusive-nor operator;
the second input end of the exclusive OR operator is used for receiving the row address data, and the output end of the exclusive OR operator is connected with the first exclusive OR operator.
5. The SRAM of claim 2 wherein the continuous read probe subcircuit includes a third flip-flop and a second AND operator;
the input end of the third trigger is used for receiving the reading signal, and the output end of the third trigger is connected with the first input end of the second AND operator;
the second input end of the second and operator is used for receiving the reading signal, and the output end of the second and operator is connected with the first and operator.
6. The static random access memory according to claim 2, wherein said read sensing circuit further comprises a latch, an input of said latch being connected to an output of said first and operator.
7. The SRAM of claim 1, wherein the read control circuit comprises an inverter, a third AND operator, and an OR operator;
the inverter is used for inverting the level signal output by the reading detection circuit and transmitting the inverted level signal to the third AND operator;
the third and operator is configured to perform and operation on the level signal output by the inverter and the level signal of the WL line to obtain a first processing result, where the first processing result is the WL driving signal;
the or arithmetic unit is configured to perform or arithmetic on the level signal output by the read detection circuit and the charging control signal to obtain a second processing result, where the second processing result is a control signal for switching m BL charging circuits to charge or stop charging.
8. The sram of claim 1, further comprising a selector coupled to the m switch groups, the selector configured to select one switch group from the m switch groups according to a received address and to turn on the selected switch group.
9. A processor comprising the static random access memory of any one of claims 1-8.
10. A method of reading data, the method comprising:
when detecting that the static random access memory continuously reads data from memory cells which are positioned in the same row and different columns, a read detection circuit in the static random access memory transmits a high-level signal representing continuous read confirmation to a read control circuit in the static random access memory;
after receiving a high-level signal output by the reading detection circuit, the reading control circuit maintains that the WL driving signal corresponding to the row where the storage units in the same row and different columns are located is low, and maintains that the BL charging circuits corresponding to the storage units in the same row and different columns are in a charging stop state, so as to keep the voltage difference between the BL lines and the BLB lines corresponding to the storage units in the same row and different columns unchanged, wherein the number of the BL charging circuits is the same as the number of the columns of the storage units.
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