CN116940984A - High speed multiport memory supporting conflicts - Google Patents

High speed multiport memory supporting conflicts Download PDF

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Publication number
CN116940984A
CN116940984A CN202280014931.XA CN202280014931A CN116940984A CN 116940984 A CN116940984 A CN 116940984A CN 202280014931 A CN202280014931 A CN 202280014931A CN 116940984 A CN116940984 A CN 116940984A
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port
read
write
response
bit
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Chinese (zh)
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P·拉杰
R·萨胡
S·K·古普塔
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Qualcomm Inc
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Qualcomm Inc
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/418—Address circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1075—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for multiport memories each having random access ports and serial ports, e.g. video RAM
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Multimedia (AREA)
  • Static Random-Access Memory (AREA)

Abstract

A multi-port memory is provided that supports conflicts between read ports and write ports for the same multi-port bit cell. The sense amplifier reads a data bit from the multi-port bit cell when a write port for the multi-port bit cell is addressed during a system clock signal. The multiplexer selects the output bit from the sense amplifier if the read ports for the multi-port bit cell are addressed during the same system clock signal.

Description

High speed multiport memory supporting conflicts
Cross Reference to Related Applications
The present application claims priority from U.S. application Ser. No. 17/210,230, filed 3/23 at 2021, the contents of which are incorporated herein by reference.
Technical Field
The present application relates to memory, and more particularly to high speed multiport memory that supports conflicts.
Background
A Static Random Access Memory (SRAM) bit cell includes a pair of cross-coupled inverters for storing bits. Two transistors are required for each inverter, so four transistors are required to implement two cross-coupled inverters. In a conventional single-port SRAM bitcell, two additional access transistors complete the bitcell implementation, such that a total of six transistors are required. The two access transistors are controlled by a shared word line such that the two access transistors form a single read/write port to the bit cell. However, for multiprocessor applications, single port architectures can present problems because contention can occur between multiple processors at a single access port. By adding additional access transistors, the multi-port SRAM bit cell may have an access (read) port for each processor.
While multi-port SRAM is advantageous for multi-processor architectures, conflicts can occur if write operations are performed simultaneously with read operations at the same multi-port SRAM bit cell. To avoid conflicts, it is conventional for the system clock signal controlling the memory access to access the multiport SRAM bit cells in a "dual pump" manner. In response to a transition (e.g., a rising edge) of the system clock signal, a read operation may be performed on one or more of the access ports during a first portion of a period of the system clock signal. After the read operation is completed, the write operation may then occur in a second portion of the system clock signal period. But the dual pump operation reduces memory speed because the write and read operations must occur sequentially during the system clock signal period.
Disclosure of Invention
According to one aspect of the present disclosure, there is provided a multi-port memory comprising: a multi-port bit cell including a first read port having a first read port bit line, the multi-port bit cell further including a pair of write port bit lines; a sense amplifier coupled to the pair of write port bit lines; a first inverter coupled to the first read port bit line; and a first multiplexer configured to select between the data output bits from the sense amplifier and the data output bits from the first inverter to provide the selected data output bits.
According to another aspect of the present disclosure, there is provided a method of operation for a multi-port memory, the method comprising: comparing the first read port address with the write port address to detect a first conflict in response to the first read port address matching the write port address and to detect a lack of the first conflict in response to the first read port address not matching the write port address; selecting, at the first multiplexer, data output bits resulting from single-ended reading of the multi-port bit cell through the first read port in response to a lack of detection of the first collision; and selecting, at the first multiplexer, data output bits resulting from differential reading of the multi-port bit cell through the write port in response to a detection result of the first collision.
According to yet another aspect of the present disclosure, there is provided a multi-port memory including: a multi-port bit cell including a first read port having a first read port bit line and a first read port word line, the multi-port bit cell further including a write port having a pair of write bit lines; an address comparator configured to detect a conflict in response to a write port address pointing to a write port and a read port address pointing to a first read port; and a read port word line controller configured to assert the first read port word line in response to a lack of a detection result of the conflict and configured to de-assert the first read port word line in response to a detection result of the conflict.
According to yet another aspect of the present disclosure, there is provided a multi-port memory including: an address comparator configured to detect a conflict in response to both the read port address and the write port address pointing to the first multi-port bitcell; a sense amplifier configured to read a first data bit from a first multi-port bit cell through a write port; a write driver configured to write the second data bit into the first multi-port bit cell through the write port after the reading of the first data bit is completed; and a multiplexer coupled to the sense amplifier, the multiplexer configured to select the first data bit in response to a detection result of the collision.
These and additional advantages will be better understood from the detailed description that follows.
Drawings
FIG. 1 illustrates an example multi-port bitcell for practicing conflict supported multi-port memories disclosed herein.
FIG. 2 is a flow diagram of an example implementation of conflict support in accordance with an aspect of the present disclosure.
Fig. 3 is a circuit diagram of a multiport memory configured to provide conflict support in accordance with an aspect of the present disclosure.
Fig. 4 is a flow chart of a method of operation for conflict support in accordance with an aspect of the present disclosure.
FIG. 5 illustrates some example electronic systems, each incorporating multiport memory with conflict support, according to one aspect of the present disclosure.
Embodiments of the present disclosure and their advantages may be better understood by referring to the detailed description that follows. It should be understood that like reference numerals are used to identify like elements illustrated in one or more of the figures.
Detailed Description
A multi-port SRAM is disclosed that supports conflicts rather than avoiding conflicts, such as by double-pumped (double-pumped) operation. To support conflicts, the memory includes an address comparator for each read port. Each address comparator compares a read port address with a write port address. If the comparison indicates that the read port address points to the first multi-port bit cell and the write port address points to the second multi-port bit cell, a single-ended read operation of the first multi-port bit cell through the read port occurs. At the same time, a write operation to the second multi-port bitcell through the write port occurs. High speed operation is enhanced due to simultaneous actuation of the read port and the write port (albeit in different multi-port bit cells).
However, if the address comparison indicates that the read port address and the write port address point to the same multi-port bitcell, then the read port is not accessed. To perform the read, the multi-port SRAM utilizes a speed difference between a single-ended read operation and a differential read operation. To this end, the write operation is delayed until a differential read occurs through the write port. Thus, such differential read operations may occur each time a write port is accessed. Although the write operation is delayed so that differential reading can occur first, the memory operating speed is not affected because single-ended reading through the read port is not as fast as differential reading. Differential read and write operations (also differential) can thus be completed in approximately the same amount of time as required for single-ended read operations. Note that the advantages are: if the multiport bitcells do not collide, the single-ended read operation may proceed. On the other hand, for multi-port bit cells with collisions, differential reading may occur. Thus, no delay occurs as may occur in the dual pump approach.
An exemplary multi-port bitcell will now be discussed, but it should be appreciated that an SRAM with any suitable multi-port bitcell architecture may practice the conflict support disclosed herein. Further, the example multi-port bit cell below has a pair of read ports, but in alternative implementations, only one read port may be included in the multi-port bit cell. Thus, the multi-port SRAM bit cell includes at least one read port in addition to a write port. The write port and the read port may be better understood in view of the example three-port SRAM bit cell 100 shown in fig. 1. The write ports include a write port access n-type metal oxide semiconductor (NMOS) transistor M3 and another write port access NMOS transistor M4. The Write Word Line (WWL) is connected to the gates of the write port access transistors M3 and M4 such that when the write word line is charged to the supply voltage, the write port access transistors are turned on. The write port also includes a pair of write bit lines formed from a real Write Bit Line (WBL) and a complementary Write Bit Line (WBLB). For simplicity, in the discussion that follows, a true write bit line may also be simply denoted a write bit line. The write bit line WBL is connected to the drain/source terminal of the write port access transistor M3. The remaining drain/source terminal of write port access transistor M3 is connected to the Q data output node of bit cell 100. The terminals are referred to as "drain/source" terminals because which terminal is the source and which terminal is the drain depends on the binary state of the SRAM bit cell 100 prior to the write operation and also depends on the binary state of the bit being written to the SRAM bit cell 100 during the write operation. The complementary write bit line WBLB is similarly arranged when it is connected to the drain/source terminal of the write port access transistor M4. The remaining drain/source terminal of the write port access transistor M4 is connected to the complementary data output node QB of the SRAM bit cell 100.
The write bit lines WBL and WBLB are precharged to the supply voltage prior to the write operation. The write operation occurs in response to an edge (e.g., a rising edge) of the system clock signal. A word line generator or controller (not shown in fig. 1, but discussed further below) responds to the clock edge by charging the write word line WWL to the supply voltage such that the write port access transistor is turned on. With the write word line asserted (also referred to as "active"), a write driver (also not shown in FIG. 1, but discussed further below) may then drive the write bit line pair with the data bit to be written to the multi-port bit cell. If the binary value of the data bit is true, the write driver discharges the complementary write bit line WBLB while keeping the real write bit line WBL charged. Conversely, in response to the data bit being false, the write driver discharges the real write bit line WBL while keeping the complementary write bit line WBLB charged.
Depending on which write bit line is charged and which write bit line is discharged to ground by the write driver, it will be determined which output node of SRAM bit cell 100 is charged to the supply voltage or discharged to ground. For example, if the write bit line remains charged during a write operation, the Q output node is charged and the complementary QB output node is discharged. The Q output node is also the output node of the first inverter cross-coupled with the second inverter in SRAM bit cell 100. The first inverter includes a P-type metal oxide semiconductor (PMOS) transistor P1, a source of the PMOS transistor P1 being connected to a power supply node for a power supply voltage. The drain of the transistor P1 is connected to the drain of the NMOS transistor M1. The source of transistor M1 is connected to ground. The drains of transistors P1 and M1 form the output node of the first inverter and also form the Q output node of bit cell 100.
The second inverter is arranged in a similar way and thus comprises a PMOS transistor P2, the source of which PMOS transistor P2 is connected to the power supply node and the drain of which is connected to the drain of an NMOS transistor M2, the source of which NMOS transistor M2 is connected to ground. The drains of transistors P2 and M2 form the output node of the second inverter and also form the QB output node. To accomplish cross-coupling between the inverters, the Q output node is connected to the gates of transistors P2 and M2. Similarly, the QB output node is connected to the gates of transistors P1 and M2. Thus, the two inverters strengthen each other and latch the bit being written to the SRAM bit cell 100.
The first read port a of the SRAM bit cell 100 includes an NMOS transistor M5, an NMOS access transistor M6, a read port a bit line a (RBLA), and a read port a word (RWLA). The read port a bit line RBLA is connected to the drain of access transistor M6. The source of access transistor M6 is connected to the drain of transistor M5. The source of transistor M5 is connected to ground. The Q output node is connected to the gate of transistor M5. The read port a word line RWLA is connected to the gate of access transistor M6. The read port a bit line RBLA is precharged to the supply voltage prior to a read operation on the read port a. The read port a bit line RBLA is then floating during a single-ended read operation to read port a so that the bit line voltage can be affected by the single-ended read operation of SRAM bit cell 100 through read port a. During a single-ended read operation on read port a, read port a word line RWLA is charged to the supply voltage to turn on access transistor M6. If the Q output node had been charged to the supply voltage prior to the read operation on port A, transistor M5 would be turned on to discharge the source of transistor M6. With access transistor M6 turned on from the assertion of read port A word line RWLA, read port A bit line RBLA will then discharge through transistors M5 and M6. Since the read operation to read port a is single ended (which involves only one read bit line), the sense amplifier for sensing the binary content of SRAM bit cell 100 through read port a may be formed by a simple inverter (not shown in fig. 1, but discussed further below). When the read port A bit line RBLA discharges to the trip point of the sense amplifier inverter, the sense amplifier inverter will assert its output signal to the supply voltage to successfully represent the binary signal being read from the SRAM bit cell 100. Since the sense amplifier inverters disclosed herein are each formed of an inverter serving as a sense amplifier, the sense amplifier inverter may also be simply referred to herein as an inverter.
If the SRAM bit cell 100 stores a binary zero, the Q output node will discharge prior to the read operation. In this case, transistor M5 will be turned off so that read port A bit line RBLA maintains its pre-charge state during a read operation on read port A. Thus, the sense amplifier inverter will continue to discharge its output signal to represent a binary zero read from the SRAM bit cell 100.
The remaining read port B is similarly configured to include NMOS transistors M7 and M8 and read port B word line (RWLB) and read port B bit line (RBLB). The read port B bit line RBLB is connected to the drain of access transistor M8. The source of access transistor M8 is connected to the drain of transistor M7. The source of transistor M7 is connected to ground. The QB output node is connected to the gate of transistor M7. The read port B word line RWLB is connected to the gate of access transistor M8. The read port B bit line RBLB is precharged to the supply voltage prior to a single ended read operation on the read port B. The read port B bit line RBLB is then floating so that its voltage can be affected by the read operation of the SRAM bit cell 100 through the read port B. During a single-ended read operation through read port B, read port B word line RWLB is charged to the supply voltage to turn on access transistor M8. If the QB output node had been charged to the supply voltage prior to the read operation on port B, transistor M7 would be turned on to discharge the source of access transistor M8. With access transistor M8 turned on from the assertion of read port B word line RWLB, read port B bit line RBLB will then discharge through transistors M7 and M8. Conversely, if the QB node is discharged, the read port B bit line RBLB remains precharged during the read port B access.
Single-ended read operations to read ports a and B are only performed without conflicts. If a write operation to multiport bitcell 100 through a write port occurs in the same system clock cycle as a read operation to read port a and/or read port B, then a conflict occurs. A read operation attempts to read the binary state of a bit already stored in SRAM bit cell 100, while a write operation potentially changes the binary state. The resulting conflict may corrupt the read operation. As previously mentioned, collision mitigation is typically performed by a dual pump operation that divides the system clock cycle into two portions. In the first portion, a read operation to either (or both) of the read ports a and B occurs. The write port is not accessed during the first portion. In a second portion of the system clock cycle, a write operation is performed. If the dual pump operation is performed correctly, there may be no conflict because no write operation occurs during the read operation. But this splitting of the system clock cycles in dual pump operation reduces the memory operating speed.
To avoid timing loss for dual pump operation, a multi-port memory is provided in which the system clock period is not divided into separate portions for read and write operations. Instead, an address comparison is performed on each active read port to determine if the write port of the SRAM bitcell is also being addressed by a write operation. If the address comparison indicates that no write operation has occurred to the addressed SRAM bitcell, a single ended read operation occurs over the corresponding read port. Such single-ended read operations occur, such as discussed with respect to SRAM bit 100. The corresponding read port bit line is thus precharged and then floated, while the corresponding read word line is then charged so that the resulting voltage of the read port bit line can be sensed by the sense amplifier inverter to produce either a read port data output bit or a complementary read port data output bit, depending on whether it is the addressed read port a or B. However, if the address comparison indicates that the write port of the SRAM bitcell is also accessed, then the read operation will not occur over the read port. Since the read port is not used, the corresponding read port bit line will not float and the corresponding read word line voltage will not be asserted. Conversely, if the write port of the multi-port SRAM bitcell is accessed during the same system clock cycle that accesses one (or both) of the read ports, then the read operation occurs through the write port.
A read operation through a write port utilizes the difference between the read port and the write port. In particular, note that the write operation to the write port is differential in that it involves a pair of write port bit lines, while the read operation to either of the read ports a and B is single ended and occurs over only one read port bit line. Given the differential nature of write port access, differential reading of bits stored in a multi-port SRAM bit cell can occur relatively quickly through a write port as compared to single-ended reading on one of the read ports. In this regard, the threshold voltage of the sense amplifier inverter for performing single-ended reading is about half of the power supply voltage. For example, assume that the power supply voltage is 0.8V. The threshold voltage for the sense amplifier inverter to perform single ended reading through the read port may be about 400mV. The precharge read port bit line must be discharged from 800mV to a 400mV trigger point before the sense amplifier inverter can make its bit decisions. Differential reading over the write port bit line does not require such relatively large voltage variations before a differential sense amplifier coupled to the write port bit line can make a bit decision.
If the write port is addressed within a given system clock cycle, driving of the write port bit line with the data bit to be written during the write operation will be delayed until a differential read operation can occur. The write port bit line may be precharged in a default state prior to write port access. During differential reading over the write port, one of the write port bit lines will begin discharging from the default precharge state, depending on the binary value of the bit stored in the multi-port SRAM bit cell. Then, a voltage difference is generated between the write port bit lines, which is sensed by the differential sense amplifier. The differential sense amplifier may make a bit decision when the voltage difference is only a small fraction of the supply voltage (e.g., 100mV, or 80mV, or even less) compared to the threshold voltage of the sense amplifier inverter. The voltage difference between the write port bit lines for making a differential bit decision in the differential sense amplifier is relatively small compared to the threshold voltage of the sense amplifier inverter making a single-ended bit decision. Thus, the voltage difference between the write port bit lines sufficient to perform differential reading occurs relatively quickly compared to single-ended read operations.
Given this relative rapidity of differential reading, differential reading and driving the write bit lines to complete the write operation can still be performed in substantially the same amount of time as it takes for a single-ended read operation. Thus, the resulting operation is relatively high speed compared to a dual pump operation, because the write operation (with its initial differential read) can begin substantially simultaneously with the execution of the single-ended read operation, but the address comparison indicates that the write port is also being addressed.
In general, it will be more common to access the read ports of a multiport SRAM bit cell without conflicts. In this case, single-ended reading occurs over the addressed read port. The write port is not accessed and therefore the write bit line remains in its default precharge state. It may be the case that both the read port and the write port are addressed for a given multi-port SRAM bit cell in the same system clock cycle. In this case, single-ended reading does not occur over the addressed read port, but over the write port, through which differential reading operations occur prior to initiation and completion of the write operation. The differential read operation senses the data bits stored in the multi-port SRAM bit cell and their complements. The multiplexer may select a bit decision from the sense amplifier inverter for the addressed read port if the write port is not addressed (no conflict) or from the differential sense amplifier if the write port is addressed (conflict exists). The latches can then latch the bit decision selections from the multiplexer.
A flow chart 200 for generating conflict mitigation for a multi-port SRAM is shown in fig. 2. With respect to the multi-port SRAM, the multi-bit cell 100 is an example of a suitable multi-port bit cell, but it should be understood that the conflict mitigation disclosed herein may be practiced with any suitable multi-port bit cell architecture. The flowchart 200 begins in response to a trigger edge of a clock signal 205 for starting a read and/or write operation. With respect to flowchart 200, the write port is denoted as port C to distinguish it from read ports A and B. After the trigger edge of the clock signal 205, it may be the case that the write port is addressed, although this need not be the case for every cycle of the clock signal 205. If the write port is addressed, then the write word line (port C word line) is asserted in step 220. After assertion of the write word line, the bits stored in the multi-port bitcell corresponding to write port C are retrieved via differential read 240 through the pair of write bit line pair write port C. The differential sense amplifier then senses the binary value of the retrieved bit. In the event that the differential read is complete, the write driver proceeds to drive writing the data bit to the corresponding bit cell through write port C in step 265. In the event that the write operation is complete, the write word line may be discharged (turned off) to complete step 265.
To determine if a conflict with read port a occurred in the same clock cycle, read port a and write port C addresses are compared in step 210. If the addresses point to the same multiport bitcell (e.g., the addresses may be equal), a conflict occurs, which is represented in flowchart 200 as a "yes" decision. In contrast, if the read port A and write port C addresses point to different multi-port bit cells, no conflict with respect to read port A will occur (represented as a "NO" decision in flowchart 200). If there is no conflict at read port A, then read port A word line may be charged in step 225 so that a single ended read operation may be performed through read port A in step 235. Multiplexer 250 may then select the single ended read result (assuming no collision) so that the output bits may be latched in step 260. However, if there is a conflict between ports A and C, then the read port A word line is not asserted and multiplexer 250 selects the output bit resulting from the differential read operation in step 240. The selection by multiplexer 250 may thus be controlled by whether the yes decision for the conflict between ports a and C in step 210 is true or false.
In step 215, a similar address comparison is made for read port B. If port B and port C addresses point to the same multi-port bitcell, a collision will occur ("yes" decision). In contrast, if the read port B and write port C addresses point to different multi-port bit cells, no conflict with respect to read port B will occur (a "no" decision). If there is no conflict at read port B, then read port B word line may be charged in step 230 so that a single ended read operation may be performed through read port B in step 245. Multiplexer 255 may then select the single ended read result of port B (assuming no collision) so that the complementary output bits may be latched in step 270. However, if there is a conflict between ports B and C, then the read port B word line is not asserted and multiplexer 255 selects the complementary output bit generated by the differential read operation in step 240. The selection by multiplexer 255 may thus be controlled by whether the yes decision for the conflict between ports B and C in step 215 is true or false.
An SRAM 300 configured for collision avoidance will now be discussed with respect to fig. 3. The address comparator 305 performs an address comparison between the port a address and the port C address in response to a trigger edge of the system clock signal (CLK). If the comparison indicates that there is no conflict between ports A and C, the address comparator 305 passes the system clock signal as the clock A signal (CLKA) for the precharge, and the port A wordline controller 310 triggers the assertion (charge) of the port A wordline and the floating of the precharged port A bitline in response to the assertion of the precharge A signal. The state (true or false) of the precharge signal a may control the selection by the multiplexer 250, as will be further explained herein.
Address comparator 315 performs an address comparison between the port B address and the port C address in response to a trigger edge of the system clock signal (CLK). If the comparison indicates that there is no conflict between ports B and C, address comparator 315 passes the system clock signal as a clock B signal (CLKB) for precharge and port B wordline controller 311 triggers assertion (charging) of the port B wordline and floating of the precharged port B bitline in response to assertion of the precharge B signal. The state (true or false) of the precharge signal B may control the selection by the multiplexer 255, as will be further explained herein.
As previously described, the write ports in the multi-port bitcell 100 include write word line WWL and write bit lines WBL and WBLB. Differential sense amplifier 320 is coupled to write bit lines WBL and WBLB such that when write word line WWL is asserted to open a write port, differential sense amplifier 320 can sense both the data bits stored in multiport bitcell 100 and their complements. The sense data bit is denoted Sout and the complementary sense data bit is denoted SoutB. The sensing by sense amplifier 320 is responsive to assertion of the sense enable signal. The sense amplifier 320 is also integrated with a write driver (Din driver) which can then drive the write bit lines WBL and WBLB with the data bits Din to be written after the differential read operation is completed.
The precharge a signal drives the gate of PMOS transistor P4, the source of PMOS transistor P4 being tied to the supply voltage node and the drain thereof being connected to the read port a bit line. The precharge a signal controls whether the read port a bit line is floating or held in its default precharge state. When the precharge a signal is deasserted, the precharge of the read port a bit line occurs due to the conduction of transistor P4. As used herein, a signal is considered "asserted" when it is true, whether using a logic high or logic low convention. The precharge a signal is active high so it is asserted by being charged to the supply voltage. The precharge a signal also controls the floating of the global read port a bit line (GRBLA). To this end, the precharge a signal also drives the gate of PMOS transistor P5, the drain of PMOS transistor P5 being connected to the global read port a bit line and the source thereof being connected to the power supply node. De-assertion of the precharge a signal thus also forces transistor P5 to turn on to precharge the global read bit line a to the supply voltage. The inverter INV C inverts the binary state of the read port a bit line to drive the gate of the NMOS transistor M9, the source of the NMOS transistor M9 being connected to ground and the drain thereof being connected to the global read port a bit line. Thus, transistor M9 is turned off when the read port A bit line is precharged. If read port A is addressed, the precharge A signal will be asserted to turn off both transistors P4 and P5, causing both read port A bit line RBLA and global read port A bit line GRBLA to float. If the data bit stored in multiport bitcell 100 is a binary zero (assuming a logic high convention), the precharge state of the RBLA line and the GRBLA line will not be affected, although they are floating. The read port a sense amplifier inverter (INV a) inverts the binary state of the GRBLA line to provide the sense data output bit selected by the multiplexer 250 due to assertion of the precharge a signal. But in the event of a collision, the precharge a signal is not asserted so that multiplexer 250 selects the Sout data bit from differential sense amplifier 320. Data output latch 325 may then latch the sense bit (DoutA) regardless of whether it is generated by read port a or write port C.
Read port B is similar. The precharge B signal drives the gate of PMOS transistor P6, the source of PMOS transistor P6 is tied to the supply voltage node and its drain is connected to the read port B bit line B (RBLB). The precharge B signal controls whether the read port B bit line is floating or remains in its default precharge state. When the precharge B signal is deasserted, the precharge of the read port B bit line occurs due to the conduction of transistor P6. The precharge B signal also controls the floating of the global read port B bit line (GRBLB). To this end, the precharge B signal also drives the gate of PMOS transistor P7, the drain of PMOS transistor P7 being connected to the global read port B bit line and the source thereof being connected to the power supply node. Deassertion of the precharge B signal thus also forces transistor P7 to turn on to precharge the global read port B bit line to the supply voltage. The inverter INV D inverts the binary state of the read port B bit line to drive the gate of the NMOS transistor M10, the source of the NMOS transistor M10 being connected to ground and the drain thereof being connected to the global read port B bit line. Thus, transistor M10 is turned off when the read port B bit line is precharged. If read port B is addressed, the precharge B signal will be asserted to turn off both transistors P6 and P7, causing both read port B bit line RBLB and global read port B bit line GRBLB to float. If the data bit stored in the multi-port bit cell 100 is a binary zero (again assuming a logic high convention), the precharge state of the RBLB and GRBLB lines will not be affected, although they are floating. The read port B sense amplifier inverter (INV B) inverts the binary state of the GRBLB line to provide the sense data output bit selected by multiplexer 255 due to assertion of the precharge B signal. But in the event of a collision, the precharge B signal is not asserted so that multiplexer 255 instead selects the SoutB complementary data bit from differential sense amplifier 320. Data output latch 325 may then latch the sense bit (DoutB), whether it is generated by read port B or write port C.
The conflict support method will now be discussed with reference to the flowchart of fig. 4. The method includes an act 400 of comparing the first read port address with the write port address to detect a first conflict in response to the first read port address matching the write port address and to detect a lack of the first conflict in response to the first read port address not matching the write port address. A comparison in either of address comparators 305 and 315 is an example of act 400. The method also includes an act 405, the act 405 occurring at the first multiplexer and including selecting data output bits resulting from single-ended reading of the multi-port bit cell through the first read port in response to a lack of detection of the first conflict. Selection at either of multiplexers 250 or 255 without conflict is an example of act 405. Finally, the method includes an act 410, the act 410 also occurring at the first multiplexer and including selecting data output bits resulting from a differential read of the multi-port bit cell through the write port in response to a detection result of the first conflict. Selection with conflict at either of multiplexers 250 or 255 is an example of act 410.
Multiport memories with conflict support as disclosed herein may be incorporated into a wide variety of electronic systems. For example, as shown in fig. 5, cellular telephone 500, laptop computer 505, and tablet PC 510 may all include multiport memory with conflict support in accordance with the present disclosure. Other exemplary electronic systems, such as music players, video players, communication devices, and personal computers, may also be configured with multiport memory constructed in accordance with the present disclosure.
The present disclosure will now be summarized in the following series of clauses:
clause 1. A multiport memory comprising:
a multi-port bitcell including a first read port having a first read port bit line, the multi-port bitcell further including a pair of write port bit lines;
a sense amplifier coupled to the pair of write port bit lines;
a first inverter coupled to the first read port bit line; and
a first multiplexer configured to select between the data output bits from the sense amplifier and the data output bits from the first inverter to provide selected data output bits.
Clause 2. The multi-port memory of clause 1, wherein the multi-port bit cell further comprises a second read port having a second read port bit line, the multi-port memory further comprising:
A second inverter coupled to the second read port bit line; and
a second multiplexer configured to select between the complementary data output bits from the sense amplifier and the complementary data output bits from the second inverter to provide selected complementary data output bits.
Clause 3 the multi-port memory of clause 2, further comprising:
a data latch configured to latch the selected data output bit and the selected complementary data output bit.
Clause 4. The multi-port memory of any of clauses 1 to 3, further comprising:
an address comparator configured to detect a collision in response to a read port address being the same as a write port address, and to detect a lack of collision in response to the read port address being different from the write port address; and
a read word line controller configured to assert a read port word line for the first read port in response to the lack of detection of a conflict, and not assert the read port word line in response to the detection of a conflict.
Clause 5, the multi-port memory of clause 4, wherein the read word line controller is further configured to assert a precharge signal in response to the lack of conflicting detection results, and not assert the precharge signal in response to the conflicting detection results.
Clause 6 the multi-port memory of clause 5, further comprising a transistor coupled between the first read port bit line and a supply node for a supply voltage, wherein the transistor is configured to turn on in response to the assertion of the precharge signal and to turn off in response to the deassertion of the precharge signal.
Clause 7. The multi-port memory of clause 6, wherein the transistor comprises a p-type metal oxide semiconductor (PMOS) transistor.
Clause 8. The multi-port memory of any of clauses 1 to 7, further comprising:
a write driver configured to drive the pair of write bit lines in response to bits to be written to the multi-port bit cell after a sensing operation is completed by the sense amplifier.
Clause 9 the multi-port memory of clause 4, wherein the multi-port bit cell comprises a pair of cross-coupled inverters configured to drive a data output node and a complementary data output node, and wherein the first read port further comprises an access transistor configured to be controlled by the read port word line.
Clause 10, the multi-port memory of clause 9, wherein the first read port further comprises a second transistor coupled between ground and a terminal of the access transistor, and wherein a gate of the second transistor is coupled to the data output node, and wherein the multi-port memory is integrated into a cellular telephone.
Clause 11. A method of operation for a multi-port memory, comprising:
comparing a first read port address with a write port address to detect a first conflict in response to the first read port address matching the write port address and to detect a lack of a first conflict in response to the first read port address not matching the write port address;
selecting, at the first multiplexer, data output bits resulting from single-ended reading of the multi-port bit cell through the first read port in response to the lack of detection of the first collision; and
at the first multiplexer, a data output bit resulting from a differential read of the multi-port bit cell through a write port is selected in response to a detection result of the first collision.
Clause 12 the method of clause 11, further comprising:
the comparison of the first read port address and the write port address is triggered in response to an edge of a clock signal.
Clause 13 the method of any of clauses 11 to 12, further comprising:
comparing a second read port address with the write port address to detect a second conflict in response to the second read port address matching the write port address and to detect a lack of a second conflict in response to the second read port address not matching the write port address;
selecting, at a second multiplexer, complementary data output bits resulting from single-ended reading of the multi-port bit cell through a second read port in response to the lack of detection of a second collision; and
at the second multiplexer, complementary data output bits resulting from the differential reading of the multi-port bit cell through the write port are selected in response to a detection result of the second collision.
The method of any one of clauses 11 to 13, further comprising:
precharging a first bit line in the first read port prior to comparing the first read port address with the write port address; and
Floating the first bit line in response to a detection result of the first collision; and
in response to the detection of the lack of the first conflict, the precharge of the first bit line is maintained.
Clause 15 the method of clause 14, further comprising:
in response to the detection of the lack of the first conflict, a precharge signal is asserted, wherein the floating of the first bit line occurs in response to the assertion of the precharge signal.
Clause 16 the method of clause 15, further comprising:
in response to the assertion of the precharge signal, a transistor coupled between the first bit line and a supply node for a supply voltage is turned off.
Clause 17 the method of clause 16, further comprising:
in response to the detection of the first conflict, de-assertion of the precharge signal is maintained to maintain the on state of the transistor.
The method of any one of clauses 11 to 17, further comprising:
the data output bits from the first multiplexer are latched.
Clause 19, a multiport memory comprising:
a multi-port bit cell including a first read port having a first read port bit line and a first read port word line, the multi-port bit cell further including a write port having a pair of write bit lines;
An address comparator configured to detect a conflict in response to a write port address pointing to the write port and a read port address pointing to the first read port; and
a read port word line controller configured to assert the first read port word line in response to a lack of a detection result of the conflict, and configured to de-assert the first read port word line in response to a detection result of the conflict.
Clause 20, wherein the read port word line controller is further configured to assert a precharge signal for the first read port in response to the absence of the detection of the conflict, and wherein the first read port is further configured to float the first read port bit line in response to assertion of the precharge signal.
Clause 21 the multi-port memory of any of clauses 19 to 20, further comprising:
a sense amplifier configured to perform differential reading through the write port in response to the write port address pointing to the write port.
Clause 22 the multi-port memory of clause 21, further comprising:
A data driver configured to drive the pair of write port bit lines with data bits to be written to the multi-port bit cell after the differential read is completed.
Clause 23 the multi-port memory of any of clauses 21 to 22, further comprising:
an inverter coupled to the first read port bit line; and
a multiplexer configured to select between the sense amplifier and the output of the inverter.
Clause 24, a multiport memory comprising:
an address comparator configured to detect a collision in response to both the read port address and the write port address pointing to the first multi-port bit cell;
a sense amplifier configured to read a first data bit from the first multi-port bit cell through a write port;
a write driver configured to write a second data bit to the first multi-port bit cell through the write port after the read of the first data bit is completed; and
a multiplexer coupled to the sense amplifier, the multiplexer configured to select the first data bit in response to a detection result of the collision.
Clause 25. The multi-port memory of clause 24, further comprising:
An inverter coupled to a read port bit line in a first read port in the first multi-port bit cell, wherein the multiplexer is further configured to select an output of the inverter in response to a lack of a detection result of the collision.
Clause 26 the multi-port memory of clause 25, further comprising:
a data latch configured to latch an output bit from the multiplexer.
Clause 27 the multi-port memory of any of clauses 25 to 26, wherein the first multi-port bit cell comprises a second read port.
Clause 28 the multi-port memory of any of clauses 25 to 27, further comprising:
a read port word line controller configured to assert a word line for the first read port in response to the lack of the detection of the conflict.
Clause 29, the multi-port memory of clause 28, wherein the read port word line controller is further configured to assert a precharge signal for the first read port in response to the lack of the conflicting detection result.
Clause 30 the multi-port memory of any of clauses 24 to 29, wherein the address comparator is configured to be triggered to detect the conflict in response to an edge of a clock signal.
As will now be appreciated by some of skill in the art, many modifications, substitutions, and variations may be made to the materials, apparatus, arrangements, and methods of use of the apparatus of the present disclosure, depending on the particular application at hand, without departing from the scope of the present disclosure. In view of the foregoing, the scope of the present disclosure should not be limited to the specific embodiments herein shown and described, since they are presented as examples only and the scope of the present disclosure should be fully commensurate with the scope of the claims appended hereto and their functional equivalents.

Claims (30)

1. A multi-port memory, comprising:
a multi-port bitcell including a first read port having a first read port bit line, the multi-port bitcell further including a pair of write port bit lines;
a sense amplifier coupled to the pair of write port bit lines;
a first inverter coupled to the first read port bit line; and
a first multiplexer configured to select between the data output bits from the sense amplifier and the data output bits from the first inverter to provide selected data output bits.
2. The multi-port memory of claim 1, wherein the multi-port bitcell further comprises a second read port having a second read port bit line, the multi-port memory further comprising:
A second inverter coupled to the second read port bit line; and
a second multiplexer configured to select between the complementary data output bits from the sense amplifier and the complementary data output bits from the second inverter to provide selected complementary data output bits.
3. The multi-port memory of claim 2, further comprising:
a data latch configured to latch the selected data output bit and the selected complementary data output bit.
4. The multi-port memory of claim 1, further comprising:
an address comparator configured to detect a collision in response to a read port address being the same as a write port address, and to detect a lack of collision in response to the read port address being different from the write port address; and
a read word line controller configured to assert a read port word line for the first read port in response to the lack of detection of a conflict, and not assert the read port word line in response to the detection of a conflict.
5. The multi-port memory of claim 4, wherein the read word line controller is further configured to assert a precharge signal in response to the lack of conflicting detection results and not assert the precharge signal in response to the conflicting detection results.
6. The multi-port memory of claim 5, further comprising: a transistor coupled between the first read port bit line and a power supply node for a power supply voltage, wherein the transistor is configured to turn on in response to assertion of the precharge signal and turn off in response to non-assertion of the precharge signal.
7. The multi-port memory of claim 6, wherein the transistor comprises a p-type metal oxide semiconductor (PMOS) transistor.
8. The multi-port memory of claim 1, further comprising:
a write driver configured to drive the pair of write bit lines in response to bits to be written to the multi-port bit cell after a sensing operation is completed by the sense amplifier.
9. The multi-port memory of claim 4, wherein the multi-port bit cell comprises a pair of cross-coupled inverters configured to drive a data output node and a complementary data output node, and wherein the first read port further comprises an access transistor configured to be controlled by the read port word line.
10. The multi-port memory of claim 9, wherein the first read port further comprises a second transistor coupled between ground and a terminal of the access transistor, and wherein a gate of the second transistor is coupled to the data output node, and wherein the multi-port memory is integrated into a cellular telephone.
11. A method of operation for a multi-port memory, comprising:
comparing a first read port address with a write port address to detect a first conflict in response to the first read port address matching the write port address and to detect a lack of a first conflict in response to the first read port address not matching the write port address;
selecting, at the first multiplexer, data output bits resulting from single-ended reading of the multi-port bit cell through the first read port in response to the detection of the missing first collision; and
at the first multiplexer, a data output bit resulting from a differential read of the multi-port bit cell through a write port is selected in response to a detection result of the first collision.
12. The method of claim 11, further comprising:
the comparison of the first read port address and the write port address is triggered in response to an edge of a clock signal.
13. The method of claim 11, further comprising:
comparing a second read port address with the write port address to detect a second conflict in response to the second read port address matching the write port address and to detect a lack of a second conflict in response to the second read port address not matching the write port address;
selecting, at a second multiplexer, complementary data output bits resulting from single-ended reading of the multi-port bit cell through a second read port in response to the lack of detection of a second collision; and
at the second multiplexer, complementary data output bits resulting from the differential reading of the multi-port bit cell through the write port are selected in response to a detection result of the second collision.
14. The method of claim 11, further comprising:
precharging a first bit line in the first read port prior to comparing the first read port address with the write port address; and
Floating the first bit line in response to a detection result of the first collision; and
in response to the detection of the lack of the first conflict, the precharge of the first bit line is maintained.
15. The method of claim 14, further comprising:
in response to the detection of the lack of the first conflict, a precharge signal is asserted, wherein the floating of the first bit line occurs in response to the assertion of the precharge signal.
16. The method of claim 15, further comprising:
in response to the assertion of the precharge signal, a transistor coupled between the first bit line and a supply node for a supply voltage is turned off.
17. The method of claim 16, further comprising:
in response to the detection of the first conflict, de-assertion of the precharge signal is maintained to maintain the on state of the transistor.
18. The method of claim 11, further comprising:
the data output bits from the first multiplexer are latched.
19. A multi-port memory, comprising:
a multi-port bit cell including a first read port having a first read port bit line and a first read port word line, the multi-port bit cell further including a write port having a pair of write bit lines;
An address comparator configured to detect a conflict in response to a write port address pointing to the write port and a read port address pointing to the first read port; and
a read port word line controller configured to assert the first read port word line in response to a lack of a detection result of the conflict, and configured to de-assert the first read port word line in response to a detection result of the conflict.
20. The multi-port memory of claim 19, wherein the read port wordline controller is further configured to assert a precharge signal for the first read port in response to the lack of detection of the conflict, and wherein the first read port is further configured to float the first read port bitline in response to assertion of the precharge signal.
21. The multi-port memory of claim 19, further comprising:
a sense amplifier configured to perform differential reading through the write port in response to the write port address pointing to the write port.
22. The multi-port memory of claim 21, further comprising:
a data driver configured to drive the pair of write port bit lines with data bits to be written to the multi-port bit cell after the differential read is completed.
23. The multi-port memory of claim 21, further comprising:
an inverter coupled to the first read port bit line; and
a multiplexer configured to select between the sense amplifier and the output of the inverter.
24. A multi-port memory, comprising:
an address comparator configured to detect a collision in response to both the read port address and the write port address pointing to the first multi-port bit cell;
a sense amplifier configured to read a first data bit from the first multi-port bit cell through a write port;
a write driver configured to write a second data bit to the first multi-port bit cell through the write port after the read of the first data bit is completed; and
a multiplexer coupled to the sense amplifier, the multiplexer configured to select the first data bit in response to a detection result of the collision.
25. The multi-port memory of claim 24, further comprising:
an inverter coupled to a read port bit line in a first read port in the first multi-port bit cell, wherein the multiplexer is further configured to select an output of the inverter in response to a lack of a detection result of the collision.
26. The multi-port memory of claim 25, further comprising:
a data latch configured to latch an output bit from the multiplexer.
27. The multi-port memory of claim 25, wherein the first multi-port bitcell comprises a second read port.
28. The multi-port memory of claim 25, further comprising:
a read port word line controller configured to assert a word line for the first read port in response to the lack of the detection of the conflict.
29. The multi-port memory of claim 28, wherein the read port word line controller is further configured to assert a precharge signal for the first read port in response to the lack of detection of the conflict.
30. The multiport memory of claim 24, wherein the address comparator is configured to be triggered to detect the collision in response to an edge of a clock signal.
CN202280014931.XA 2021-03-23 2022-03-09 High speed multiport memory supporting conflicts Pending CN116940984A (en)

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