CN112379204A - Drive port state detection circuit and method of drive circuit - Google Patents
Drive port state detection circuit and method of drive circuit Download PDFInfo
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Abstract
The invention discloses a drive port state detection circuit and a method, wherein the drive port state detection circuit comprises a drive circuit, a delay module and a sampling circuit; the sampling circuit comprises a switch tube, a sampling tube and a sampling capacitor; the switch tube is connected to the driving end of the driving circuit, a fixed delay of a driving signal is introduced between the switch tube and the driving tube by the delay module, and the switch tube is conducted in advance with fixed delay to form a capacitor series voltage division branch; the capacitor series structure comprises a sampling capacitor and a driving end parasitic capacitor of the series structure, and in a fixed time delay period, the capacitor series structure charges the sampling capacitor and the parasitic capacitor of the series structure by using a small current and samples the state of a driving port of the driving circuit. The invention samples the state of the driving port of the driving circuit, judges the working state of the driving port by judging the voltage result on the sampling capacitor, and because relatively independent sampling judgment time is introduced and the capacitor device is used for sampling, the sampling signal is stable and is not easy to be interfered, the accuracy of the detection result is greatly improved, and the judgment result is ensured to be accurate and reliable.
Description
Technical Field
The invention relates to the technical field of power electronics, in particular to a driving port state detection circuit and method of a driving circuit.
Background
For the state detection and judgment of the power tube driving port, a common detection circuit is to add a sampling resistor between a power tube driving branch and a power tube, at the moment when the power tube is turned on or turned off, the grid driving current of the power tube can generate a voltage drop on the sampling resistor, and the voltage drop is collected to be used as a sampling signal for judgment.
Disclosure of Invention
In order to solve the above technical problem, an object of the present invention is to provide a driving port status detection circuit, which includes a driving circuit, a sampling circuit and a delay module;
the driving circuit comprises a driving tube;
the sampling circuit comprises a switch tube and a capacitor series structure, the switch tube is connected into a driving port of the driving circuit, a delay module is arranged between the switch tube and the driving tube, the delay module introduces fixed delay of a driving signal, and the switch tube is conducted in advance for fixed delay time to form the capacitor series structure;
the capacitor series structure comprises a sampling capacitor of the series structure and a parasitic capacitor of a driving port, and the capacitor series structure charges the sampling capacitor and the parasitic capacitor by using a small current and samples the state of the driving end of the driving circuit within a fixed delay time.
By adopting the technical scheme, the driving tube comprises a driving tube at the driving end, the driving tube at the driving end and an input port of the driving circuit form a signal input branch udb, a signal input branch uda is led out from the signal input branch udb and is connected with the switch tube, a delay module is arranged on the signal input branch udb, and the delay module introduces the fixed delay of the driving signal.
According to the technical scheme, the driving tube comprises a driving end lower driving tube, the driving end lower driving tube and a driving port of the driving circuit form a signal input branch Idb, a delay module is arranged on the signal input branch Idb, and the delay module introduces fixed delay of the driving signal.
By adopting the technical scheme, the parasitic capacitance comprises a first parasitic capacitance and a second parasitic capacitance, the first parasitic capacitance is a driving port of the driving circuit to ground parasitic capacitance, the second parasitic capacitance is a power tube gate to ground parasitic capacitance, and the first parasitic capacitance and the second parasitic capacitance satisfy the following relationship:
Cs＝Csp+Csd；
Csp>>Csd；
Cd>Csd；
Csp>>Cd；
and Vcc Csd/(Csd + Cd) < | Vthmp2| when Csp is not present;
wherein Cs is a parasitic capacitance, Csd is a first parasitic capacitance, Csp is a second parasitic capacitance, and Cd is a sampling capacitance; vcc is the power supply; vthmp2 is the threshold turn-on voltage of the sample tube.
Technical scheme more than adopting, sampling circuit includes the sampling pipe, the drain electrode of switch tube links to each other with drive circuit's drive port, the source electrode of switch tube, the grid of sampling pipe link to each other with sampling capacitor's bottom plate three, sampling capacitor's top plate and sampling pipe's source electrode connect power Vcc.
By adopting the technical scheme, the sampling circuit comprises a current source Ibias, and the current source Ibias is introduced into the drain electrode of the sampling tube.
Another object of the present invention is to provide a method for detecting a status of a driver port, including:
introducing fixed time delay of a driving signal between the switching tube and the driving tube;
the input port of the driving circuit inputs a driving signal, and the switching tube is conducted in advance for a fixed delay time to form a capacitor series structure;
in a fixed time delay, the capacitor series structure charges the sampling capacitor and the parasitic capacitor which are connected in series by using a small current, samples the state of a driving port of the driving circuit, and outputs an indication signal of the state of the driving end at an output port of the detection circuit;
and judging the working state of the driving end of the driving circuit according to the waveform of the signal at the output end of the detection circuit.
Adopt above technical scheme, introduce the fixed time delay of drive signal between switch tube and drive tube, include:
the driving tube comprises a driving tube at a driving end, the driving tube at the driving end and an input port of a driving circuit form a signal input branch udb, a signal input branch uda is led out from the signal input branch udb and is connected with the switching tube, so that the switching tube and the driving tube at the driving end have the same waveform of driving signal input, and the signal input branch udb has the fixed time delay of the driving signal input, so that the fixed time delay of the driving signal input is provided between the switching tube and the driving tube at the driving end.
Technical scheme more than adopting, electric capacity series connection structure utilizes undercurrent to charge the sampling capacitance and the parasitic capacitance who establish ties, includes:
the switching tube is conducted in advance with fixed delay time, the sampling capacitor and the parasitic capacitor are charged by using small current, and because the second parasitic capacitor is far larger than the sampling capacitor, the voltage of a lower electrode plate node Aadj of the sampling capacitor is quickly pulled down and is stabilized at Vcd (Vcc) Cs/(Cd + Cs) along with the end of charging, wherein Vcd is the voltage drop of the sampling capacitor, Vcc is the power supply voltage, Cs is the total parasitic capacitor, and Cd is the sampling capacitor;
in the fixed time delay, because the parasitic capacitance value of the driving port is far larger than the capacitance value of the sampling capacitor, the gate-source voltage Vgsmp2 of the sampling tube is smaller than the threshold starting voltage Vthmp2 of the sampling tube, the sampling tube is conducted, and the drain current of the sampling tube is far larger than the current source Ibias, so that the drain voltage of the sampling tube is quickly raised to be close to Vcc from Gnd.
With the above technical solution, the determining the working state of the driving end of the driving circuit according to the waveform of the signal at the output end of the detection circuit includes:
firstly, judging whether an output signal and an input signal of a detection circuit are periodic pulses with the same period, if so, judging that a driving end of the driving circuit is in a normal state;
if the judgment result is negative, judging whether the waveform of the signal at the output end of the detection circuit is a high level; if the judgment result is yes, the driving end of the driving circuit is in a short-circuit state;
and if the judgment result is negative, the driving end of the driving circuit is in an open circuit state.
The invention has the beneficial effects that: the invention sets a capacitor series structure of a power supply to ground between a driving port of a driving circuit and the power supply, introduces a fixed time delay of a driving signal between a switching tube and the driving tube, charges the capacitor series structure in a micro conduction time through the control of the switching tube in the fixed time delay, samples the driving end of the driving circuit, judges the working state of the driving end of the driving circuit through judging a sampling result, and has the advantages of stable sampling signal, difficult interference, greatly improved accuracy of a detection result and ensured accuracy and reliability of the judgment result because relatively independent sampling judgment time is introduced and a capacitor device is used for sampling.
Drawings
FIG. 1 is a schematic diagram of a drive port status detection circuit of the drive circuit of the present invention.
Fig. 2 is a schematic diagram of the capacitor series configuration of the present invention.
FIG. 3 is a flow chart of a method for detecting the status of a driver port of a driver circuit according to the present invention.
FIG. 4 is a waveform diagram of each node in a normal state of the driving port of the driving circuit according to the present invention.
Fig. 5 is a schematic diagram of a capacitor series structure in which the driving port of the driving circuit of the present invention is in an open state.
Fig. 6 is a waveform diagram of each node in the open state of the driving port of the driving circuit according to the present invention.
Fig. 7 is a schematic diagram of a capacitor series structure in a short-circuited state of a driving port of the driving circuit according to the present invention.
Fig. 8 is a waveform diagram of each node in a short-circuited state of the driving port of the driving circuit according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments.
Examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are illustrative and intended to be illustrative of the invention and are not to be construed as limiting the invention.
In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
Fig. 1 is a schematic circuit structure diagram of a driving port state detection circuit of a driving circuit according to the present invention, in which input is an input port of the driving circuit, MP0 is a driving tube on the driving end, MP1 is a switching tube, MP2 is a sampling tube, MN0 is a driving tube under the driving end, delay is a delay module, Cd is a sampling capacitor, Cs is a parasitic capacitor (which refers to the parasitic capacitor of the driving end to the ground in the present invention), MOSFET is a power tube, and output is a detection signal output port of the driving port state detection circuit of the driving circuit.
Referring to fig. 1, a driving circuit of the detection circuit is composed of a driving end upper driving tube MP0 and a driving end lower driving tube MN0, and when a driving signal is input to an input port input of the driving circuit, the power tube MOSFET is turned on or off by pulling up or pulling down the driving end upper driving tube MP0 and the driving end lower driving tube MN 0.
Referring to fig. 1, a sampling circuit of the detection circuit is composed of a series connection structure of a switching tube MP1, a sampling tube MP2, a current source Ibias and a capacitor, on one hand, a signal input branch udb is formed by a driving tube MP0 at a driving end and an input port of the driving circuit, a signal input branch uda is led out of the signal input branch udb, the signal input branch uda is connected with a switching tube MP1, and a delay module delay is arranged on a signal input branch udb, and the delay module delay introduces a fixed delay td of a driving signal, so that the driving tube MP0 and the switching tube MP1 at the driving end have the same driving signal waveform, but the driving signal between the two has the fixed delay td; on the other hand, the capacitor series structure comprises a sampling capacitor Cd and a parasitic capacitor Cs, and the sampling capacitor Cd and the parasitic capacitor Cs are introduced between a power supply and a driving port of the driving circuit to form a capacitor series structure of the power supply to the ground; the sampling circuit comprises a sampling tube MP2, a power supply Vcc, a source electrode of a switch tube MP1, a grid electrode of the sampling tube MP2, and a lower polar plate of a sampling capacitor Cd, wherein an upper polar plate of the sampling capacitor Cd and a source electrode of the sampling tube MP2 are connected with the power supply Vcc, and a drain electrode of the sampling tube MP2 is connected with a current source Ibias to ensure that the output state of the circuit is stable in a detection period.
Referring to fig. 1, the driving tube includes a driving-end lower driving tube MN0, the driving-end lower driving tube MN0 and a driving port of the driving circuit form a signal input branch Idb, a delay module delay is disposed on the signal input branch Idb, and the delay module delay introduces a fixed delay td of the driving signal. The main purpose is to ensure that the driving waveform of the power tube MOSFET is completely consistent with the waveform pulse width of the input port input of the driving circuit, and the signal of the upper plate node Vdri of the parasitic capacitor Cs is translated backwards by 2 × td relative to the signal of the input port input of the driving circuit. In general, the time Tsw > > td and Csp > > Cd of the switching frequency period of the power tube MOSFET, so the limiting factor of the power tube MOSFET itself can be approximately ignored.
In design, it is required to satisfy (Vcc-Vcd) < Vthmosfet to ensure that the driving pulse width of the input port input of the driving circuit is equal to the turn-on pulse width of the power tube MOSFET, so that the on-time of the power tube MOSFET (especially when the pulse width of input is extremely narrow) is not affected by the fixed delay td, where Vthmosfet is the threshold turn-on voltage of the power tube.
And a resistor R1 and a filter capacitor C0 form a filter circuit of the detection circuit to further eliminate glitch interference.
In the design of the detection circuit, a fixed delay td of a driving signal is introduced into an input port of a driving tube MP0 on a driving end, and when a switching tube MP1 is switched on within the time of the fixed delay td (the driving tube MP0 on the driving end is switched off), a capacitor series structure of a power supply Vcc to ground Gnd is formed. Fig. 2 is a schematic diagram of a circuit structure of a capacitor series structure, where Csd is a first parasitic capacitor, Csp is a second parasitic capacitor, and Aadj is a lower plate node of a sampling capacitor Cd; vdri is the upper plate node of the parasitic capacitance Cs.
Specifically, a capacitance series structure is formed by the sampling capacitor Cd and the parasitic capacitor Cs, wherein the parasitic capacitor Cs includes a first parasitic capacitor Csd and a second parasitic capacitor Csp, the first parasitic capacitor Csd is a driving port of the driving circuit and is a parasitic capacitor to ground, the second parasitic capacitor Csp is a gate parasitic capacitor to ground of the power tube MOSFET, and the first parasitic capacitor Csd, the second parasitic capacitor Csp and the sampling capacitor Cd satisfy the following relations:
Cs＝Csp+Csd；
Csp>>Csd；
Cd>Csd；
Csp>>Cd；
and Vcc Csd/(Csd + Cd) < | Vthmp2| when Csp is not present;
wherein Vcc is the power supply; vthmp2 is the threshold turn-on voltage of the sample tube.
Referring to fig. 2, according to the inverse relationship between the capacitance drop and the capacitance capacity in the capacitor series structure, the following formula can be obtained: and | Vgsmp2| -Vcd ═ Vcc × Cs/(Cd + Cs), wherein Vgsmp2 is the gate-source voltage of the sampling tube MP2, and Vcd is the sampling capacitor voltage drop.
The resistor R0 is equivalent to the sum of the on-resistance and the voltage-dividing resistance of the switch MP1 to adjust the time constant of charging the capacitor.
Fig. 3 is a schematic flow chart of a method for detecting a state of a driving port of a driving circuit according to embodiment 2 of the present invention, which is described in detail with reference to fig. 1 and fig. 2.
Referring to fig. 3, a method for detecting a state of a driving port of a driving circuit includes the following steps:
in step S101, a fixed delay of the driving signal is introduced between the switching tube MP1 and the driving tube.
Illustratively, the driving tube MP0 on the driving end and the input port of the driving circuit form a signal input branch udb, a signal input branch uda is led out from the signal input branch udb, the signal input branch uda is connected with the switching tube MP1, so that the switching tube MP1 and the driving tube MP0 on the driving end have the same input of the driving signal, and a fixed delay of the driving signal is introduced into the signal input branch udb, so that a fixed delay of the input of the driving signal is provided between the switching tube MP1 and the driving tube MP0 on the driving end.
In step S102, a driving signal is input to the input port of the driving circuit, and the switching tube MP1 is turned on in advance by a fixed delay time to form a capacitor series structure.
In step S103, in a fixed delay time, the capacitor series structure charges the sampling capacitor Cd and the parasitic capacitor Cs connected in series by using a small current, samples the state of the driving port of the driving circuit, and outputs an indication signal of the state of the driving end at the output port output of the detection circuit.
Illustratively, the switching tube MP1 is turned on in advance by a fixed delay time, the sampling capacitor Cd and the parasitic capacitor Cs are charged by a small current, and since the second parasitic capacitor Csp is much larger than the sampling capacitor Cd, the voltage of the lower plate node Aadj of the sampling capacitor Cd is rapidly pulled down, and is stabilized at Vcd-Vcc Cs/(Cd + Cs) as the charging ends; vcd is the voltage drop on the sampling capacitor, Vcc is the power supply voltage, Cs is the parasitic capacitor, and Cd is the sampling capacitor; in the fixed time delay, because the parasitic capacitance Cs is far larger than the sampling capacitance Cd, the grid-source voltage of the sampling tube MP2 is smaller than the threshold starting voltage of the sampling tube MP2, the sampling tube is conducted, and the drain current of the sampling tube is far larger than the current source Ibias, so that the drain voltage of the sampling tube MP2 is quickly raised to be close to Vcc from Gnd; and then the output end output of the detection circuit outputs a detection signal of the driving port for a post-stage circuit to read a result.
In step S104, the operating state of the driving terminal of the driving circuit is determined according to the waveform of the signal at the output terminal of the detection circuit.
Illustratively, firstly, judging whether the output signal and the input signal are periodic pulses with the same period, if so, judging that the driving end state of the driving circuit is normal; if the judgment result is negative, judging whether the waveform of the signal at the output end of the detection circuit is a high level; if the judgment result is yes, the driving end of the driving circuit is in a short-circuit state; and if the judgment result is negative, the driving end of the driving circuit is in an open circuit state.
In summary, in the invention, the sampling capacitor Cd is introduced between the positive power supply end and the driving end of the driving circuit, the driving end is used for connecting the parasitic capacitor Cs to the ground, so as to form a capacitor series structure of the power supply to the ground, the fixed delay of the driving signal is introduced between the switching tube MP1 and the driving tube MP0 on the driving end, the switching tube MP1 is controlled to charge the capacitor series structure within a small conduction time within the fixed delay time, and the driving end of the driving circuit is sampled, and the working state of the driving end of the driving circuit is judged according to the sampling result.
The traditional drive port state detection circuit can only detect the open circuit or short circuit state of the drive port singly, and the invention can detect the open circuit and short circuit state of the drive port simultaneously, thereby obviously reducing the use limitation.
The following will specifically describe the details of the driving port state detection method of the driving circuit according to the present invention by way of example.
Example 1
An example of a normal operation state of the driving port of the driving circuit with the driving transistor MP0 at the driving end being a PMOS transistor and the power transistor MOSFET being a lower transistor is as follows, and fig. 4 is a schematic diagram of a result of the driving end of the driving circuit being a normal state.
Due to the introduction of the fixed delay td, the gate waveform of the switching tube MP1 is identical to the gate waveform of the driving tube MP0 at the driving end, but the gate waveform of the driving tube MP0 at the driving end is shifted backward by the fixed delay td with respect to the gate waveform of the switching tube MP1, as shown by the waveforms uda and udb in fig. 4.
At the beginning, the voltage of the upper plate node Vdri of the parasitic capacitor Cs is released to zero charge in advance by the driving-end lower driving tube MN0, and when the switching tube MP1 is turned on in advance for a fixed delay td time, as shown in fig. 2, the capacitor series structure starts to charge the sampling capacitor Cd and the parasitic capacitor Cs, at this time, because the gate parasitic capacitor Csp (Csp > > Cd) of the power tube MOSFET exists (the charge is zero), the voltage of the lower plate node Aadj of the sampling capacitor Cd is pulled down rapidly, and the voltage drop of the sampling capacitor is stabilized at Vcd aa Vcc × Cs/(Cd + Cs) as the charging ends, so as to form a zoomA waveform shown in fig. 4.
During the fixed delay td, the voltage of the upper plate node Vdri of the parasitic capacitor Cs is slightly raised due to the small current charging, and a Vdri waveform in the zoomB region as shown in fig. 4 is formed.
In the fixed time delay td, as Cs > > Cd, the gate-source voltage Vgsmp2 of the sampling tube MP2 is smaller than the threshold starting voltage Vthmp2 of the sampling tube MP2, the sampling tube MP2 is turned on, the drain current is much larger than the current of the current source Ibias, so that the drain voltage of the sampling tube MP2 is rapidly raised to be close to Vcc from Gnd, and the output signal of the output end output of the detection circuit jumps from zero level to high level.
When the fixed delay td time is over, the driving tube MP0 on the driving end is started, because the width-to-length ratio W/Lmp0 of the driving tube MP0 on the driving end is far greater than the width-to-length ratio W/Lmp1 of the switching tube MP1, the voltage of the parasitic capacitor Cs (the voltage of the Vdri node) is quickly pulled up to Vcc, at this time, the MOSFET of the power tube is started, the voltage of the lower plate node Aaddj of the sampling capacitor Cd is raised to Vcc along with the voltage of the upper plate node Vdri of the parasitic capacitor Cs, two ends of the sampling capacitor Cd are equivalently short-circuited, the gate source voltage Vgsmp2 of the sampling tube MP2 is changed into 0 and is turned off, the drain voltage of the sampling tube MP2 is pulled down to 0 by the current source Ibias, and at this time, the signal of the output end output of the port; when the upper half driving period is finished, the switch tube MP1 is finished with a fixed delay td in advance, at this time, there is no current release path at the node Aadj, the voltage of the node Aadj of the lower plate of the sampling capacitor Cd is stably latched at Vcc, at this time, the gate-source voltage Vgsmp2 of the sampling tube MP2 is 0V, and the sampling tube MP2 is kept turned off.
In summary, in the above, for the signal change of each node in one detection period of the detection circuit, in the process from the start to the end of the fixed time delay td, the output terminal of the state detection circuit of the driving port of the driving circuit generates a periodic pulse signal with the same period as the input terminal of the driving circuit.
Example 2
An example of the driving terminal of the driving circuit with the driving transistor MP0 as a PMOS transistor and the power transistor MOSFET as a lower transistor being in an open state is as follows, and fig. 6 is a schematic diagram of the driving terminal of the driving circuit being in an open state.
When the driving port of the driving circuit is opened, the gate of the power tube MOSFET is disconnected from the driving port of the driving-end upper driving tube MP0 and the driving-end lower driving tube MN0, and the second parasitic capacitance Csp does not exist.
At the beginning, the voltage of the upper plate node Vdri of the parasitic capacitor Cs is released to zero charge in advance by the driving-end down driving tube MN0, and when the switching tube MP1 is turned on at a fixed delay td in advance, as shown in fig. 5, the capacitor series structure starts to charge the sampling capacitor Cd and the parasitic capacitor Cs, and at this time, because the gate parasitic capacitor Csp of the power tube MOSFET does not exist, there is a sampling capacitor voltage drop Vcd (Vcc × Cs/(Cd + Cs) ═ Vcc/(Cd + Csd), where Cd > Csd needs to be satisfied when designing, and an Aadj waveform in the zoom area shown in fig. 6 is formed.
During the fixed delay td, the voltage of the upper plate node Vdri of the parasitic capacitor Cs is rapidly raised to Vcs-Vcc Cd/(Cd + Csd) by the current charging of the switching tube MP1, thereby forming the Vdri waveform in the zoomB region as shown in fig. 6.
In the fixed time delay td, as Vcd < | Vthmp2| is ensured in the circuit design, the sampling tube MP2 can be ensured to keep the off state under the condition, the drain voltage of the sampling tube MP2 is pulled down by the current source Ibias to be continuously zero, and the obtained signal of the output port output of the driving port state detection circuit result of the driving circuit always maintains low-level output under the condition that the grid of the power tube MOSFET is open-circuited.
The waveforms of the input, output and middle nodes of the detection circuit are as shown in fig. 6, and when the driving port of the driving circuit is open, the signal of the driving port state detection circuit result output port output of the driving circuit always maintains the low level 0V output.
Example 3
An example of a case where the driving port of the driving circuit with the driving transistor MP0 at the driving end being a PMOS transistor and the power transistor MOSFET being a lower transistor is in a short-circuit state is as follows, and fig. 8 is a schematic diagram of a result of the driving port of the driving circuit being in a short-circuit state.
When the driving port of the driving circuit is short-circuited to GND, the gate of the power tube MOSFET and the driving ports of the driving tube MP0 on the driving end and the driving tube MN0 under the driving end are short-circuited to ground, the voltage Vdri of the node of the parasitic capacitor Cs is forcibly pulled down to GND, and at the moment, the first parasitic capacitor Csd and the second parasitic capacitor Csp are both short-circuited to ground in two ends.
In the whole driving period, the driving tube MP0 and the switching tube MP1 on the driving end are conducted, and the voltage of the node Vdri of the parasitic capacitor Cs is short-circuited to Gnd, so that the voltage of the lower electrode plate node Aadj of the sampling capacitor Cd is also pulled down to Gnd; when the switching tube MP1 is cut off at a fixed delay td ahead of time, as shown in fig. 7, there is no current path at this node, so the voltage at the bottom plate node Aadj of the sampling capacitor Cd is latched to 0V, in this case, Vgsmp2< vthmp 2; the sampling tube MP2 is continuously turned on, the drain voltage of the sampling tube MP2 is continuously pulled high, and the obtained signal of the output port output of the driving port state detection circuit result of the driving circuit always maintains high level output under the condition that the driving port of the driving circuit is short-circuited.
The waveforms of the input, output and middle nodes of the detection circuit are as shown in fig. 8, and when the driving port of the driving circuit is short-circuited, the signal of the driving port state detection circuit result output port output of the driving circuit always maintains the high-level Vcc output.
The above-mentioned embodiments are merely preferred embodiments for fully illustrating the present invention, and the scope of the present invention is not limited thereto. The equivalent substitution or change made by the technical personnel in the technical field on the basis of the invention is all within the protection scope of the invention. The protection scope of the invention is subject to the claims.
Claims (10)
1. A drive port status detection circuit characterized in that: the circuit comprises a driving circuit, a sampling circuit and a time delay module;
the driving circuit comprises a driving tube;
the sampling circuit comprises a switch tube and a capacitor series structure, the switch tube is connected into a driving port of the driving circuit, a delay module is arranged between the switch tube and the driving tube, the delay module introduces fixed delay of a driving signal, and the switch tube is conducted in advance for fixed delay time to form the capacitor series structure;
the capacitor series structure comprises a sampling capacitor of the series structure and a parasitic capacitor of a driving port, and the capacitor series structure charges the sampling capacitor and the parasitic capacitor by using a small current and samples the state of the driving end of the driving circuit within a fixed delay time.
2. The drive port status detection circuit according to claim 1, characterized in that: the driving tube comprises a driving tube at a driving end, the driving tube at the driving end and an input port of a driving circuit form a signal input branch udb, a signal input branch uda is led out from the signal input branch udb and is connected with a switch tube, a delay module is arranged on the signal input branch udb, and the delay module introduces fixed delay of a driving signal.
3. The drive port status detection circuit according to claim 2, characterized in that: the driving tube comprises a driving end lower driving tube, the driving end lower driving tube and a driving port of the driving circuit form a signal input branch Idb, a delay module is arranged on the signal input branch Idb, and the delay module introduces fixed delay of a driving signal.
4. The drive port status detection circuit according to claim 1, characterized in that: the parasitic capacitance comprises a first parasitic capacitance and a second parasitic capacitance, the first parasitic capacitance is a driving port of the driving circuit and is a parasitic capacitance to the ground, the second parasitic capacitance is a parasitic capacitance to the ground of a grid electrode of the power tube, and the first parasitic capacitance and the second parasitic capacitance satisfy the following relations:
Cs＝Csp+Csd；
Csp>>Csd；
Cd>Csd；
Csp>>Cd；
and Vcc Csd/(Csd + Cd) < | Vthmp2| when Csp is not present;
wherein Cs is a parasitic capacitance, Csd is a first parasitic capacitance, Csp is a second parasitic capacitance, and Cd is a sampling capacitance; vcc is the power supply; vthmp2 is the threshold turn-on voltage of the sample tube.
5. The drive port status detection circuit according to claim 1, characterized in that: the sampling circuit comprises a sampling tube, the drain electrode of the switch tube is connected with the drive port of the drive circuit, the source electrode of the switch tube, the grid electrode of the sampling tube are connected with the lower polar plate of the sampling capacitor, and the upper polar plate of the sampling capacitor and the source electrode of the sampling tube are connected with a power supply Vcc.
6. The drive port status detection circuit according to claim 5, characterized in that: the sampling circuit comprises a current source Ibias, and the current source Ibias is introduced into the drain electrode of the sampling tube.
7. A method for detecting a state of a drive port, comprising:
introducing fixed time delay of a driving signal between the switching tube and the driving tube;
the input port of the driving circuit inputs a driving signal, and the switching tube is conducted in advance for a fixed delay time to form a capacitor series structure;
in a fixed time delay, the capacitor series structure charges the sampling capacitor and the parasitic capacitor which are connected in series by using a small current, samples the state of a driving port of the driving circuit, and outputs an indication signal of the state of the driving end at an output port of the detection circuit;
and judging the working state of the driving end of the driving circuit according to the waveform of the signal at the output end of the detection circuit.
8. The drive port status detection method of claim 7, wherein: the fixed time delay of introducing the driving signal between the switching tube and the driving tube comprises the following steps:
the driving tube comprises a driving tube at a driving end, the driving tube at the driving end and an input port of a driving circuit form a signal input branch udb, a signal input branch uda is led out from the signal input branch udb and is connected with the switching tube, so that the switching tube and the driving tube at the driving end have the same waveform of driving signal input, and the signal input branch udb has the fixed time delay of the driving signal input, so that the fixed time delay of the driving signal input is provided between the switching tube and the driving tube at the driving end.
9. The drive port status detection method of claim 7, wherein: the capacitor series structure charges the sampling capacitor and the parasitic capacitor which are connected in series by using a small current, and comprises:
the switching tube is conducted in advance with fixed delay time, the sampling capacitor and the parasitic capacitor are charged by using small current, and because the second parasitic capacitor is far larger than the sampling capacitor, the voltage of the lower plate node of the sampling capacitor is quickly pulled down and is stabilized at Vcd (Vcc Cs/(Cd + Cs) along with the end of charging, wherein Vcd is the voltage drop of the sampling capacitor, Vcc is the power supply voltage, Cs is the parasitic capacitor, and Cd is the sampling capacitor;
in the fixed time delay, because the parasitic capacitance value of the driving port is far larger than the capacitance value of the sampling capacitor, the gate-source voltage Vgsmp2 of the sampling tube is smaller than the threshold starting voltage Vthmp2 of the sampling tube, the sampling tube is conducted, and the drain current of the sampling tube is far larger than the current source Ibias, so that the drain voltage of the sampling tube is quickly raised to be close to Vcc from Gnd.
10. The drive port status detection method of claim 7, wherein: the judging the working state of the driving end of the driving circuit according to the waveform of the signal at the output end of the detection circuit comprises the following steps:
firstly, judging whether an output signal and an input signal of a detection circuit are periodic pulses with the same period, if so, judging that a driving end of the driving circuit is in a normal state;
if the judgment result is negative, judging whether the waveform of the signal at the output end of the detection circuit is a high level; if the judgment result is yes, the driving end of the driving circuit is in a short-circuit state;
and if the judgment result is negative, the driving end of the driving circuit is in an open circuit state.
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