CN112379204B - Driving port state detection circuit and method of driving circuit - Google Patents
Driving port state detection circuit and method of driving circuit Download PDFInfo
- Publication number
- CN112379204B CN112379204B CN202011295445.9A CN202011295445A CN112379204B CN 112379204 B CN112379204 B CN 112379204B CN 202011295445 A CN202011295445 A CN 202011295445A CN 112379204 B CN112379204 B CN 112379204B
- Authority
- CN
- China
- Prior art keywords
- driving
- tube
- sampling
- capacitor
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000001514 detection method Methods 0.000 title claims abstract description 52
- 238000000034 method Methods 0.000 title claims description 13
- 239000003990 capacitor Substances 0.000 claims abstract description 141
- 238000005070 sampling Methods 0.000 claims abstract description 123
- 230000003071 parasitic effect Effects 0.000 claims abstract description 82
- 230000000737 periodic effect Effects 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 12
- 101100455063 Caenorhabditis elegans lmp-1 gene Proteins 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
Abstract
The invention discloses a driving port state detection circuit and a driving port state detection method, wherein the driving port state detection circuit comprises a driving circuit, a delay module and a sampling circuit; the sampling circuit comprises a switching tube, a sampling tube and a sampling capacitor; the switch tube is connected to the driving end of the driving circuit, fixed delay of a driving signal is introduced between the switch tube and the driving tube by the delay module, and the switch tube is conducted in advance with fixed delay to form a capacitive series voltage dividing branch; the capacitor serial structure comprises a sampling capacitor and a driving end parasitic capacitor of the serial structure, and the sampling capacitor and the parasitic capacitor of the serial structure are charged by the capacitor serial structure by utilizing small current in the time of fixed delay, and the driving port state of the driving circuit is sampled. The invention samples the state of the driving port of the driving circuit, judges the working state of the driving port by judging the voltage result on the sampling capacitor, and because the relatively independent sampling judgment time is introduced and the capacitor device is used for sampling, the sampling signal is stable and is not easy to interfere, the accuracy of the detection result is greatly improved, and the accuracy and reliability of the judgment result are ensured.
Description
Technical Field
The present invention relates to the field of power electronics, and in particular, to a driving port state detection circuit and method for a driving circuit.
Background
For state detection and judgment of a power tube driving port, a sampling resistor is added between a power tube driving branch and a power tube in a common detection circuit, voltage drop is generated on the sampling resistor by power tube grid driving current at the moment of opening or closing the power tube, and the voltage drop is collected as a sampling signal for judgment, but the sampling signal is short in time, easy to interfere, and has the problems of inaccurate state detection result and large use limitation due to jitter and the like.
Disclosure of Invention
In order to solve the above technical problems, an object of the present invention is to provide a driving port state detection circuit, which includes a driving circuit, a sampling circuit and a delay module;
the driving circuit comprises a driving tube;
the sampling circuit comprises a switching tube and a capacitor series structure, the switching tube is connected into a driving port of the driving circuit, a delay module is arranged between the switching tube and the driving tube, the delay module introduces fixed delay of a driving signal, and the switching tube is conducted for a fixed delay time in advance to form the capacitor series structure;
the capacitor serial structure comprises a sampling capacitor of the serial structure and a parasitic capacitor of the driving port, and the capacitor serial structure charges the sampling capacitor and the parasitic capacitor by utilizing small current in the time of fixed delay so as to sample the driving end state of the driving circuit.
By adopting the technical scheme, the driving tube comprises a driving tube on a driving end, the driving tube on the driving end and an input port of a driving circuit form a signal input branch udb, a signal input branch uda is led out of the signal input branch udb, the signal input branch uda is connected with a switch tube, and a delay module is arranged on the signal input branch udb and introduces fixed delay of a driving signal.
By adopting the technical scheme, the driving tube comprises a driving end lower driving tube, the driving end lower driving tube and a driving port of a driving circuit form a signal input branch Idb, a delay module is arranged on the signal input branch Idb, and the delay module introduces fixed delay of a driving signal.
By adopting the technical scheme, the parasitic capacitance comprises a first parasitic capacitance and a second parasitic capacitance, the first parasitic capacitance is the parasitic capacitance of the driving port of the driving circuit to the ground, the second parasitic capacitance is the parasitic capacitance of the power tube gate to the ground, and the first parasitic capacitance and the second parasitic capacitance meet the following relation:
Cs＝Csp+Csd；
Csp>>Csd；
Cd>Csd；
Csp>>Cd；
and vcc×csd/(csd+cd) <|vthmp2| when Csp is not present;
wherein Cs is parasitic capacitance, csd is first parasitic capacitance, csp is second parasitic capacitance, and Cd is sampling capacitance; vcc is the power supply; vthmp2 is the threshold on voltage of the sampling tube.
By adopting the technical scheme, the sampling circuit comprises a sampling tube, the drain electrode of the switching tube is connected with the driving port of the driving circuit, the source electrode of the switching tube, the grid electrode of the sampling tube and the lower polar plate of the sampling capacitor are connected, and the upper polar plate of the sampling capacitor is connected with the source electrode of the sampling tube by a power supply Vcc.
By adopting the technical scheme, the sampling circuit comprises a current source Ibias, and the current source Ibias is introduced into the drain electrode of the sampling tube.
Another object of the present invention is to provide a method for detecting a status of a drive port, including:
introducing fixed delay of a driving signal between the switching tube and the driving tube;
the input port of the driving circuit inputs a driving signal, and the switching tube is conducted in advance by fixed delay time to form a capacitor series structure;
in the time of fixed delay, the capacitor serial structure charges the sampling capacitor and the parasitic capacitor which are connected in series by using small current, samples the state of a driving port of the driving circuit, and outputs an indication signal of the state of the driving end at an output port of the detection circuit;
and judging the working state of the driving end of the driving circuit according to the waveform of the signal at the output end of the detection circuit.
By adopting the technical scheme, introduce the fixed time delay of drive signal between switch tube and drive tube, include:
the driving tube comprises a driving tube on the driving end, the driving tube on the driving end and an input port of the driving circuit form a signal input branch udb, a signal input branch uda is led out on the signal input branch udb and is connected with the switching tube, so that the switching tube and the driving tube on the driving end have the same waveform of driving signal input, and the fixed delay of the driving signal is introduced on the signal input branch udb, so that the fixed delay of the driving signal input is formed between the switching tube and the driving tube on the driving end.
By adopting the technical scheme, the capacitor series structure utilizes small current to charge the sampling capacitor and the parasitic capacitor which are connected in series, and the capacitor series structure comprises:
the switching tube is conducted in advance by fixed delay time, the sampling capacitor and the parasitic capacitor are charged by utilizing small current, and as the second parasitic capacitor is far larger than the sampling capacitor, the voltage of a lower polar plate node Aadj of the sampling capacitor is rapidly pulled down and stabilized at Vcd=Vcc/(Cd+Cs) along with the end of charging, wherein Vcd is the voltage drop of the sampling capacitor, vcc is the power supply voltage, cs is the total parasitic capacitor, and Cd is the sampling capacitor;
in the time of fixed delay, because the parasitic capacitance of the drive port is far greater than the capacitance of the sampling capacitor, the gate-source voltage Vgsmp2 of the sampling tube is smaller than the threshold starting voltage Vthmp2 of the sampling tube, the sampling tube is conducted, and the drain current of the sampling tube is far greater than the current source Ibias, so that the drain voltage of the sampling tube is rapidly pulled up from Gnd to near Vcc.
By adopting the technical scheme, the working state of the driving end of the driving circuit is judged according to the waveform of the signal of the output end of the detection circuit, and the method comprises the following steps:
firstly, judging whether an output signal and an input signal of a detection circuit are periodic pulses with the same period, and if so, enabling a driving end of the driving circuit to be in a normal state;
if the judgment result is negative, judging whether the waveform of the signal at the output end of the detection circuit is high level or not; if the judgment result is yes, the driving end of the driving circuit is in a short circuit state;
if the judgment result is negative, the driving end of the driving circuit is in an open state.
The invention has the beneficial effects that: according to the invention, a capacitor series structure of the power supply to the ground is arranged between the driving port of the driving circuit and the power supply, fixed delay of a driving signal is introduced between the switching tube and the driving tube, the capacitor series structure is charged in a tiny conduction time through the control of the switching tube in the fixed delay time, the driving end of the driving circuit is sampled, and the working state of the driving end of the driving circuit is judged through judging the sampling result.
Drawings
Fig. 1 is a schematic diagram of a driving port status detection circuit of a driving circuit according to the present invention.
Fig. 2 is a schematic diagram of a capacitive series structure according to the present invention.
Fig. 3 is a flow chart of a method for detecting a status of a driving port of a driving circuit according to the present invention.
Fig. 4 is a waveform diagram of each node in a normal state of a drive port of a drive line according to the present invention.
Fig. 5 is a schematic diagram of a capacitive series structure with a driving port of a driving circuit in an open state.
Fig. 6 is a waveform diagram of each node of the drive line of the present invention in an open state.
Fig. 7 is a schematic diagram of a capacitive series structure of the driving circuit of the present invention in a short circuit state.
Fig. 8 is a waveform diagram of each node in a state where the drive port of the drive line of the present invention is short-circuited.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments.
Examples of the embodiments are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements throughout or elements having like or similar functionality. The embodiments described below by referring to the drawings are illustrative and intended to explain the present invention and should not be construed as limiting the invention.
In the present invention, unless explicitly specified and limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.
Fig. 1 is a schematic circuit diagram of a driving port state detection circuit of a driving circuit according to the present invention, in which input is an input port of the driving circuit, MP0 is an upper driving tube at the driving end, MP1 is a switching tube, MP2 is a sampling tube, MN0 is a lower driving tube at the driving end, delay is a delay module, cd is a sampling capacitor, cs is a parasitic capacitor (the parasitic capacitor of the driving end is referred to as a ground), MOSFET is a power tube, and output is a detection signal output port of the driving port state detection circuit of the driving circuit.
Referring to fig. 1, an upper driving tube MP0 at the driving end and a lower driving tube MN0 at the driving end form a driving circuit of the detection circuit, and when a driving signal is input to an input port of the driving circuit, the power tube MOSFET is turned on or turned off by pulling up or pulling down the upper driving tube MP0 at the driving end and the lower driving tube MN0 at the driving end.
Referring to fig. 1, a switching tube MP1, a sampling tube MP2, a current source Ibias and a capacitor in series structure form a sampling circuit of the detection circuit, on one hand, a driving tube MP0 on a driving end and an input port of the driving circuit form a signal input branch udb, a signal input branch uda is led out from the signal input branch udb, the signal input branch uda is connected with the switching tube MP1, and a delay module delay is arranged on the signal input branch udb, and the delay module delay introduces a fixed delay td of a driving signal, so that the driving tube MP0 on the driving end and the switching tube MP1 have the same driving signal waveform, but the driving signal between the driving tube MP0 and the switching tube MP1 has the fixed delay td; on the other hand, the capacitor series structure comprises a sampling capacitor Cd and a parasitic capacitor Cs, and the sampling capacitor Cd and the parasitic capacitor Cs are introduced between a power supply of the driving circuit and the driving port to form a capacitor series structure of the power supply to the ground; the source electrode of the switch tube MP1 is also connected with the grid electrode of the sampling tube MP2 and the lower polar plate of the sampling capacitor Cd, the upper polar plate of the sampling capacitor Cd is connected with the source electrode of the sampling tube MP2 by the power supply Vcc, and the drain electrode of the sampling tube MP2 is connected with the current source Ibias so as to ensure that the output state of the circuit is stable in the detection period.
Referring to fig. 1, the driving tube includes a driving end lower driving tube MN0, the driving end lower driving tube MN0 and a driving port of the driving circuit form a signal input branch Idb, a delay module delay is disposed on the signal input branch Idb, and the delay module delay introduces a fixed delay td of the driving signal. The main purpose is to ensure that the driving waveform of the power tube MOSFET is completely consistent with the waveform pulse width of the input port input of the driving circuit, and the signal of the upper polar plate node Vdri of the parasitic capacitor Cs is shifted backwards by 2 x td relative to the signal of the input port input of the driving circuit. Typically, the time Tsw > td and Csp > Cd of the switching frequency period of the power tube MOSFET are negligible, so that the limiting factor of the power tube MOSFET itself is approximately negligible.
In design, the (Vcc-Vcd) < Vthmosfet is required to be satisfied to ensure that the driving pulse width of the input port input of the driving circuit is equal to the on pulse width of the power tube MOSFET, so that the on time of the power tube MOSFET (especially in the case of extremely narrow pulse width of input) is not affected by the fixed delay td, where Vthmosfet is the threshold on voltage of the power tube.
And a resistor R1 and a filter capacitor C0 form a filter circuit of the detection circuit to further eliminate glitch interference.
In the design of the detection circuit, a fixed delay td of a driving signal is introduced into an input port of the driving tube MP0 on the driving end, and when the switching tube MP1 is turned on within the time of the fixed delay td (the driving tube MP0 on the driving end is turned off), a capacitor series structure of the power supply Vcc to the ground Gnd is formed. Fig. 2 is a schematic circuit structure diagram of a capacitor series structure, wherein Csd is a first parasitic capacitor, csp is a second parasitic capacitor, and Aadj is a lower plate node of a sampling capacitor Cd; vdri is the upper plate node of the parasitic capacitance Cs.
Specifically, the sampling capacitor Cd and the parasitic capacitor Cs form a capacitor series structure, wherein the parasitic capacitor Cs includes a first parasitic capacitor Csd and a second parasitic capacitor Csp, the first parasitic capacitor Csd is a parasitic capacitor of the driving port of the driving circuit to ground, the second parasitic capacitor Csp is a parasitic capacitor of the gate electrode of the power tube MOSFET to ground, and the first parasitic capacitor Csd, the second parasitic capacitor Csp and the sampling capacitor Cd satisfy the following relationships:
Cs＝Csp+Csd；
Csp>>Csd；
Cd>Csd；
Csp>>Cd；
and vcc×csd/(csd+cd) <|vthmp2| when Csp is not present;
wherein Vcc is the power supply; vthmp2 is the threshold on voltage of the sampling tube.
Referring to fig. 2, according to the inverse relation between the capacitance drop and the capacitance in the capacitor series structure, the following formula can be obtained: vgsmp2|=vcd=vcc×cs/(cd+cs), where Vgsmp2 is the gate-source voltage of the sampling tube MP2 and Vcd is the sampling capacitance voltage drop.
The resistor R0 can be equivalent to the sum of the on-resistance and the voltage-dividing resistance of the switch tube MP1 to adjust the capacitor charging time constant.
Fig. 3 is a flow chart of a method for detecting a status of a driving port of a driving circuit according to embodiment 2 of the present invention, and the method is described in detail with reference to fig. 1 and 2.
Referring to fig. 3, a method for detecting a state of a driving port of a driving circuit includes the steps of:
in step S101, a fixed delay of the drive signal is introduced between the switching tube MP1 and the drive tube.
For example, the driving end driving tube MP0 and the input port of the driving circuit form a signal input branch udb, a signal input branch uda is led out from the signal input branch udb, and the signal input branch uda is connected to the switching tube MP1, so that the switching tube MP1 and the driving end driving tube MP0 have the same input of the driving signal, and a fixed delay of the driving signal is led in from the signal input branch udb, so that a fixed delay of the driving signal input is provided between the switching tube MP1 and the driving end driving tube MP 0.
In step S102, the input port of the driving circuit inputs a driving signal, and the switching tube MP1 is turned on in advance by a fixed delay time to form a capacitor series structure.
In step S103, in a time of a fixed delay, the capacitor serial structure charges the sampling capacitor Cd and the parasitic capacitor Cs connected in series with a small current, samples the state of the driving port of the driving circuit, and outputs an indication signal of the state of the driving end at the output port output of the detection circuit.
For example, the switch tube MP1 is turned on in advance by a fixed delay time, and charges the sampling capacitor Cd and the parasitic capacitor Cs by using a small current, and since the second parasitic capacitor Csp is far greater than the sampling capacitor Cd, the voltage of the lower plate node Aadj of the sampling capacitor Cd is rapidly pulled down, and is stabilized at vcd=vcc×cs/(cd+cs) along with the end of charging; wherein Vcd is the voltage drop on the sampling capacitor, vcc is the power supply voltage, cs is the parasitic capacitor, and Cd is the sampling capacitor; in the time of fixed delay, because the parasitic capacitance Cs is far greater than the sampling capacitance Cd, the gate-source voltage of the sampling tube MP2 is smaller than the threshold starting voltage of the sampling tube MP2, the sampling tube is conducted, and the drain current of the sampling tube is far greater than the current source Ibias, so that the drain voltage of the sampling tube MP2 is rapidly pulled up to be close to Vcc from Gnd; and then the output end of the detection circuit outputs a driving port detection signal for the later-stage circuit to read the result.
In step S104, the operating state of the driving end of the driving circuit is determined according to the waveform of the signal at the output end of the detection circuit.
For example, first, whether the output signal and the input signal are periodic pulses having the same period is judged, and if the judgment result is yes, the driving end state of the driving circuit is normal; if the judgment result is negative, judging whether the waveform of the signal at the output end of the detection circuit is high level or not; if the judgment result is yes, the driving end of the driving circuit is in a short circuit state; if the judgment result is negative, the driving end of the driving circuit is in an open state.
In summary, the sampling capacitor Cd is introduced between the power supply positive and the driving end of the driving circuit, and the parasitic capacitor Cs of the driving end to the ground is utilized to form a capacitor series structure of the power supply to the ground, and the fixed delay of the driving signal is introduced between the switching tube MP1 and the driving tube MP0 on the driving end, in the fixed delay time, the switching tube MP1 is controlled to charge the capacitor series structure in a tiny conduction time, and the driving end of the driving circuit is sampled, and the working state of the driving end of the driving circuit is judged according to the sampling result.
In addition, the traditional driving port state detection circuit can only singly detect the open circuit or short circuit state of the driving port, but the invention can detect the open circuit and short circuit state of the driving port at the same time, thereby obviously reducing the use limitation.
The following will specifically describe the specific contents of a method for detecting a status of a driving port of a driving circuit according to the present invention by way of example.
Example 1
An example of a case where the driving port of the driving circuit with the upper driving tube MP0 at the driving end as the PMOS tube and the power tube MOSFET as the lower tube is in a normal working state is as follows, and fig. 4 is a schematic diagram of a result where the driving end of the driving circuit is in a normal state.
Due to the introduction of the fixed delay td, the gate waveform of the switching tube MP1 is identical to the gate waveform of the driving tube MP0 on the driving end, but the gate waveform of the driving tube MP0 on the driving end is shifted backward with respect to the gate waveform of the switching tube MP1 by the fixed delay td, as shown by the waveforms uda and udb in fig. 4.
At the beginning, the voltage of the upper plate node Vdri of the parasitic capacitor Cs is released to zero charge in advance by the driving end lower driving tube MN0, when the switching tube MP1 is turned on in advance by a fixed delay td, as shown in fig. 2, the capacitor series structure starts to charge the sampling capacitor Cd and the parasitic capacitor Cs, at this time, since the gate parasitic capacitor Csp (Csp > > Cd) of the power tube MOSFET exists (the charge is zero), the voltage of the lower plate node Aadj of the sampling capacitor Cd is rapidly pulled down, and the voltage drop of the sampling capacitor is stabilized at vcd=vcc×cs/(cd+cs) along with the end of charging, so as to form an Aadj waveform of the zoomA region as shown in fig. 4.
During the fixed time delay td, the parasitic capacitor Cs is charged with a small current, and the voltage of the upper plate node Vdri of the parasitic capacitor Cs is slightly raised, so that the Vdri waveform of the zomb area as shown in fig. 4 is formed.
In the time of the fixed delay td, because Cs > Cd, the gate-source voltage Vgsmp2 of the sampling tube MP2 is smaller than the threshold starting voltage Vthmp2 of the sampling tube MP2, the sampling tube MP2 is conducted, the drain current is far greater than the current source Ibias current, the drain voltage of the sampling tube MP2 is promoted to be rapidly pulled up from Gnd to be close to Vcc, and the output signal of the output end of the detection circuit jumps from zero level to high level.
When the fixed time delay td is finished, the driving tube MP0 on the driving end is started, the width/length ratio W/Lmp0 of the driving tube MP0 on the driving end is far greater than the width/length ratio W/Lmp1 of the switching tube MP1, the voltage of the parasitic capacitor Cs (Vdri node voltage) is rapidly pulled up to Vcc, the MOSFET on the power tube is started, the voltage of the lower plate node Aadj of the sampling capacitor Cd is lifted to Vcc along with the voltage of the upper plate node Vdri of the parasitic capacitor Cs, the two ends of the sampling capacitor Cd are equivalently shorted, the gate-source voltage Vgsmp2 of the sampling tube MP2 is changed to 0 and turned off, the drain voltage of the sampling tube MP2 is pulled down to 0 by the current source Ibias, and at the moment, the signal of the output end output of the port state detection circuit of the driving circuit jumps to be at a low level; at the end of the upper half driving period, the switching tube MP1 is advanced for a fixed delay td time to end, at this time, no current release path exists at the node Aadj, the voltage at the node Aadj of the polar plate under the sampling capacitor Cd is stably locked at Vcc, at this time, the gate-source voltage vgsmp2=0v of the sampling tube MP2, and the sampling tube MP2 remains turned off.
In summary, the above is that the signal change of each node in one detection period of the detection circuit, and in the process from the start to the end of the fixed delay td, the output end of the state detection circuit of the driving port of the driving circuit generates the periodic pulse signal with the same period as the input end of the driving circuit.
Example 2
An example of a case where the driving end of the driving circuit with the upper driving tube MP0 at the driving end as a PMOS tube and the power tube MOSFET at the driving end as a lower tube is in an open state is as follows, and fig. 6 is a schematic diagram showing a result that the driving port of the driving circuit is in an open state.
When the driving port of the driving circuit is opened, the gate of the power tube MOSFET is disconnected from the driving ports of the driving end upper driving tube MP0 and the driving end lower driving tube MN0, and the second parasitic capacitance Csp does not exist.
At the beginning, the voltage of the upper plate node Vdri of the parasitic capacitor Cs is released to zero charge in advance by the driving end lower driving tube MN0, when the switching tube MP1 is turned on in advance by a fixed delay td, as shown in fig. 5, the capacitor series structure starts to charge the sampling capacitor Cd and the parasitic capacitor Cs, at this time, since the gate parasitic capacitor Csp of the power tube MOSFET does not exist, there is a sampling capacitor voltage drop vcd=vcc×cs/(cd+cs) =vcc×csd/(cd+csd), where Cd > Csd needs to be satisfied when designing, and an Aadj waveform of the zoomA region as shown in fig. 6 is formed.
During the fixed time delay td, the voltage of the upper plate node Vdri of the parasitic capacitor Cs is rapidly raised to vcs=vcsd=vcc×cd/(cd+csd) under the current charging of the switching tube MP1, so as to form a Vdri waveform of the zomb region as shown in fig. 6.
In the time of the fixed delay td, as Vcd < |vthmp2| is guaranteed in the circuit design, the sampling tube MP2 can be guaranteed to be kept in an cut-off state under the condition, the drain voltage of the sampling tube MP2 is pulled down by the current source Ibias to be continuously zero, and at the moment, the signal of the output of the driving port state detection circuit result output of the obtained driving circuit always maintains low-level output under the condition that the grid of the power tube MOSFET is open.
The waveforms of the input, output and intermediate nodes of the detection circuit are as shown in fig. 6, and when the driving port of the driving circuit is opened, the signal of the output port of the driving port state detection circuit result output of the driving circuit always maintains low level 0V output.
Example 3
An example of a case where the driving port of the driving circuit with the driving end upper driving tube MP0 being a PMOS tube and the power tube MOSFET being a lower tube is in a short circuit state is as follows, and fig. 8 is a schematic diagram of a result of the driving port of the driving circuit being in a short circuit state.
When the driving port of the driving circuit is shorted to GND, the gate of the power transistor MOSFET is shorted to ground with the driving port of the driving end upper driving tube MP0 and the driving end lower driving tube MN0, and the node Vdri of the parasitic capacitor Cs is forcibly pulled down to GND, at this time, both ends of the first parasitic capacitor Csd and the second parasitic capacitor Csp are shorted to ground.
In the whole driving period, the driving tube MP0 and the switching tube MP1 on the driving end are conducted, and the voltage of the node Vdri of the parasitic capacitor Cs is short-circuited to Gnd, so that the voltage of the node Aadj of the lower polar plate of the sampling capacitor Cd is also pulled down to Gnd; when the switching tube MP1 is cut off by a fixed delay td in advance, as shown in fig. 7, there is no current path at this node, so the lower plate node Aadj voltage of the sampling capacitor Cd is latched to 0V, in this case, vgsmp2< vthmp2; the sampling tube MP2 is continuously conducted, the drain voltage of the sampling tube MP2 is continuously pulled up, and the obtained signal of the output port of the driving port state detection circuit result output of the driving circuit always maintains high-level output under the condition that the driving port of the driving circuit is short-circuited.
The waveforms of the input, output and intermediate nodes of the detection circuit are as shown in fig. 8, and when the driving port of the driving circuit is short-circuited, the signal output from the output port of the driving port state detection circuit of the driving circuit always maintains the high-level Vcc output.
The above-described embodiments are merely preferred embodiments for fully explaining the present invention, and the scope of the present invention is not limited thereto. Equivalent substitutions and modifications will occur to those skilled in the art based on the present invention, and are intended to be within the scope of the present invention. The protection scope of the invention is subject to the claims.
Claims (4)
1. A drive port state detection circuit is characterized in that: the sampling circuit comprises a driving circuit, a sampling circuit and a delay module;
the driving circuit comprises a driving tube;
the sampling circuit comprises a switching tube and a capacitor series structure, the switching tube is connected into a driving port of the driving circuit, a delay module is arranged between the switching tube and the driving tube, the delay module introduces fixed delay of a driving signal, and the switching tube is conducted for a fixed delay time in advance to form the capacitor series structure;
the capacitor serial structure comprises a sampling capacitor of the serial structure and a parasitic capacitor of the driving port, and the sampling capacitor and the parasitic capacitor are charged by the capacitor serial structure by utilizing small current in the time of fixed delay, so that the driving end state of the driving circuit is sampled;
the driving tube comprises a driving tube at a driving end, the driving tube at the driving end and an input port of the driving circuit form a signal input branch udb, a signal input branch uda is led out from the signal input branch udb, the signal input branch uda is connected with a switching tube, a delay module is arranged on the signal input branch udb, and the delay module introduces fixed delay of a driving signal;
the driving tube comprises a driving end lower driving tube, the driving end lower driving tube and a driving port of the driving circuit form a signal input branch Idb, a delay module is arranged on the signal input branch Idb, and the delay module introduces fixed delay of a driving signal;
the sampling circuit comprises a sampling tube, the drain electrode of the switching tube is connected with the driving port of the driving circuit, the source electrode of the switching tube and the grid electrode of the sampling tube are connected with the lower polar plate of the sampling capacitor, and the upper polar plate of the sampling capacitor and the source electrode of the sampling tube are connected with a power supply Vcc;
the sampling circuit comprises a current source Ibias, and the current source Ibias is introduced into the drain electrode of the sampling tube;
the grid electrode of the power tube is connected with the driving port of the driving circuit, and the drain electrode of the power tube is grounded.
2. The drive port state detection circuit of claim 1, wherein: the parasitic capacitance comprises a first parasitic capacitance and a second parasitic capacitance, the first parasitic capacitance is a parasitic capacitance of a driving port of the driving circuit to the ground, the second parasitic capacitance is a parasitic capacitance of a power tube gate to the ground, and the first parasitic capacitance and the second parasitic capacitance meet the following relation:
Cs=Csp+Csd；
Csp>>Csd；
Cd>Csd；
Csp>>Cd；
and vcc×csd/(csd+cd) <|vthmp2| when Csp is not present;
wherein Cs is parasitic capacitance, csd is first parasitic capacitance, csp is second parasitic capacitance, and Cd is sampling capacitance; vcc is the power supply; vthmp2 is the threshold on voltage of the sampling tube.
3. A drive port state detection method, wherein the method is applied to the drive port state detection circuit as claimed in claim 1, the method comprising:
introducing fixed delay of a driving signal between the switching tube and the driving tube;
the input port of the driving circuit inputs a driving signal, and the switching tube is conducted in advance by fixed delay time to form a capacitor series structure;
in the time of fixed delay, the capacitor serial structure charges the sampling capacitor and the parasitic capacitor which are connected in series by using small current, samples the state of a driving port of the driving circuit, and outputs an indication signal of the state of the driving end at an output port of the detection circuit;
judging the working state of the driving end of the driving circuit according to the waveform of the signal at the output end of the detection circuit;
the fixed delay for introducing a driving signal between the switching tube and the driving tube comprises the following steps:
the driving tube comprises a driving tube on the driving end, the driving tube on the driving end and an input port of the driving circuit form a signal input branch udb, a signal input branch uda is led out from the signal input branch udb and is connected with the switching tube, so that the switching tube and the driving tube on the driving end have the input of driving signals with the same waveform, and the fixed delay of the driving signals is led in from the signal input branch udb, so that the fixed delay of the driving signal input is formed between the switching tube and the driving tube on the driving end;
the capacitor series structure charges a sampling capacitor and a parasitic capacitor connected in series by using small current, and comprises:
the switching tube is conducted in advance by fixed delay time, the sampling capacitor and the parasitic capacitor are charged by utilizing small current, and as the second parasitic capacitor is far larger than the sampling capacitor, the node voltage of the lower polar plate of the sampling capacitor is rapidly pulled down and stabilized at Vcd=Vcc/(Cd+Cs) along with the end of charging, wherein Vcd is the voltage drop of the sampling capacitor, vcc is the power supply voltage, cs is the parasitic capacitor, and Cd is the sampling capacitor;
in the time of fixed delay, because the parasitic capacitance of the drive port is far greater than the capacitance of the sampling capacitor, the gate-source voltage Vgsmp2 of the sampling tube is smaller than the threshold starting voltage Vthmp2 of the sampling tube, the sampling tube is conducted, and the drain current of the sampling tube is far greater than the current source Ibias, so that the drain voltage of the sampling tube is rapidly pulled up from Gnd to near Vcc.
4. The drive port state detection method according to claim 3, wherein: the step of judging the working state of the driving end of the driving circuit according to the waveform of the signal of the output end of the detection circuit comprises the following steps:
firstly, judging whether an output signal and an input signal of a detection circuit are periodic pulses with the same period, and if so, enabling a driving end of the driving circuit to be in a normal state;
if the judgment result is negative, judging whether the waveform of the signal at the output end of the detection circuit is high level or not; if the judgment result is yes, the driving end of the driving circuit is in a short circuit state;
if the judgment result is negative, the driving end of the driving circuit is in an open state.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011295445.9A CN112379204B (en) | 2020-11-18 | 2020-11-18 | Driving port state detection circuit and method of driving circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011295445.9A CN112379204B (en) | 2020-11-18 | 2020-11-18 | Driving port state detection circuit and method of driving circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112379204A CN112379204A (en) | 2021-02-19 |
| CN112379204B true CN112379204B (en) | 2024-03-29 |
Family
ID=74584158
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011295445.9A Active CN112379204B (en) | 2020-11-18 | 2020-11-18 | Driving port state detection circuit and method of driving circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112379204B (en) |
Citations (25)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1454318A (en) * | 2000-08-03 | 2003-11-05 | 高通股份有限公司 | System, method, and apparatus for electromagnetic compatibility-driven product design |
| CN1691506A (en) * | 2004-04-30 | 2005-11-02 | 华为技术有限公司 | Line driver and output signal controlling method thereof |
| CN101546998A (en) * | 2009-04-15 | 2009-09-30 | 东南大学 | High-precision sampling switch adopting grate source tracking technology |
| JP2009303472A (en) * | 2008-05-13 | 2009-12-24 | Fuji Electric Holdings Co Ltd | Arrangement for testing power converter |
| JP2010217043A (en) * | 2009-03-17 | 2010-09-30 | Fuji Electric Holdings Co Ltd | Apparatus for testing power conversion apparatus |
| CN102081482A (en) * | 2009-11-27 | 2011-06-01 | 索尼公司 | Sensor device, method of driving sensor element, display device and electronic unit |
| CN102735906A (en) * | 2012-07-05 | 2012-10-17 | 矽力杰半导体技术(杭州)有限公司 | Inductive current detecting circuit and LED (light emitting diode) driving circuit using inductive current detecting circuit |
| CN103095127A (en) * | 2013-01-22 | 2013-05-08 | 上海艾为电子技术有限公司 | Charge pump circuit and electronic equipment |
| CN103424609A (en) * | 2013-08-20 | 2013-12-04 | 电子科技大学 | Current sampling circuit based on sectional drive |
| CN103701306A (en) * | 2013-12-18 | 2014-04-02 | 苏州美思迪赛半导体技术有限公司 | Energy-saving driving circuit device and design method |
| JP2014085367A (en) * | 2012-10-19 | 2014-05-12 | Seiko Epson Corp | Inspection method of electro-optic device |
| CN104020377A (en) * | 2014-06-13 | 2014-09-03 | 成都芯源系统有限公司 | LED driving device, controller thereof and dimming mode detection method |
| CN104066242A (en) * | 2014-06-09 | 2014-09-24 | 浙江大学 | Control chip with detection function of fly-back-type LED constant current driver |
| CN104319983A (en) * | 2014-09-29 | 2015-01-28 | 矽力杰半导体技术(杭州)有限公司 | Source driving method and driving circuit for switch power supply, and switch power supply |
| CN205509873U (en) * | 2016-02-02 | 2016-08-24 | 苏州美思迪赛半导体技术有限公司 | Self -adaptation dynamic verification and control system |
| CN106026334A (en) * | 2016-07-27 | 2016-10-12 | 西安科技大学 | Supercapacitor three-stage charging circuit and supercapacitor quick charging method thereof |
| CN106130355A (en) * | 2016-08-12 | 2016-11-16 | 广州金升阳科技有限公司 | The transistor driving control method of push-pull converter and controller |
| CN106786401A (en) * | 2016-12-22 | 2017-05-31 | 上海灿瑞科技股份有限公司 | The anti-interference detection circuit of LED drive chip feedback pin |
| CN206401881U (en) * | 2016-12-22 | 2017-08-11 | 上海灿瑞科技股份有限公司 | The anti-interference detection circuit of LED drive chip feedback pin |
| CN107732875A (en) * | 2016-08-12 | 2018-02-23 | 通用电气公司 | Solid circuit breaker and motor driven systems |
| CN109245053A (en) * | 2018-08-30 | 2019-01-18 | 广州金升阳科技有限公司 | A kind of overload protecting circuit |
| CN109962604A (en) * | 2017-12-22 | 2019-07-02 | 华润矽威科技（上海）有限公司 | Driving circuit and zero passage detection method with zero crossing detection function |
| CN109980921A (en) * | 2017-12-27 | 2019-07-05 | 华润矽威科技（上海）有限公司 | Switch constant-current controller and switch constant-current supply driving circuit |
| CN110244813A (en) * | 2019-07-15 | 2019-09-17 | 电子科技大学 | The grid driving current charging circuit and grid drive control circuit of power device |
| CN110995013A (en) * | 2019-12-28 | 2020-04-10 | 苏州美思迪赛半导体技术有限公司 | Synchronous rectification control circuit of switching power supply |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10316901A1 (en) * | 2003-04-12 | 2004-10-28 | Roche Diagnostics Gmbh | Control system and control method for checking the function of LCD displays |
| US7173590B2 (en) * | 2004-06-02 | 2007-02-06 | Sony Corporation | Pixel circuit, active matrix apparatus and display apparatus |
| JP6464752B2 (en) * | 2015-01-09 | 2019-02-06 | 株式会社デンソー | Leakage determination device |
| CN110945637A (en) * | 2017-06-20 | 2020-03-31 | 特索罗科技有限公司 | Light Emitting Diode (LED) testing apparatus and method of manufacture |
-
2020
- 2020-11-18 CN CN202011295445.9A patent/CN112379204B/en active Active
Patent Citations (26)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1454318A (en) * | 2000-08-03 | 2003-11-05 | 高通股份有限公司 | System, method, and apparatus for electromagnetic compatibility-driven product design |
| CN1691506A (en) * | 2004-04-30 | 2005-11-02 | 华为技术有限公司 | Line driver and output signal controlling method thereof |
| JP2009303472A (en) * | 2008-05-13 | 2009-12-24 | Fuji Electric Holdings Co Ltd | Arrangement for testing power converter |
| JP2010217043A (en) * | 2009-03-17 | 2010-09-30 | Fuji Electric Holdings Co Ltd | Apparatus for testing power conversion apparatus |
| CN101546998A (en) * | 2009-04-15 | 2009-09-30 | 东南大学 | High-precision sampling switch adopting grate source tracking technology |
| CN102081482A (en) * | 2009-11-27 | 2011-06-01 | 索尼公司 | Sensor device, method of driving sensor element, display device and electronic unit |
| CN102735906A (en) * | 2012-07-05 | 2012-10-17 | 矽力杰半导体技术(杭州)有限公司 | Inductive current detecting circuit and LED (light emitting diode) driving circuit using inductive current detecting circuit |
| JP2014085367A (en) * | 2012-10-19 | 2014-05-12 | Seiko Epson Corp | Inspection method of electro-optic device |
| CN103095127A (en) * | 2013-01-22 | 2013-05-08 | 上海艾为电子技术有限公司 | Charge pump circuit and electronic equipment |
| CN103424609A (en) * | 2013-08-20 | 2013-12-04 | 电子科技大学 | Current sampling circuit based on sectional drive |
| CN103701306A (en) * | 2013-12-18 | 2014-04-02 | 苏州美思迪赛半导体技术有限公司 | Energy-saving driving circuit device and design method |
| CN104066242A (en) * | 2014-06-09 | 2014-09-24 | 浙江大学 | Control chip with detection function of fly-back-type LED constant current driver |
| CN104535854A (en) * | 2014-06-13 | 2015-04-22 | 成都芯源系统有限公司 | LED driving device, controller thereof and dimming mode detection method |
| CN104020377A (en) * | 2014-06-13 | 2014-09-03 | 成都芯源系统有限公司 | LED driving device, controller thereof and dimming mode detection method |
| CN104319983A (en) * | 2014-09-29 | 2015-01-28 | 矽力杰半导体技术(杭州)有限公司 | Source driving method and driving circuit for switch power supply, and switch power supply |
| CN205509873U (en) * | 2016-02-02 | 2016-08-24 | 苏州美思迪赛半导体技术有限公司 | Self -adaptation dynamic verification and control system |
| CN106026334A (en) * | 2016-07-27 | 2016-10-12 | 西安科技大学 | Supercapacitor three-stage charging circuit and supercapacitor quick charging method thereof |
| CN107732875A (en) * | 2016-08-12 | 2018-02-23 | 通用电气公司 | Solid circuit breaker and motor driven systems |
| CN106130355A (en) * | 2016-08-12 | 2016-11-16 | 广州金升阳科技有限公司 | The transistor driving control method of push-pull converter and controller |
| CN106786401A (en) * | 2016-12-22 | 2017-05-31 | 上海灿瑞科技股份有限公司 | The anti-interference detection circuit of LED drive chip feedback pin |
| CN206401881U (en) * | 2016-12-22 | 2017-08-11 | 上海灿瑞科技股份有限公司 | The anti-interference detection circuit of LED drive chip feedback pin |
| CN109962604A (en) * | 2017-12-22 | 2019-07-02 | 华润矽威科技（上海）有限公司 | Driving circuit and zero passage detection method with zero crossing detection function |
| CN109980921A (en) * | 2017-12-27 | 2019-07-05 | 华润矽威科技（上海）有限公司 | Switch constant-current controller and switch constant-current supply driving circuit |
| CN109245053A (en) * | 2018-08-30 | 2019-01-18 | 广州金升阳科技有限公司 | A kind of overload protecting circuit |
| CN110244813A (en) * | 2019-07-15 | 2019-09-17 | 电子科技大学 | The grid driving current charging circuit and grid drive control circuit of power device |
| CN110995013A (en) * | 2019-12-28 | 2020-04-10 | 苏州美思迪赛半导体技术有限公司 | Synchronous rectification control circuit of switching power supply |
Non-Patent Citations (3)
| Title |
|---|
| 40MS/s全差分采样-保持电路的设计;何茗, 巫丛平;成都电子机械高等专科学校学报;20041230(04);全文 * |
| 一种用于电流模Buck变换器的电流采样电路;辛杨立;王卓;贾丽伟;梁华;范子威;张志文;明鑫;张波;;微电子学;20190420(02);全文 * |
| 基于开关串联和延时驱动的高压方波脉冲源研究;饶俊峰;唐正宇;;上海理工大学学报;20191215(06);全文 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112379204A (en) | 2021-02-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103166473B (en) | For detecting adaptability sample circuit and the control circuit of the demagnetization voltage of transformator | |
| US10082919B2 (en) | Semiconductor device | |
| US6967519B2 (en) | Drive circuit for a power semiconductor device | |
| US8258822B2 (en) | Driver circuit and method for reducing electromagnetic interference | |
| US9825555B2 (en) | Semiconductor control device, switching device, inverter, and control system | |
| EP2819288B1 (en) | Method of valley inductance current polarity detection in a pulse width modulated circuit with an inductive charge | |
| CN103023469B (en) | A kind of boot-strapped switch circuit | |
| CN101401307A (en) | Drive circuit and semiconductor device using the same | |
| CN103795385A (en) | Power tube drive method and circuit, and direct-current solid power controller | |
| CN107534436B (en) | Circuit and method for implementing charge/discharge switch in integrated circuit | |
| CN113014234B (en) | Overcurrent protection and floating level shift circuit applied to half-bridge high-voltage drive | |
| CN107947774B (en) | LDMOS level shift dv/dt noise suppression circuit for IGBT grid electrode driving chip | |
| CN112379204B (en) | Driving port state detection circuit and method of driving circuit | |
| CN108462152B (en) | Output protection circuit of double-phase direct-current brushless motor | |
| EP4027160A1 (en) | Universal plug status detection circuit | |
| CN110855134A (en) | Power tube driving method, driving circuit and switching circuit | |
| CN102403740B (en) | Capacitive charging current control circuit | |
| EP0829730B1 (en) | A circuit for diagnosing the state of an electric load | |
| CN105450212A (en) | Output circuit and light coupling device | |
| CN112557945A (en) | Drive port state detection circuit and method | |
| EP2627001B1 (en) | External power transistor control | |
| CN103986333B (en) | system and method for adjusting output current of power supply conversion system | |
| US20020125922A1 (en) | Semiconductor integrated circuit device | |
| CN102570794B (en) | Peak current control device and method for switching power supply | |
| CN113852353A (en) | RC oscillator and electronic equipment |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |