CN112557945A - Drive port state detection circuit and method - Google Patents
Drive port state detection circuit and method Download PDFInfo
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Abstract
The invention discloses a driving port state detection circuit and a method, wherein the driving port state detection circuit comprises a driving circuit, a sampling circuit and a time delay module; the driving circuit comprises a driving tube; the sampling circuit comprises a switch tube and a capacitor parallel structure, the switch tube is connected into a driving port of the driving circuit, a delay module is arranged between the switch tube and the driving tube, the delay module introduces fixed delay of a driving signal, and the switch tube is conducted in advance for fixed delay time to form the capacitor parallel structure; the capacitor parallel structure comprises a sampling capacitor and a parasitic capacitor which are in a parallel structure, in a fixed time delay period, the sampling capacitor is charged by charges stored on the parasitic capacitor, and the state of the driving end of the driving circuit is sampled by the voltage on the sampling capacitor. The invention introduces relatively independent sampling judgment time and uses the capacitance device for sampling, so that the sampling signal is stable and is not easy to be interfered, the accuracy of the detection result is greatly improved, and the judgment result is ensured to be accurate and reliable.
Description
Technical Field
The invention relates to the technical field of power electronics, in particular to a drive port state detection circuit and a drive port state detection method.
Background
For the state detection and judgment of the power tube driving port, a common detection circuit is to add a sampling resistor between a power tube driving branch and a power tube, at the moment when the power tube is turned on or turned off, the grid driving current of the power tube can generate a voltage drop on the sampling resistor, and the voltage drop is collected to be used as a sampling signal for judgment.
Disclosure of Invention
In order to solve the above technical problem, an object of the present invention is to provide a driving port status detection circuit, which includes a driving circuit, a sampling circuit and a delay module;
the driving circuit comprises a driving tube;
the sampling circuit comprises a switch tube and a capacitor parallel structure, the switch tube is connected into a driving port of the driving circuit, a delay module is arranged between the switch tube and the driving tube, the delay module introduces fixed delay of a driving signal, and the switch tube is conducted in advance for fixed delay time to form the capacitor parallel structure;
the capacitor parallel structure comprises a sampling capacitor and a parasitic capacitor which are in parallel structure, in a fixed time delay period, the sampling capacitor is charged by charges stored on the parasitic capacitor, and the state of the driving end of the driving circuit is sampled by the voltage on the sampling capacitor.
According to the technical scheme, the driving tube comprises a driving-end lower driving tube, the driving-end lower driving tube and an input port of a driving circuit form a signal input branch Idb, a signal input branch Ida is led out of the signal input branch Idb, the signal input branch Ida is connected with a switching tube, a delay module is arranged on the signal input branch Idb, and fixed delay of a driving signal is led in by the delay module.
Technical scheme more than adopting, the driving tube includes the driving tube on the drive end, the driving tube forms signal input branch udb with drive circuit's drive port on the drive end, is equipped with the time delay module on the signal input branch udb, the fixed time delay of drive signal is introduced to the time delay module.
By adopting the technical scheme, the parasitic capacitance comprises a first parasitic capacitance and a second parasitic capacitance, the first parasitic capacitance is a driving port of the driving circuit to ground parasitic capacitance, the second parasitic capacitance is a power tube gate to ground parasitic capacitance, and the first parasitic capacitance and the second parasitic capacitance satisfy the following relationship:
Cs＝Csp+Csd；
Csp>>Csd；
Cd>Csd；
Csp>>Cd；
and Vcc Csd/(Csd + Cd) < Vthmn2 when Csp is not present;
wherein Cs is a parasitic capacitance, Csd is a first parasitic capacitance, Csp is a second parasitic capacitance, and Cd is a sampling capacitance; vcc is the power supply; vthmn2 is the threshold turn-on voltage of the sample tube.
According to the technical scheme, the sampling circuit comprises a sampling tube, the drain electrode of the switch tube is connected with the driving port of the driving circuit, the source electrode of the switch tube, the grid electrode of the sampling tube and the upper polar plate of the sampling capacitor are connected, and the lower polar plate of the sampling capacitor and the source electrode of the sampling tube are connected with the power ground Gnd.
By adopting the technical scheme, the sampling circuit comprises a current source Ibias, and the current source Ibias is injected into the drain electrode of the sampling tube.
Another object of the present invention is to provide a method for detecting a status of a driver port, including:
introducing fixed time delay of a driving signal between the switching tube and the driving tube;
the input port of the driving circuit inputs a driving signal, and the switching tube is conducted in advance for a fixed delay time to form a capacitor parallel structure;
in the fixed time delay, the sampling capacitor is charged by the charges stored on the parasitic capacitor, the detection circuit samples the state of the driving port of the driving circuit, and an indication signal of the state of the driving end is output at the output port of the detection circuit;
and judging the working state of the driving end of the driving circuit according to the waveform of the signal at the output end of the detection circuit.
Adopt above technical scheme, introduce the fixed time delay of drive signal between switch tube and drive tube, include:
the driving tube comprises a driving end lower driving tube, a signal input branch Idb is formed by the driving end lower driving tube and an input port of a driving circuit, a signal input branch Ida is led out of the signal input branch Idb and connected with the switching tube, so that the switching tube and the driving end lower driving tube have the same waveform of driving signal input, and fixed time delay of driving signals is led in the signal input branch Idb, so that fixed time delay of driving signal input is formed between the switching tube and the driving end lower driving tube.
By adopting the technical scheme, the charging of the sampling capacitor by the charges stored on the parasitic capacitor comprises the following steps:
the parasitic capacitor is charged to the power supply voltage in the process of starting the driving tube on the driving end, and the sampling capacitor is discharged and latched to 0V at the end of the previous driving period;
the switching tube is conducted in advance with fixed delay time, the sampling capacitor is charged by the charges stored on the parasitic capacitor, the parasitic capacitor is far larger than the sampling capacitor, at the moment, Vdri is Vcd and Vcc is Cs/(Cd + Cs) > Vthmn2, wherein Vdri is an upper plate node of the parasitic capacitor, Vcd is the voltage drop of the sampling capacitor, Vcc is power voltage, Cs is the parasitic capacitor, Cd is the sampling capacitor, and Vthmn2 is threshold starting voltage of the sampling tube;
the sampling tube is turned on, and the drain voltage of the sampling tube is pulled down to 0V.
Technical scheme more than adopting, judge the operating condition of drive end of drive circuit according to the wave form of detection circuitry output end signal, include:
firstly, judging whether an output signal and an input signal of a detection circuit are periodic pulses with the same period, if so, judging that a driving end of the driving circuit is in a normal state;
if the judgment result is negative, judging whether the waveform of the output signal of the detection circuit is always high level, and if the judgment result is high, the driving end of the driving circuit is in a short-circuit state or an open-circuit state;
and if the judgment result is negative, the system state is abnormal.
The invention has the beneficial effects that: the invention sets a capacitor parallel structure of the driving port to the ground between the driving port of the driving circuit and the ground, introduces a fixed time delay of the driving signal between the switch tube and the driving tube, charges the parallel sampling capacitor by using the parasitic capacitor in a tiny conduction time through the control of the switch tube in the fixed time delay, samples the driving end of the driving circuit by the detection circuit, and judges the working state of the driving end of the driving circuit through the sampling result.
Drawings
FIG. 1 is a schematic diagram of a drive port status detection circuit of the drive circuit of the present invention.
Fig. 2 is a schematic diagram of the parallel structure of capacitors of the present invention.
FIG. 3 is a flow chart of a method for detecting the status of a driver port of a driver circuit according to the present invention.
FIG. 4 is a waveform diagram of each node in a normal state of the driving port of the driving circuit according to the present invention.
Fig. 5 is a schematic diagram of a capacitor parallel structure of the driving circuit according to the present invention in which the driving port is in an open state.
Fig. 6 is a waveform diagram of each node in the open state of the driving port of the driving circuit according to the present invention.
Fig. 7 is a schematic diagram of a capacitor parallel structure in a short-circuited state of a driving port of the driving circuit according to the present invention.
Fig. 8 is a waveform diagram of each node in a short-circuited state of the driving port of the driving circuit according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments.
Examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are illustrative and intended to be illustrative of the invention and are not to be construed as limiting the invention.
In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
Fig. 1 is a schematic circuit structure diagram of a driving port state detection circuit of a driving circuit according to the present invention, in which input is an input port of the driving circuit, MP0 is a driving tube on the driving end, MN1 is a switching tube, MN2 is a sampling tube, MN0 is a driving tube under the driving end, delay is a delay module, Cd is a sampling capacitor, Cs is a parasitic capacitor (which refers to the parasitic capacitor of the driving end to the ground in the present invention), MOSFET is a power tube, and output is a detection signal output port of the driving port state detection circuit of the driving circuit.
Referring to fig. 1, a driving circuit of the detection circuit is composed of a driving end upper driving tube MP0 and a driving end lower driving tube MN0, the driving circuit is connected to the power tube MOSFET, and when a driving signal is input to an input port input of the driving circuit, the power tube MOSFET is turned on or off by pulling up or down the driving end upper driving tube MP0 and the driving end lower driving tube MN 0.
As shown in fig. 1, the switching tube MN1, the sampling tube MN2, the current source Ibias and the capacitor are connected in parallel to form a sampling circuit of the detection circuit, on one hand, the lower driving tube MN0 is driven to form a signal input branch Idb with an input port of the driving circuit, the signal input branch Ida is led out from the signal input branch Idb, the signal input branch Ida is connected with the switching tube MN1, and a delay module delay is arranged on the signal input branch Idb, and the delay module delay introduces a fixed delay td of the driving signal, so that the lower driving tube MN0 and the switching tube MN1 are driven to have the same driving signal waveform, but the driving signal between the lower driving tube MN0 and the switching tube MN1 has the fixed delay td; on the other hand, the capacitance parallel structure comprises a sampling capacitance Cd and a parasitic capacitance Cs, and the sampling capacitance Cd and the parasitic capacitance Cs are introduced between the driving port of the driving circuit and the ground to form a capacitance parallel structure of the driving port to the ground; the source electrode of the switch tube MN1, the grid electrode of the sampling tube MN2 and the upper polar plate of the sampling capacitor Cd are connected, the lower polar plate of the sampling capacitor Cd and the source electrode of the sampling tube MN2 are connected with a power ground Gnd, and the drain electrode of the sampling tube MN2 is connected with a current source Ibias, so that the output state of the circuit in a detection period is stable.
Referring to fig. 1, the driving tube includes a driving tube MP0 at a driving end, the driving tube MP0 at the driving end and a driving port of the driving circuit form a signal input branch udb, a delay module delay is disposed on the signal input branch udb, and the delay module delay introduces a fixed delay td of the driving signal. The main purpose is to ensure that the driving waveform of the power tube MOSFET is completely consistent with the waveform pulse width of the input port input of the driving circuit, and the signal of the upper plate node Vdri of the parasitic capacitor Cs is translated backwards by 2 × td relative to the signal of the input port input of the driving circuit. In general, the time Tsw > > td and Csp > > Cd of the switching frequency period of the power tube MOSFET, so the limiting factor of the power tube MOSFET itself can be approximately ignored.
In the design, it is required to meet that Vcd is much larger than Vthmosfet within a fixed delay td to ensure that the driving pulse width of the input port input of the driving circuit is equal to the turn-on pulse width of the power tube MOSFET, so that the turn-on time of the power tube MOSFET (especially when the pulse width of input is extremely narrow) is not affected by the fixed delay td, where Vthmosfet is the threshold turn-on voltage of the power tube.
And a resistor R1 and a capacitor C0 form a filter circuit of the detection circuit to further eliminate glitch interference.
In the design of the detection circuit, a fixed time delay td of a driving signal is introduced into an input port of a driving tube MN0 under a driving end, and when a switching tube MN1 is switched on within the time of the fixed time delay td (the driving tube MP0 on the driving end is switched off), a capacitor parallel structure of the driving port to the ground Gnd is formed. Fig. 2 is a schematic circuit diagram of a capacitor parallel structure, in which Csd is a first parasitic capacitor, Csp is a second parasitic capacitor, and Aadj is an upper plate node of a sampling capacitor Cd; vdri is the upper plate node of the parasitic capacitance Cs.
Specifically, a capacitance parallel structure is formed by the sampling capacitor Cd and the parasitic capacitor Cs, wherein the parasitic capacitor Cs includes a first parasitic capacitor Csd and a second parasitic capacitor Csp, the first parasitic capacitor Csd is a driving port of the driving circuit and is a parasitic capacitor to ground, the second parasitic capacitor Csp is a gate parasitic capacitor to ground of the power tube MOSFET, and the first parasitic capacitor Csd, the second parasitic capacitor Csp and the sampling capacitor Cd satisfy the following relationships:
Cs＝Csp+Csd；
Csp>>Csd；
Cd>Csd；
Csp>>Cd；
and Vcc Csd/(Csd + Cd) < Vthmn2 when Csp is not present;
wherein Vcc is the power supply; vthmn2 is the threshold turn-on voltage of the sample tube.
Referring to fig. 2, the following formula is derived according to the parallel structure of the capacitors: vgsmn2 is Vdri Cs/(Cd + Cs) Vcc Cs/(Cd + Cs), where Vgsmn2 is the gate-source voltage of the sampling tube MN 2.
The resistor R0 can be equivalent to the sum of the on-resistance and the current-limiting resistance of the switch tube MN1 to adjust the charging time constant of the capacitor.
Fig. 3 is a schematic flow chart of a method for detecting a state of a driving port of a driving circuit according to embodiment 2 of the present invention, which is described in detail with reference to fig. 1 and fig. 2.
Referring to fig. 3, a method for detecting a state of a driving port of a driving circuit includes the following steps:
in step S101, a fixed delay of the driving signal is introduced between the switching tube MN1 and the driving tube.
Illustratively, the driving-end lower driving tube MN0 and the input port of the driving circuit form a signal input branch Idb, the signal input branch Ida is led out from the signal input branch Idb, the signal input branch Ida is connected with the switching tube MN1, and the signal input branch Idb is provided with a delay module delay, which introduces a fixed delay td of the driving signal, so that the driving-end lower driving tube MN0 and the switching tube MN1 have the same driving signal waveform, but the driving signal between the two has the fixed delay td.
In step S102, a driving signal is input to the input port of the driving circuit, and the switching tube MN1 is turned on in advance by a fixed delay time to form a capacitor parallel structure.
In step S103, in a fixed delay time, the sampling capacitor Cd is charged by the charge stored in the parasitic capacitor Cs, the detection circuit samples the state of the driving port of the driving circuit, and an indication signal of the state of the driving end is output at the output port of the detection circuit.
Illustratively, the parasitic capacitor Cs is charged to the power voltage Vcc during the process of turning on the driving transistor MP0 on the driving end, and the sampling capacitor Cd is discharged and latched to 0V at the end of the last driving period; the switching tube MN1 is turned on in advance by a fixed delay td time, the sampling capacitor Cd is charged by the charges stored in the parasitic capacitor Cs, and because the parasitic capacitor Cs is far larger than the sampling capacitor Cd, Vdri is Vcc Cs/(Cd + Cs) > Vthmn2 exists at this time, wherein Vdri is an upper plate node of the parasitic capacitor Cs, Vcd is a sampling capacitor voltage drop, Vcc is a power supply voltage, Cs is a parasitic capacitor, Cd is a sampling capacitor, and Vthmn2 is a threshold starting voltage of the sampling tube MN 2; the sampling tube MN2 is turned on, and the drain voltage of the sampling tube MN2 is pulled down to 0V; then the output of the detection circuit outputs a drive port detection signal which jumps to low level.
In step S104, the operating state of the driving terminal of the driving circuit is determined according to the waveform of the signal at the output terminal of the detection circuit.
Illustratively, firstly, judging whether the output signal and the input signal of the detection circuit are periodic pulses with the same period, if so, the driving end of the driving circuit is in a normal state; if the judgment result is negative, judging whether the waveform of the output signal of the detection circuit is always high level, and if the judgment result is high, the driving end of the driving circuit is in a short-circuit state or an open-circuit state; and if the judgment result is negative, the system state is abnormal.
In summary, in the invention, a capacitor parallel structure of a driving port to the ground is arranged between the driving port of the driving circuit and the ground, a fixed delay of a driving signal is introduced between the switching tube and the driving tube, the parasitic capacitor is used for charging the parallel sampling capacitor within a small conduction time controlled by the switching tube within the fixed delay time, the driving end of the driving circuit is sampled by the detection circuit, and the working state of the driving end of the driving circuit is judged by judging the sampling result.
The traditional drive port state detection circuit can only detect the open circuit or short circuit state of the drive port singly, and the invention can detect the open circuit and short circuit state of the drive port simultaneously, thereby obviously reducing the use limitation.
The following will specifically describe the details of the driving port state detection method of the driving circuit according to the present invention by way of example.
Example 1
An example of a normal operation state of the driving port of the driving circuit with the driving-end lower driving transistor MN0 as an NMOS transistor and the power transistor MOSFET as a lower transistor is as follows, and fig. 4 is a schematic diagram of a result of the driving-end of the driving circuit being in a normal state.
Due to the introduction of the fixed delay td, the gate waveform of the switching tube MN1 is identical to the gate waveform of the driving-end lower driving tube MV0, but the gate waveform of the driving-end lower driving tube MV0 is shifted backward by the fixed delay td relative to the gate waveform of the switching tube MN1, as shown by the waveforms of Ida and Idb in fig. 4.
In the process of starting the driving tube MP0 on the driving end, the voltage of the parasitic capacitor Cs is charged to the power supply voltage Vcc, and the voltage of the sampling capacitor Cd is discharged at the end of the last conduction period and latched to 0V; due to the existence of the fixed delay td, the switching tube MN1 is turned on in advance for the fixed delay td, so as to form a capacitor parallel structure as shown in fig. 2, and the charge stored in the parasitic capacitor Cs charges the sampling capacitor Cd and stabilizes at Vcd-Vcc Cs/(Cd + Cs) as the charging ends.
In the fixed delay td, the gate driving voltage of the power tube MOSFET is slightly reduced due to the parasitic capacitor Cs charging the sampling capacitor Cd, but the state of the power tube MOSFET is not significantly affected (as shown by zoom E in fig. 4); meanwhile, the sampling tube MN2 samples the voltage of the sampling capacitor Cd in the discharging process; because Cs > > Cd, at this time, Vdri ═ Vcd ═ Vcc × Cs/(Cd + Cs) > Vthmn2 (as shown in zoom F in fig. 4), the sampling tube MN2 is turned on, the drain voltage of the sampling tube MN2 is pulled down to 0V, and the output level of the output port of the detection circuit jumps to 0V.
After the fixed delay td time is over, the lower driving tube MN0 is driven to be opened, and the voltage of the upper electrode plate node Vdri of the parasitic capacitor Cs is rapidly pulled down to 0V; because the drive end lower drive tube MN0 and the switch tube MN1 are simultaneously conducted, the width-to-length ratio W/Lmn0 of MN0 is far greater than the width-to-length ratio W/Lmn1 of MN1, and the voltage of the upper electrode plate node Aaddj of the sampling capacitor Cd is discharged to 0V; the sampling tube MN2 is turned off, and the drain voltage of the sampling tube MN2 is pulled up to the power supply voltage Vcc by the current source Ibias; the output signal of the output port of the detection circuit jumps to high level Vcc.
In summary, in the above, for the signal change of each node in one detection period of the detection circuit, in the process from the start to the end of the fixed time delay td, the output end output of the state detection circuit of the driving port of the driving circuit generates a periodic pulse signal with the same period as the input end of the driving circuit, as shown in fig. 4 output.
Example 2
An example of the case where the driving terminal of the driving circuit with the under-driving-terminal driving transistor MN0 as an NMOS transistor and the power transistor MOSFET as a lower transistor is in an open state is as follows, and fig. 6 is a schematic diagram of a result of the driving terminal of the driving circuit being in an open state.
When the driving port of the driving circuit is open, the second parasitic capacitance Csp does not exist at this time.
In the process that the driving tube MP0 on the driving end is turned on, the voltage of the upper plate node Vdri of the parasitic capacitor Cs is charged to the power supply voltage Vcc, the switching tube MN1 is turned on in advance for a fixed delay td time, so as to form a capacitor parallel structure as shown in fig. 5, at this time, the parasitic capacitor Cs is equal to the first parasitic capacitor Csd, the first parasitic capacitor Csd charges the sampling capacitor Cd within the fixed delay td time, because Cd > d, the voltage of the upper plate node Vdri of the parasitic capacitor Cs is rapidly pulled down (as shown by zoom H in fig. 6), after the charging is finished, the gate voltage of the sampling tube MN2 is stabilized at Vcc Csd/(Csd + Cd) < Vthmn2 (as shown by zoom G in fig. 6), the sampling tube MN2 is not turned on, the drain voltage thereof is maintained at Vcc, and the obtained output port state detection circuit result of the driving circuit is open-circuited at the gate of the power tube MOSFET, the high level output is always maintained. The waveforms of the input, output and intermediate nodes of the detection circuit are shown in fig. 6.
Example 3
An example of a case where the driving port of the driving circuit with the under-driver MN0 as an NMOS transistor and the power transistor MOSFET as a lower tube is in a short-circuit state is as follows, and fig. 8 is a schematic diagram of a result of the driving port of the driving circuit being in a short-circuit state.
When the driving port of the driving circuit is short-circuited to GND, the voltage of the upper plate node Vdri of the parasitic capacitor Cs is forcibly pulled down to 0V without being affected by the driving circuit, so that the voltage of the upper plate node Vdri of the parasitic capacitor Cs and the voltage of the upper plate node Aadj of the sampling capacitor Cd are always kept at 0V regardless of whether the switching tube MN1 is turned off or on, at this time, the sampling tube MN2 is also continuously turned off, the drain voltage thereof is stabilized at Vcc under the action of the current source Ibias, and the obtained signal of the output port output of the driving port state detection circuit result of the driving circuit always maintains high-level output under the condition that the gate of the power tube is short-circuited, and meanwhile, the voltage of the upper plate node Vdri of the parasitic capacitor Cs is always maintained at 0V. The waveforms of the input, output and intermediate nodes of the detection circuit are shown in fig. 8.
The above-mentioned embodiments are merely preferred embodiments for fully illustrating the present invention, and the scope of the present invention is not limited thereto. The equivalent substitution or change made by the technical personnel in the technical field on the basis of the invention is all within the protection scope of the invention. The protection scope of the invention is subject to the claims.
Claims (10)
1. A drive port status detection circuit characterized in that: the circuit comprises a driving circuit, a sampling circuit and a time delay module;
the driving circuit comprises a driving tube;
the sampling circuit comprises a switch tube and a capacitor parallel structure, the switch tube is connected into a driving port of the driving circuit, a delay module is arranged between the switch tube and the driving tube, the delay module introduces fixed delay of a driving signal, and the switch tube is conducted in advance for fixed delay time to form the capacitor parallel structure;
the capacitor parallel structure comprises a sampling capacitor and a parasitic capacitor which are in parallel structure, in a fixed time delay period, the sampling capacitor is charged by charges stored on the parasitic capacitor, and the state of the driving end of the driving circuit is sampled by the voltage on the sampling capacitor.
2. The drive port status detection circuit according to claim 1, characterized in that: the driving tube comprises a driving end lower driving tube, the driving end lower driving tube and an input port of a driving circuit form a signal input branch Idb, a signal input branch Ida is led out of the signal input branch Idb, the signal input branch Ida is connected with a switch tube, a delay module is arranged on the signal input branch Idb, and the delay module introduces fixed delay of a driving signal.
3. The drive port status detection circuit according to claim 2, characterized in that: the driving tube comprises a driving tube at the driving end, the driving tube at the driving end and a driving port of the driving circuit form a signal input branch udb, a delay module is arranged on the signal input branch udb, and the delay module introduces the fixed delay of the driving signal.
4. The drive port status detection circuit according to claim 1, characterized in that: the parasitic capacitance comprises a first parasitic capacitance and a second parasitic capacitance, the first parasitic capacitance is a driving port of the driving circuit and is a parasitic capacitance to the ground, the second parasitic capacitance is a parasitic capacitance to the ground of a grid electrode of the power tube, and the first parasitic capacitance and the second parasitic capacitance satisfy the following relations:
Cs＝Csp+Csd；
Csp>>Csd；
Cd>Csd；
Csp>>Cd；
and Vcc Csd/(Csd + Cd) < Vthmn2 when Csp is not present;
wherein Cs is a parasitic capacitance, Csd is a first parasitic capacitance, Csp is a second parasitic capacitance, and Cd is a sampling capacitance; vcc is the power supply; vthmn2 is the threshold turn-on voltage of the sample tube.
5. The drive port status detection circuit according to claim 1, characterized in that: the sampling circuit comprises a sampling tube, the drain electrode of the switching tube is connected with the driving port of the driving circuit, the source electrode of the switching tube, the grid electrode of the sampling tube and the upper polar plate of the sampling capacitor are connected, and the lower polar plate of the sampling capacitor and the source electrode of the sampling tube are connected to the ground Gnd.
6. The drive port status detection circuit according to claim 5, characterized in that: the sampling circuit comprises a current source Ibias, and the current source Ibias is injected into the drain electrode of the sampling tube.
7. A method for detecting a state of a drive port, comprising:
introducing fixed time delay of a driving signal between the switching tube and the driving tube;
the input port of the driving circuit inputs a driving signal, and the switching tube is conducted in advance for a fixed delay time to form a capacitor parallel structure;
in the fixed time delay, the sampling capacitor is charged by the charges stored on the parasitic capacitor, the detection circuit samples the state of the driving port of the driving circuit, and an indication signal of the state of the driving end is output at the output port of the detection circuit;
and judging the working state of the driving end of the driving circuit according to the waveform of the signal at the output end of the detection circuit.
8. The drive port status detection method of claim 7, wherein: the fixed time delay of introducing the driving signal between the switching tube and the driving tube comprises the following steps:
the driving tube comprises a driving end lower driving tube, a signal input branch Idb is formed by the driving end lower driving tube and an input port of a driving circuit, a signal input branch Ida is led out of the signal input branch Idb and connected with the switching tube, so that the switching tube and the driving end lower driving tube have the same waveform of driving signal input, and the fixed time delay of the driving signal is led in the signal input branch Idb, so that the fixed time delay of the driving signal input is formed between the switching tube and the driving end lower driving tube.
9. The drive port status detection method of claim 7, wherein: the charging of the sampling capacitor by the charge stored on the parasitic capacitor comprises:
the parasitic capacitor is charged to the power supply voltage in the process of starting the driving tube on the driving end, and the sampling capacitor is discharged and latched to 0V at the end of the previous driving period;
the switching tube is conducted at a fixed delay time in advance, the sampling capacitor is charged by the charges stored on the parasitic capacitor, the parasitic capacitor is far larger than the sampling capacitor, Vdri is Vcc Cs/(Cd + Cs) > Vthmn2, wherein Vdri is an upper plate node of the parasitic capacitor, Vcd is sampling capacitor voltage, Vcc is power supply voltage, Cs is the parasitic capacitor, Cd is the sampling capacitor, and Vthmn2 is threshold opening voltage of the sampling tube.
10. The drive port status detection method of claim 7, wherein: the working state of the driving end of the driving circuit is judged according to the waveform of the signal at the output end of the detection circuit, and the working state comprises the following steps:
firstly, judging whether an output signal and an input signal of a detection circuit are periodic pulses with the same period, if so, judging that a driving end of the driving circuit is in a normal state;
if the judgment result is negative, judging whether the waveform of the output signal of the detection circuit is always high level, and if the judgment result is high, the driving end of the driving circuit is in a short-circuit state or an open-circuit state;
and if the judgment result is negative, the system state is abnormal.
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