CN112379179A - Built-in pulse width adjustable pulse sampling hold circuit - Google Patents
Built-in pulse width adjustable pulse sampling hold circuit Download PDFInfo
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- CN112379179A CN112379179A CN202011026776.2A CN202011026776A CN112379179A CN 112379179 A CN112379179 A CN 112379179A CN 202011026776 A CN202011026776 A CN 202011026776A CN 112379179 A CN112379179 A CN 112379179A
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- 238000005070 sampling Methods 0.000 title claims abstract description 20
- 239000003990 capacitor Substances 0.000 claims description 29
- 230000000630 rising effect Effects 0.000 claims description 6
- 229910044991 metal oxide Inorganic materials 0.000 abstract 1
- 150000004706 metal oxides Chemical class 0.000 abstract 1
- 239000004065 semiconductor Substances 0.000 abstract 1
- 238000000034 method Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 230000003321 amplification Effects 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000004146 energy storage Methods 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- 230000002238 attenuated effect Effects 0.000 description 1
- 230000008030 elimination Effects 0.000 description 1
- 238000003379 elimination reaction Methods 0.000 description 1
- 238000003079 width control Methods 0.000 description 1
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R29/00—Arrangements for measuring or indicating electric quantities not covered by groups G01R19/00 - G01R27/00
- G01R29/02—Measuring characteristics of individual pulses, e.g. deviation from pulse flatness, rise time or duration
- G01R29/023—Measuring pulse width
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Abstract
The invention discloses a built-in pulse sampling hold circuit with adjustable pulse width, which comprises an emitter follower, a pulse amplitude hold circuit, an emitter follower output circuit, a monostable trigger circuit and an MOS (metal oxide semiconductor) tube switch circuit, wherein the emitter follower is connected with the pulse amplitude hold circuit; the input signal pulse enters the non-inverting input end of the emitter follower, the output end of the emitter follower is respectively connected with the input end of the pulse amplitude holding circuit and the trigger end of the monostable trigger circuit, the output end of the pulse amplitude holding circuit is respectively connected with the non-inverting input end of the emitter follower output circuit and the drain electrode of the MOS tube switch circuit, the reverse output end of the monostable trigger circuit is connected with the grid electrode of the MOS tube switch circuit, and the source electrode of the MOS tube switch circuit is grounded; the output end of the emitter follower output circuit is used as amplitude holding pulse output; the pulse width of the output signal of the holding circuit is fixed, the pulse signal with the amplitude being held can be output without externally inputting a sampling pulse frequency signal, and in addition, the flat top of the output pulse amplitude voltage is not reduced.
Description
Technical Field
The invention relates to the technical field of integrated circuit design, in particular to a built-in pulse sampling hold circuit with adjustable pulse width.
Background
The pulse sampling and holding circuit is generally composed of components such as a high-speed comparator, a storage capacitor, an emitter follower output circuit, an external trigger pulse circuit and the like, the pulse width of the pulse sampling and holding circuit is determined by the pulse width of an external trigger sampling pulse, and the amplitude of the held pulse width high level voltage is reduced, namely the top of the high level is not flat. Some sample-and-hold circuits only sample peak voltage levels, and subsequent pulse amplitudes with low amplitudes cannot sample and hold, and the like. For example, patent document "a narrow pulse peak value sampling and holding circuit" (publication No. CN 108809278A) is of a type in which a peak detection module controls the pulse width, neither an analog switch nor a relay is described, the patent does not have a glitch elimination circuit, whether the output voltage is in a pulse form or not is not described, and when the input pulse is directly charged to C1, if the input peak signal source has internal resistance, the voltage held on C1 is lower than the input peak voltage by adding contact resistance and line loss of the switch K1. The output voltage has amplification function and fixed amplification factor, and when high voltage or low level is input, the numerical deviation of the output voltage is large and cannot be consistent with the numerical value of the peak voltage. A narrow pulse peak value sampling and holding circuit and a control method thereof (publication No. CN 110460322A) includes a peak value signal sampling and holding section, a comparator control section, a capacitance voltage compensation section, a follow-up output section and a DSP signal control processing section, and the peak value detection pulse width is not widened.
Disclosure of Invention
The invention aims to provide a built-in pulse sampling holding circuit with adjustable pulse width, the pulse width of an output signal of the holding circuit is fixed, a sampling pulse frequency signal is not required to be input externally, an amplitude-held pulse signal can be output, and in addition, the flat top of the output pulse amplitude voltage is not reduced.
The technical scheme adopted by the invention for solving the technical problems is as follows:
a built-in pulse width adjustable pulse sampling hold circuit comprises an emitter follower, a pulse amplitude holding circuit, an emitter follower output circuit, a monostable trigger circuit and an MOS tube switch circuit;
the input signal pulse enters the non-inverting input end of the emitter follower, the output end of the emitter follower is respectively connected with the input end of the pulse amplitude holding circuit and the trigger end of the monostable trigger circuit, the output end of the pulse amplitude holding circuit is respectively connected with the non-inverting input end of the emitter follower output circuit and the drain electrode of the MOS tube switch circuit, the reverse output end of the monostable trigger circuit is connected with the grid electrode of the MOS tube switch circuit, and the source electrode of the MOS tube switch circuit is grounded; the output end of the emitter follower output circuit is used as amplitude holding pulse output.
Furthermore, the emitter follower comprises an operational amplifier N1, a resistor R3 and a capacitor C3, the pulse amplitude holding circuit comprises a diode D1 and a capacitor C1, the emitter follower output circuit comprises an operational amplifier N2 and a resistor R1, the monostable trigger circuit comprises a monostable trigger U1, an adjustable resistor RX and an adjustable capacitor CX, and the MOS transistor switch circuit comprises a MOS transistor Q1 and a resistor R4;
resistors R3 and C3 are connected in series between an input pulse end and GND, the output end of an operational amplifier N1 is connected with the anode of a diode D1, the inverting input end of the operational amplifier N1 is connected with the cathode of a diode D1, and the input pulse end is connected with the non-inverting input end of an operational amplifier N1;
the cathode end of the diode D1 is connected with the positive end of the capacitor C1, and the non-inverting input end of the operational amplifier N2 is respectively connected with the positive end of the capacitor C1 and the drain electrode of the MOS switching tube Q1; the negative terminal of the capacitor C1 is grounded;
the output end of the operational amplifier N1 is also connected to the rising edge trigger end of the monostable flip-flop U1, an adjustable capacitor CX is connected between the C end and the RC end of the monostable flip-flop U1, and an adjustable resistor RX is connected between the RC end of the monostable flip-flop U1 and a power supply VCC;
the RESET end and the lower edge trigger end of the monostable trigger U1 are connected with a power supply together, and the reverse output end of the monostable trigger U1 is connected with the grid electrode of the MOS transistor Q1; the resistor R4 is connected between the gate and the source of the MOS transistor Q1, and the source of the MOS transistor Q1 is grounded.
The resistor R1 is connected between the inverting input terminal and the output terminal of the operational amplifier N2, and the output terminal of the operational amplifier N2 is output as an amplitude holding pulse.
The pulse width control circuit has the advantages that the rising edge of an input pulse signal is obtained through the monostable trigger circuit, the pulse width of the holding voltage is controlled through the adjustable resistor RX and the adjustable capacitor CX which are connected in a monostable trigger mode, the low leakage loop ensures that the high level of a pulse amplitude sampling holding output pulse is not attenuated, and a sampling pulse frequency signal does not need to be added.
Drawings
The invention is further illustrated with reference to the following figures and examples:
FIG. 1 is a schematic block diagram of the circuit of the present invention;
fig. 2 is a circuit schematic of the present invention.
Detailed Description
As shown in fig. 1, the present invention provides a built-in pulse sampling and holding circuit with adjustable pulse width, which includes an emitter follower 1, a pulse amplitude holding circuit 2, an emitter follower output circuit 3, a monostable trigger circuit 4 and a MOS transistor switch circuit 5;
the input signal pulse enters the non-inverting input end of the emitter follower, the output end of the emitter follower is respectively connected with the input end of the pulse amplitude holding circuit and the trigger end of the monostable trigger circuit, the output end of the pulse amplitude holding circuit is respectively connected with the non-inverting input end of the emitter follower output circuit and the drain electrode of the MOS tube switch circuit, the reverse output end of the monostable trigger circuit is connected with the grid electrode of the MOS tube switch circuit, and the source electrode of the MOS tube switch circuit is grounded; the output end of the emitter follower output circuit is used as amplitude holding pulse output.
Referring to fig. 2, a specific circuit diagram is shown in this embodiment, the emitter follower includes an operational amplifier N1, a resistor R3 and a capacitor C3, the pulse amplitude holding circuit includes a diode D1 and a capacitor C1, the emitter follower output circuit includes an operational amplifier N2 and a resistor R1, the monostable flip-flop circuit includes a monostable flip-flop U1, an adjustable resistor RX and an adjustable capacitor CX, and the MOS switch circuit includes a MOS transistor Q1 and a resistor R4.
Resistors R3 and C3 are connected in series between the input pulse end and GND, the output end of the operational amplifier N1 is connected with the anode of the diode D1, the inverting input end of the operational amplifier N1 is connected with the cathode of the diode D1, and the input pulse end is connected with the non-inverting input end of the operational amplifier N1.
The cathode end of the diode D1 is connected with the positive end of the capacitor C1, and the non-inverting input end of the operational amplifier N2 is respectively connected with the positive end of the capacitor C1 and the drain electrode of the MOS switching tube Q1; the negative terminal of the capacitor C1 is connected to ground.
The output end of the operational amplifier N1 is also connected to the rising edge trigger end of the monostable flip-flop U1, an adjustable capacitor CX is connected between the C end and the RC end of the monostable flip-flop U1, and an adjustable resistor RX is connected between the RC end of the monostable flip-flop U1 and a power supply VCC.
The RESET end and the lower edge trigger end of the monostable trigger U1 are connected with a power supply together, and the reverse output end of the monostable trigger U1 is connected with the grid electrode of the MOS transistor Q1; the resistor R4 is connected between the gate and the source of the MOS transistor Q1, and the source of the MOS transistor Q1 is grounded.
The resistor R1 is connected between the inverting input terminal and the output terminal of the operational amplifier N2, and the output terminal of the operational amplifier N2 is output as an amplitude holding pulse.
The resistors R3 and C3 play a role in eliminating spike burrs of input signal pulses, the input signal pulses enter the operational amplifier N1, are sent into the high-stability capacitor C1 through the diode D1 to keep the voltage amplitude of the input signal pulses, and finally the DC voltage value Vo kept by the C1 is output through the operational amplifier N2. The output end of the operational amplifier N1 is connected to the rising edge trigger input end + TR of the monostable flip-flop U1, when the rising edge of the input signal pulse comes, the inverting output end of the monostable flip-flop U1 outputs a negative pulse with the pulse width determined by the charging time of the adjustable resistor RX and the adjustable capacitor CX, and the negative pulse controls the MOS tube Q1 to be turned off, so that the value of the holding voltage on the capacitor C1 is not reduced. The drain of the MOS transistor Q1 is connected with the positive end of the energy storage capacitor C1, after the negative pulse is finished, the inverted output end of the monostable trigger U1 outputs high level, the MOS transistor Q1 is controlled to be turned on, the voltage on the energy storage capacitor C1 is rapidly discharged to GND, and the Vo of the operational amplifier N2 outputs low level. The width of the Vo output pulse signal is determined by the adjustable resistor RX and the adjustable capacitor CX, the pulse amplitude sampling and holding function is realized, and the Vo output pulse signal holding width is built-in and adjustable. The circuit working conditions are as follows: the output pulse width is greater than the input pulse width; while the output pulse width is less than the input pulse period. Vo output pulse width calculation TW = (RX x CX)/2, where CX ≧ 10 nF.
The foregoing is merely a preferred embodiment of the invention and is not intended to limit the invention in any manner; those skilled in the art can make numerous possible variations and modifications to the present teachings, or modify equivalent embodiments to equivalent variations, without departing from the scope of the present teachings, using the methods and techniques disclosed above. Therefore, any simple modification, equivalent replacement, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the scope of the protection of the technical solution of the present invention.
Claims (2)
1. A built-in pulse sampling hold circuit with adjustable pulse width is characterized by comprising an emitter follower, a pulse amplitude holding circuit, an emitter follower output circuit, a monostable trigger circuit and an MOS tube switch circuit;
the input signal pulse enters the non-inverting input end of the emitter follower, the output end of the emitter follower is respectively connected with the input end of the pulse amplitude holding circuit and the trigger end of the monostable trigger circuit, the output end of the pulse amplitude holding circuit is respectively connected with the non-inverting input end of the emitter follower output circuit and the drain electrode of the MOS tube switch circuit, the reverse output end of the monostable trigger circuit is connected with the grid electrode of the MOS tube switch circuit, and the source electrode of the MOS tube switch circuit is grounded; the output end of the emitter follower output circuit is used as amplitude holding pulse output.
2. The built-in pulse width adjustable pulse sampling and holding circuit of claim 1,
the emitter follower comprises an operational amplifier N1, a resistor R3 and a capacitor C3, the pulse amplitude holding circuit comprises a diode D1 and a capacitor C1, the emitter follower output circuit comprises an operational amplifier N2 and a resistor R1, the monostable trigger circuit comprises a monostable trigger U1, an adjustable resistor RX and an adjustable capacitor CX, and the MOS tube switch circuit comprises an MOS tube Q1 and a resistor R4;
resistors R3 and C3 are connected in series between an input pulse end and GND, the output end of an operational amplifier N1 is connected with the anode of a diode D1, the inverting input end of the operational amplifier N1 is connected with the cathode of a diode D1, and the input pulse end is connected with the non-inverting input end of an operational amplifier N1;
the cathode end of the diode D1 is connected with the positive end of the capacitor C1, and the non-inverting input end of the operational amplifier N2 is respectively connected with the positive end of the capacitor C1 and the drain electrode of the MOS switching tube Q1; the negative terminal of the capacitor C1 is grounded;
the output end of the operational amplifier N1 is also connected to the rising edge trigger end of the monostable flip-flop U1, an adjustable capacitor CX is connected between the C end and the RC end of the monostable flip-flop U1, and an adjustable resistor RX is connected between the RC end of the monostable flip-flop U1 and a power supply VCC;
the RESET end and the lower edge trigger end of the monostable trigger U1 are connected with a power supply together, and the reverse output end of the monostable trigger U1 is connected with the grid electrode of the MOS transistor Q1; the resistor R4 is connected between the grid and the source of the MOS transistor Q1, and the source of the MOS transistor Q1 is grounded;
the resistor R1 is connected between the inverting input terminal and the output terminal of the operational amplifier N2, and the output terminal of the operational amplifier N2 is output as an amplitude holding pulse.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011026776.2A CN112379179B (en) | 2020-09-25 | 2020-09-25 | Pulse sampling hold circuit with adjustable built-in pulse width |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011026776.2A CN112379179B (en) | 2020-09-25 | 2020-09-25 | Pulse sampling hold circuit with adjustable built-in pulse width |
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| CN112379179A true CN112379179A (en) | 2021-02-19 |
| CN112379179B CN112379179B (en) | 2024-01-30 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113866481A (en) * | 2021-09-28 | 2021-12-31 | 上海电气泰雷兹交通自动化系统有限公司 | Voltage acquisition circuit automatically adapting to wide voltage input range |
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2020
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| JP2004247834A (en) * | 2003-02-12 | 2004-09-02 | Denso Corp | Over-current detection circuit of single phase load subjected to pwm voltage control by mos transistor |
| CN101795127A (en) * | 2010-02-04 | 2010-08-04 | 西安理工大学 | High-voltage square-wave pulse generator and method for generating high-voltage square-wave pulse |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113866481A (en) * | 2021-09-28 | 2021-12-31 | 上海电气泰雷兹交通自动化系统有限公司 | Voltage acquisition circuit automatically adapting to wide voltage input range |
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| CN112379179B (en) | 2024-01-30 |
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