CN220896541U - Compatible high pulse and low pulse power management enable circuit - Google Patents
Compatible high pulse and low pulse power management enable circuit Download PDFInfo
- Publication number
- CN220896541U CN220896541U CN202322851152.XU CN202322851152U CN220896541U CN 220896541 U CN220896541 U CN 220896541U CN 202322851152 U CN202322851152 U CN 202322851152U CN 220896541 U CN220896541 U CN 220896541U
- Authority
- CN
- China
- Prior art keywords
- pulse
- exclusive
- power
- gate
- resistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000003990 capacitor Substances 0.000 claims description 16
- 238000000034 method Methods 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Landscapes
- Power Conversion In General (AREA)
Abstract
The utility model discloses a compatible high-pulse and low-pulse power management enabling circuit, which comprises a power input end, a power output end, a power switch circuit, a control switch circuit, an exclusive-OR gate circuit and a singlechip, wherein the input end of the exclusive-OR gate circuit is used for acquiring external pulse signals, the output end of the exclusive-OR gate circuit is connected with the input end of the control switch circuit, and the output end of the control switch circuit is connected with the control end of the power switch circuit and is used for controlling the power switch circuit to be electrified; the utility model is provided with the exclusive or gate, the input end of the exclusive or gate can input high pulse or low pulse signals, the high pulse or low pulse is changed into the power management enabling source through the exclusive or gate, the triode controls the P-type MOS tube to be conducted, so that the power supply supplies power to the singlechip, the high pulse or low pulse can be simultaneously considered, and the single port can be connected, thereby saving the cost.
Description
Technical Field
The utility model relates to the technical field of power management enabling circuits, in particular to a high-pulse and low-pulse power management enabling circuit compatible.
Background
The current mainstream wake-up singlechip mode comprises wake-up by a wake-up source, and the other is to perform auxiliary power supply management, wherein the auxiliary power supply management needs specific level of an external wake-up source to conduct a power supply management circuit, and generally needs to build circuits according to high pulse and low pulse respectively, so that the production cost is increased.
Disclosure of utility model
Accordingly, it is a primary objective of the present utility model to provide a high-pulse and low-pulse power management enabling circuit.
In order to achieve the above purpose, the technical scheme of the utility model is realized as follows:
The embodiment of the utility model provides a compatible high-pulse and low-pulse power management enabling circuit, which comprises a power input end, a power output end, a power switch circuit, a control switch circuit, an exclusive-OR gate circuit and a singlechip, wherein the input end of the exclusive-OR gate circuit is used for acquiring a wake-up pulse signal, the output end of the exclusive-OR gate circuit is connected with the input end of the control switch circuit, the output end of the control switch circuit is connected with the control end of the power switch circuit and used for controlling the power switch circuit to be electrified, the power input end is connected with the current input end of the power switch circuit, the input end of the power output end is connected with the current output end of the power switch circuit, and the output end of the power output end is connected with the power input end of the singlechip.
In the above scheme, the power switch circuit includes P type MOS pipe, first condenser, second resistor, third resistor, fifth diode, the positive pole of fifth diode is connected with the power input, the negative pole of fifth diode is connected with the first end of third resistor and the source electrode of P type MOS pipe respectively, the second end of third resistor is connected with the first end of second resistor and the grid of P type MOS pipe respectively, the drain electrode of P type MOS pipe is connected with the first end and the power output of first condenser respectively, the second end ground connection of first condenser.
In the above scheme, the control switch circuit comprises a triode, a collector of the triode is connected with the second end of the second resistor, and an emitter of the triode is grounded.
In the above scheme, the exclusive-or gate circuit includes an exclusive-or gate, a fourth resistor, a fifth resistor, a second capacitor, a fourth diode, and a wake-up pulse signal terminal, a first end of the fifth resistor is connected with a base electrode of the triode, a second end of the fifth resistor is connected with a negative electrode of the fourth diode, an anode of the fourth diode is connected with a Y end of the exclusive-or gate, a B end of the exclusive-or gate is connected with a first end of the fourth resistor and the wake-up pulse signal terminal, a second end of the fourth resistor is connected with an a end of the exclusive-or gate and a first end of the second capacitor, and a second end of the second capacitor is grounded.
Compared with the prior art, the utility model has the beneficial effects that:
The utility model is provided with the exclusive-OR gate, the input end of the exclusive-OR gate can input high pulse or low pulse signals, the high pulse or low pulse is changed into the power management enabling source through the exclusive-OR gate, the triode controls the conduction of the P-type MOS tube, so that the power supply supplies power to the singlechip, the high pulse or low pulse can be simultaneously considered, the single port can be connected, and the cost is saved .
Drawings
The accompanying drawings, which are included to provide a further understanding of the utility model and are incorporated in and constitute a part of this specification, illustrate embodiments of the utility model and together with the description serve to explain the utility model. In the drawings:
fig. 1 is a schematic diagram of a compatible high-pulse and low-pulse power management enabling circuit according to an embodiment of the utility model.
Detailed Description
The present utility model will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present utility model more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the utility model.
The same or similar reference numerals in the drawings of the present embodiment correspond to the same or similar components; in the description of the present utility model, it should be understood that the terms "first," "second," "third," etc. are merely for convenience in distinguishing and describing identical components, and are not intended to indicate or imply the number of components referred to, but are not to be construed as limiting the present patent, so that a person of ordinary skill in the art would understand the specific meaning of the terms as the case may be.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, article or apparatus that comprises the element.
The embodiment of the utility model provides a compatible high-pulse and low-pulse power management enabling circuit, which is shown in fig. 1 and comprises a power input end PWR_ I N, a power output end PWR_OUT, a power switch circuit, a control switch circuit, an exclusive-OR gate circuit and a singlechip, wherein the input end of the exclusive-OR gate circuit is used for acquiring a power management enabling pulse signal, the output end of the exclusive-OR gate circuit is connected with the input end of the control switch circuit, the output end of the control switch circuit is connected with the control end of the power switch circuit and is used for controlling the power switch circuit to be electrified, the input end PWR_ I N of the power supply is connected with the current input end of the power switch circuit, and the output end of the power output end PWR_OUT is connected with the power input end of the singlechip.
As shown in fig. 1, the power switch circuit includes a P-type MOS transistor Q3, a first capacitor C1, a second resistor R2, a third resistor R3, and a fifth diode D5, where an anode of the fifth diode D5 is connected to the power input terminal pwr_ I N, a cathode of the fifth diode D5 is connected to a first end of the third resistor R3 and a source of the P-type MOS transistor Q3, a second end of the third resistor R3 is connected to a first end of the second resistor R2 and a gate of the P-type MOS transistor Q3, and a drain of the P-type MOS transistor Q3 is connected to a first end of the first capacitor C1 and the power output terminal pwr_out, and a second end of the first capacitor C1 is grounded.
As shown in fig. 1, the control switch circuit includes a triode Q1, a collector of the triode Q1 is connected to the second end of the second resistor, and an emitter of the triode Q1 is grounded.
As shown in fig. 1, the exclusive-or gate circuit includes an exclusive-or gate U1, a fourth resistor R4, a fifth resistor R5, a second capacitor C2, a fourth diode D4, and an enable pulse signal terminal, a first end of the fifth resistor R5 is connected to the base of the triode Q1, a second end of the fifth resistor is connected to the cathode of the fourth diode, an anode of the fourth diode D4 is connected to the Y end of the exclusive-or gate U1, a B end of the exclusive-or gate U1 is connected to the first end of the fourth resistor R4 and the enable pulse signal terminal WEAKUP _sig_all, a second end of the fourth resistor R4 is connected to the a end of the exclusive-or gate U1 and the first end of the second capacitor C2, and a second end of the second capacitor C2 is grounded.
In the scheme, the input end of the exclusive OR gate can be input with a high pulse or low pulse signal, the high pulse or low pulse is changed into the energy source of the power management circuit through the exclusive OR gate, and the triode controls the P-type MOS tube to be conducted, so that the power supply supplies power to the singlechip.
The working principle of the utility model is as follows:
As shown in fig. 1, when the external pulse signal is changed, the end B of the exclusive or gate U1 keeps the same voltage of the pulse waveform, and the voltage is compared with the level of the second capacitor C2 connected to the end a of the exclusive or gate U1 to form a voltage difference, and the voltage difference forms a new pulse through the exclusive or gate U1, wherein the pulse is a power management enabling source, so that the base of the triode Q1 is a high pulse, the collector of the triode Q1 is controlled to be low to control the conduction of the P-type MOS transistor Q3, and the power supply is enabled to supply power to the singlechip.
In actual use, the P-type MOS transistor Q3 can also be any type of P-type transistor, and the triode Q1 can also be any type of N-type MOS transistor.
The foregoing description is only of the preferred embodiments of the present utility model, and is not intended to limit the scope of the present utility model.
Claims (4)
1. The utility model provides a compatible high pulse and low pulse power management enable circuit, its characterized in that includes power input end, power output end, switch circuit, control switch circuit, exclusive-OR gate circuit, singlechip, the input of exclusive-OR gate circuit is used for acquireing external pulse signal, the output of exclusive-OR gate circuit is connected with control switch circuit's input, control switch circuit's output is connected with power switch circuit's control end for control switch circuit is energized, power input end is connected with switch circuit's current input end, the input of power output end is connected with switch circuit's current output end, the output of power output end is connected with the power input of singlechip.
2. The compatible high-pulse and low-pulse power management enabling circuit according to claim 1, wherein the power switch circuit comprises a P-type MOS tube, a first capacitor, a second resistor, a third resistor and a fifth diode, wherein the positive electrode of the fifth diode is connected with the power input end, the negative electrode of the fifth diode is respectively connected with the first end of the third resistor and the source electrode of the P-type MOS tube, the second end of the third resistor is respectively connected with the first end of the second resistor and the gate electrode of the P-type MOS tube, the drain electrode of the P-type MOS tube is respectively connected with the first end of the first capacitor and the power output end, and the second end of the first capacitor is grounded.
3. The compatible high-pulse and low-pulse power management enabling circuit of claim 2, wherein the control switch circuit comprises a triode having a collector connected to the second terminal of the second resistor and an emitter connected to ground.
4. A compatible high-pulse and low-pulse power management enabling circuit according to claim 3 and characterized in that said exclusive-or gate circuit comprises an exclusive-or gate, a fourth resistor, a fifth resistor, a second capacitor, a fourth diode, a wake-up pulse signal terminal, a first terminal of said fifth resistor being connected to the base of the triode, a second terminal of said fifth resistor being connected to the cathode of the fourth diode, the anode of said fourth diode being connected to the Y terminal of said exclusive-or gate, the B terminal of said exclusive-or gate being connected to the first terminal of said fourth resistor and to the power management enabling pulse signal terminal, respectively, the a terminal of said fourth resistor being connected to the first terminal of said exclusive-or gate and to the first terminal of said second capacitor, respectively, the second terminal of said second capacitor being grounded.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202322851152.XU CN220896541U (en) | 2023-10-24 | 2023-10-24 | Compatible high pulse and low pulse power management enable circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202322851152.XU CN220896541U (en) | 2023-10-24 | 2023-10-24 | Compatible high pulse and low pulse power management enable circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN220896541U true CN220896541U (en) | 2024-05-03 |
Family
ID=90873692
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202322851152.XU Active CN220896541U (en) | 2023-10-24 | 2023-10-24 | Compatible high pulse and low pulse power management enable circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN220896541U (en) |
-
2023
- 2023-10-24 CN CN202322851152.XU patent/CN220896541U/en active Active
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102097923B (en) | Driving circuit with zero turn-off current and driving method thereof | |
| CN203574531U (en) | A mos transistor drive circuit based on high-frequency oscillation signals | |
| CN220896541U (en) | Compatible high pulse and low pulse power management enable circuit | |
| CN204859144U (en) | Auto -lock switch circuit | |
| CN207490898U (en) | The logic level transition device and amplifying circuit of dual power supply amplifier | |
| CN215120570U (en) | Low standby power consumption DC-DC converter | |
| CN114465331A (en) | Watch charging seat circuit without voltage drop of anode and cathode | |
| CN111600460A (en) | ORing MOSFET control circuit and power supply parallel system | |
| CN201733130U (en) | Power supply management module circuit | |
| CN212231329U (en) | ORing MOSFET control circuit and power supply parallel system | |
| CN211352561U (en) | Sound control lamp circuit | |
| CN218298799U (en) | Single-chip microcomputer power supply control circuit with zero standby power consumption | |
| CN206004528U (en) | A kind of high power booster circuit | |
| CN201153295Y (en) | Television standby detection power supply circuit | |
| CN116505888B (en) | Negative pressure protection circuit of GaN power amplifier | |
| CN220605773U (en) | Automatic code dialing circuit and voltage doubling circuit | |
| CN218213842U (en) | Key awakening circuit applied to frame circuit breaker | |
| CN109921772B (en) | Input signal holding circuit | |
| CN210183224U (en) | Ultra-wide voltage input range self-adaptive direct-current power supply circuit | |
| CN215817630U (en) | Intelligent direct-current discharge circuit | |
| CN203968002U (en) | LED self-oscillation drive circuit with output over-voltage protection function | |
| CN212210571U (en) | Dry battery power supply circuit for temperature measuring gun | |
| CN213879355U (en) | Common-negative electrode battery charging and discharging circuit | |
| CN211454407U (en) | Low-power-consumption power management circuit | |
| CN216721285U (en) | Negative voltage protection circuit of amplifier |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |