CN112367573A - Control link suitable for orthogonal architecture equipment and implementation method thereof - Google Patents
Control link suitable for orthogonal architecture equipment and implementation method thereof Download PDFInfo
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- CN112367573A CN112367573A CN202011432030.1A CN202011432030A CN112367573A CN 112367573 A CN112367573 A CN 112367573A CN 202011432030 A CN202011432030 A CN 202011432030A CN 112367573 A CN112367573 A CN 112367573A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/0001—Selecting arrangements for multiplex systems using optical switching
- H04Q11/0003—Details
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
- G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/0001—Selecting arrangements for multiplex systems using optical switching
- H04Q11/0005—Switch and router aspects
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/0001—Selecting arrangements for multiplex systems using optical switching
- H04Q11/0005—Switch and router aspects
- H04Q2011/0007—Construction
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/0001—Selecting arrangements for multiplex systems using optical switching
- H04Q11/0005—Switch and router aspects
- H04Q2011/0052—Interconnection of switches
- H04Q2011/0058—Crossbar; Matrix
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Abstract
The invention discloses a control link suitable for orthogonal architecture equipment and an implementation method thereof. The control link of the equipment comprises two main control boards, six cross boards and eight service boards; the two main control boards respectively comprise a control chip and a switching chip; the six cross boards respectively comprise a control chip and two exchange chips; the eight service boards respectively comprise a control chip and a switching chip. The invention provides a control channel from the main control board to each cross board and the service board of the device without a back board, the channel adopts GE interface, the Ethernet exchange chip which can realize the GE interface at present has at most 8 ports, the device realizes the exchange function of 12 GE ports, and the centralized control of the multi-board communication device is satisfied.
Description
Technical Field
The present invention relates to the field of communications technologies, and in particular, to a control link suitable for an orthogonal architecture device and an implementation method thereof.
Background
With the deepening of the informatization degree of the communication industry, particularly the rising of cloud computing and the application of the Internet of things, the big data era has come, and the rapid development of optical fiber communication is promoted by the massive data communication demand. At present, the optical fiber network rate of a backbone network reaches 100G, communication equipment faces the problem of leading-in of high-capacity 100G signals, so that in order to improve equipment capacity, an orthogonal architecture based on a backboard is favored, and due to the absence of the backboard, how to design a control link based on the orthogonal architecture enables all board cards to be controlled in a centralized manner, and the problem that independent and stable control planes need to be solved at present is guaranteed.
Disclosure of Invention
In view of the present state of the art and the need, the present invention provides a control link suitable for orthogonal architecture devices and a method for implementing the same.
The technical scheme adopted by the invention is as follows: a control link suitable for orthogonal architecture equipment is characterized by comprising two main control boards, six cross boards and eight service boards; the two main control boards respectively comprise a control chip and a switching chip; the six cross boards respectively comprise a control chip and two exchange chips; the eight service boards respectively comprise a control chip and a switching chip; the first control chip of the first main control board is connected with the first exchange chip, the second control chip of the second main control board is connected with the second exchange chip, the first control chip and the second control chip are respectively connected with the PC through network cables, and the first control chip and the second control chip are connected through an SERDES interface.
The third control chip of the first cross plate is connected with a third exchange chip, the third exchange chip is connected with a fourth exchange chip through a GE port, the fourth control chip of the second cross plate is connected with a fifth exchange chip, the fifth exchange chip is connected with a sixth exchange chip through the GE port, the fifth control chip of the third cross plate is connected with a seventh exchange chip, the seventh exchange chip is connected with an eighth exchange chip through the GE port, the sixth control chip of the fourth cross plate is connected with a ninth exchange chip, the ninth exchange chip is connected with a tenth exchange chip through the GE port, the seventh control chip of the fifth cross plate is connected with an eleventh exchange chip, the eleventh exchange chip is connected with a twelfth exchange chip through the GE port, the eighth control chip of the sixth cross plate is connected with a thirteenth exchange chip, and the thirteenth exchange chip is connected with the fourteenth exchange chip through the GE port.
The ninth control chip of the first service board is connected with the fifteenth switching chip, the tenth control chip of the second service board is connected with the sixteenth switching chip, the eleventh control chip of the third service board is connected with the seventeenth switching chip, the twelfth control chip of the fourth service board is connected with the eighteenth switching chip, the thirteenth control chip of the fifth service board is connected with the nineteenth switching chip, the fourteenth control chip of the sixth service board is connected with the twentieth switching chip, the fifteenth control chip of the seventh service board is connected with the twenty-first switching chip, and the sixteenth control chip of the eighth service board is connected with the twenty-second switching chip.
And the third exchange chip of the first cross board, the fifth exchange chip of the second cross board, the seventh exchange chip of the third cross board, the ninth exchange chip of the fourth cross board, the eleventh exchange chip of the fifth cross board and the thirteenth exchange chip of the sixth cross board are respectively connected with the first exchange chip of the first main control board and the second exchange chip of the second main control board through GE interfaces.
The fifteenth switching chip of the first service board, the sixteenth switching chip of the second service board, the seventeenth switching chip of the third service board and the eighteenth switching chip of the fourth service board are simultaneously connected to the third cross chip of the first cross board, the fifth cross chip of the second cross board, the seventh cross chip of the third cross board, the ninth cross chip of the fourth cross board, the eleventh cross chip of the fifth cross board and the thirteenth cross chip of the sixth cross board through GE interfaces respectively; and the nineteenth switching chip of the fifth service board, the twentieth switching chip of the sixth service board, the twenty-first switching chip of the seventh service board and the twenty-second switching chip of the eighth service board are simultaneously connected to the fourth cross chip of the first cross board, the sixth cross chip of the second cross board, the eighth cross chip of the third cross board, the tenth cross chip of the fourth cross board, the twelfth cross chip of the fifth cross board and the fourteenth cross chip of the sixth cross board respectively through GE interfaces.
A method for realizing the control link suitable for orthogonal framework equipment as claimed in claim 1, wherein, first, the control chip and the switching chip on the main control board are led out RJ45 interface, SERDES interface and GE interface respectively, the RJ45 interface is connected with the PC through the network cable to realize the communication with the management software on the PC, the SERDES interface is interconnected through the horizontal plate to realize the information synchronization between the main and standby, the GE interface is connected with the first to sixth cross boards to realize the communication with the cross board and the service board; the priority of the first main control board is highest, the first main control board is defaulted to work, the first main control board synchronizes information with the second main control board in real time, and when the first main control board fails, the second main control board starts to work and has the function of main-standby switching.
The exchange chip on the cross board is provided with 10 GE interfaces, wherein the two GE interfaces are respectively connected with the two main control boards, the 8 GE interfaces are respectively connected with the 8 service boards, the communication between the control chip of the cross board and the main control boards is realized, and meanwhile, a communication bridge is established from the main control boards to the service boards; the GE channels from the first cross board to the first service board 1 to the eighth service board are respectively the highest priority and are defaulted to be the main control channel, the GE channels from the second cross board to the sixth cross board to the first service board 1 to the eighth service board are respectively the standby control channels, the default main control channel is effective, and the standby control channels are forbidden to prevent network storm; when the main control channel is abnormally disconnected, the standby control channel from the second cross board to the first service board to the eighth service board works, and when the standby channel of the second cross board is abnormally disconnected, the standby control channel from the third cross board to the first service board to the eighth service board works, and so on, so that the standby protection of multiple channels is realized.
The exchange chip on the service board leads out 6 GE interfaces in total, and the GE interfaces are connected with the cross board to realize communication with the main control board.
The design principle of the invention is as follows: the control link of the orthogonal architecture device comprises two main control boards, 6 cross boards and 8 service boards. The main control board provides the network management function of the equipment, is connected with the PC, is connected with the cross boards and the service board, and has the capability of vertical and horizontal real-time processing and communication. The main control board provides an independent control plane for the equipment and supports the main and standby functions, the priority of the first main control board is highest, the first main control board is defaulted to work, the first main control board synchronizes information with the second main control board in real time, when the first main control board fails, the second main control board starts to work, and when the first main control board recovers to work, the role of main control is recovered. The cross boards build an intercommunication bridge for communication between the equipment main control board and the service board, meanwhile, a plurality of cross boards provide a plurality of channels between the main control board and the service board, the first cross board 1 is used as a main channel in a default mode, and the second cross boards 2 to the sixth cross boards are used as standby channels.
The invention has the following advantages: under the condition of no back plate, control channels are provided for the equipment main control board to each cross board and the service board, the channels adopt GE interfaces, at present, the maximum number of Ethernet switching chips capable of realizing the GE interfaces is 8, the equipment realizes the switching function of 12 GE ports, and the centralized control of the multi-board communication equipment is met.
Drawings
FIG. 1 is a control link block diagram of an orthogonal architecture apparatus of the present invention;
FIG. 2 is a control block diagram of a main control board according to an embodiment of the present invention;
FIG. 3 is a cross board control block diagram in an embodiment of the present invention;
fig. 4 is a control block diagram of a service board in an embodiment of the present invention.
Detailed Description
In order to more clearly understand the technical solution of the present invention, the present invention is further described with reference to the accompanying drawings and examples.
As shown in fig. 1, a control link suitable for an orthogonal architecture device includes two main control boards, six cross boards, and eight service boards; the two main control boards respectively comprise a control chip and a switching chip; the six cross boards respectively comprise a control chip and two exchange chips; the eight service boards respectively comprise a control chip and a switching chip; the first control chip of the first main control board is connected with the first exchange chip, the second control chip of the second main control board is connected with the second exchange chip, the first control chip and the second control chip are respectively connected with the PC through network cables, and the first control chip and the second control chip are connected through an SERDES interface.
The third control chip of the first cross plate is connected with a third exchange chip, the third exchange chip is connected with a fourth exchange chip through a GE port, the fourth control chip of the second cross plate is connected with a fifth exchange chip, the fifth exchange chip is connected with a sixth exchange chip through the GE port, the fifth control chip of the third cross plate is connected with a seventh exchange chip, the seventh exchange chip is connected with an eighth exchange chip through the GE port, the sixth control chip of the fourth cross plate is connected with a ninth exchange chip, the ninth exchange chip is connected with a tenth exchange chip through the GE port, the seventh control chip of the fifth cross plate is connected with an eleventh exchange chip, the eleventh exchange chip is connected with a twelfth exchange chip through the GE port, the eighth control chip of the sixth cross plate is connected with a thirteenth exchange chip, and the thirteenth exchange chip is connected with the fourteenth exchange chip through the GE port.
A ninth control chip of the first service board is connected with a fifteenth switching chip, a tenth control chip of the second service board is connected with a sixteenth switching chip, an eleventh control chip of the third service board is connected with a seventeenth switching chip, a twelfth control chip of the fourth service board is connected with an eighteenth switching chip, a thirteenth control chip of the fifth service board is connected with a nineteenth switching chip, a fourteenth control chip of the sixth service board is connected with a twentieth switching chip, a fifteenth control chip of the seventh service board is connected with a twenty-first switching chip, and a sixteenth control chip of the eighth service board is connected with a twenty-second switching chip;
and the third exchange chip of the first cross board, the fifth exchange chip of the second cross board, the seventh exchange chip of the third cross board, the ninth exchange chip of the fourth cross board, the eleventh exchange chip of the fifth cross board and the thirteenth exchange chip of the sixth cross board are respectively connected with the first exchange chip of the first main control board and the second exchange chip of the second main control board through GE interfaces.
A fifteenth switching chip of the first service board, a sixteenth switching chip of the second service board, a seventeenth switching chip of the third service board and an eighteenth switching chip of the fourth service board are simultaneously connected to a third cross chip of the first cross board, a fifth cross chip of the second cross board, a seventh cross chip of the third cross board, a ninth cross chip of the fourth cross board, an eleventh cross chip of the fifth cross board and a thirteenth cross chip of the sixth cross board respectively through GE interfaces; and the nineteenth switching chip of the fifth service board, the twentieth switching chip of the sixth service board, the twenty-first switching chip of the seventh service board and the twenty-second switching chip of the eighth service board are simultaneously connected to the fourth cross chip of the first cross board, the sixth cross chip of the second cross board, the eighth cross chip of the third cross board, the tenth cross chip of the fourth cross board, the twelfth cross chip of the fifth cross board and the fourteenth cross chip of the sixth cross board respectively through GE interfaces.
Firstly, an RJ45 interface, an SERDES interface and a GE interface are respectively led out from a control chip and a switching chip on a main control board, the RJ45 interface is connected with a PC through a network cable to realize communication with management software on the PC, the SERDES interfaces are interconnected through a back board and a transverse board to realize information synchronization between a main board and a standby board, and the GE interface is connected with first to sixth cross boards to realize communication with the cross boards and a service board; the priority of the main control board 1 is highest, the main control board 1 is defaulted to work, the solid line part works in the figure, the dotted line part is in a forbidden state to prevent the generation of network storm, the main control board 1 synchronizes information with the main control board 2 in real time, when the main control board 1 fails, the main control board 2 starts to work, and the dotted line part is started to realize the main-standby switching function.
10 GE interfaces are led out from the exchange chip on the cross board, wherein two GE interfaces are respectively connected with the main control board, 8 GE interfaces are respectively connected with 8 service boards, communication between the control chip of the cross board and the main control board is realized, and a communication bridge is built from the main control board to the service boards; the GE channel from the cross board 1 to the service board 8 has the highest priority and is the main control channel by default, the GE channel from the cross board 2 to the service board 1 to the service board 8 is the standby control channel, the main control channel is effective by default, and the standby control channel is forbidden to prevent network storm; when the main control channel is abnormally disconnected, the standby control channels from the cross board 2 to the service boards 1-8 work, and when the standby channel of the cross board 2 is abnormally disconnected, the standby control channels from the cross board 3 to the service boards 1-8 work, and so on, so that the standby protection of multiple channels is realized.
The exchange chip on the service board leads out 6 GE interfaces, and is connected with the cross board to realize the communication with the main control board.
The main control board comprises an RJ45 control interface and 1 horizontal signal connector, the RJ45 control interface is connected with a PC, and the horizontal signal connector is connected with a transverse plate of the back plate. The cross board includes 1 horizontal signal connector and 8 orthogonal signal connectors. The service board comprises 6 orthogonal signal connectors. The horizontal signal connector on the main control board is the same as the horizontal signal connector on the cross board in type.
The horizontal signal connector on the main control board is in signal connection with the horizontal signal connector on the cross board through a back board transverse plate; and the orthogonal signal connector on the cross board is directly connected with the orthogonal signal connector on the service board to realize signal transmission.
As shown in fig. 2, the hardware of the two main control boards is completely the same, the control chips on the main control boards are connected with the ethernet controller 1 through RGMII _1 interfaces, the ethernet controller 1 is connected with the switch chip through GE interfaces, and the switch chip is led out to the horizontal signal connector through GE1-GE6 interfaces and connected to six switch boards; the Ethernet controller 2 is connected with the RJ45 interface through the GE interface, is led out to the horizontal signal connector through the SERDES interface and is connected to the standby main control board.
The control chip of the main control board adopts Zynq-030 chip, the Ethernet controller adopts PHY-88E1518 chip, the exchange chip adopts BCM53128, the control chip Zynq-030 draws out two RGMII interfaces to connect with PHY chip, draw out a SERDES interface to the horizontal connector, connect with spare main control board directly, 7 GE interfaces are drawn out from BCM53128 chip, 1 is connected with PHY chip directly, 6 are drawn out to the horizontal signal connector, connect with 6 cross boards.
As shown in FIG. 3, the hardware of 6 cross boards is completely the same, the cross board adopts a control chip Zynq-030, the Ethernet controller adopts a PHY-88E1518 chip, two switching chips adopt a BCM53128, the control chip Zynq-030 leads out an RGMII interface to be connected with the PHY chip, 8 GE interfaces are led out from the switching chip 1-BCM53128 chip, a GE1 channel is connected with the PHY chip, GE2 and GE3 channels are connected with a main control board through a horizontal signal connector, a channel for communication between the cross board and the main control board is established, the GE4-GE7 channels are respectively connected with the service boards 1-4 through orthogonal signal connectors 1-4, a channel for communication between the main control board and the service boards 1-4 is established, the GE8 channel is connected with the switching chip 2-BCM53128 chip, 4 GE interfaces are led out from the switching chip 2-BCM53128 chip, the GE 1-4 channels are respectively connected with the service boards 5-8 through orthogonal signal connectors 5-8, and establishing a communication channel from the main control board to the service boards 5-8.
The cross board adopts a mode of cascading two exchange chips to realize the extension of a GE interface, the problem of simultaneous control of a plurality of board cards is solved, meanwhile, the control channel of the cross board 1 is acquiescent to work and is in an open state, and the control channel of the cross board 2-the cross board 6 is used as a standby channel and is acquiescent to be in a forbidden state to prevent network storms.
As shown in fig. 4, the hardware of 8 service boards is completely the same, the service board adopts a control chip Zynq-030, an ethernet control chip PHY-88E1518, a switch chip is BCM53128, the control chip Zynq-030 leads out an RGMII interface to be connected with a PHY chip, the BCM53128 chip leads out 7 GE interfaces, a GE1 channel is connected with the PHY chip, GE2-GE7 channels are respectively connected with a cross board 1-a cross board 6 through orthogonal signal connectors 1-6, a default state GE2 channel is a main channel and is in a working state, GE3-GE7 are standby channels and are in a disabled state, when a GE2 channel works abnormally, the GE3 channel is converted into the main channel and is in the working state, and so on.
Claims (2)
1. A control link suitable for orthogonal architecture equipment is characterized by comprising two main control boards, six cross boards and eight service boards; the two main control boards respectively comprise a control chip and a switching chip; the six cross boards respectively comprise a control chip and two exchange chips; the eight service boards respectively comprise a control chip and a switching chip; the first control chip of the first main control board is connected with the first exchange chip, the second control chip of the second main control board is connected with the second exchange chip, the first control chip and the second control chip are respectively connected with the PC through network cables, and the first control chip and the second control chip are connected through an SERDES interface;
the third control chip of the first cross plate is connected with a third exchange chip, the third exchange chip is connected with a fourth exchange chip through a GE port, the fourth control chip of the second cross plate is connected with a fifth exchange chip, the fifth exchange chip is connected with a sixth exchange chip through a GE port, the fifth control chip of the third cross plate is connected with a seventh exchange chip, the seventh exchange chip is connected with an eighth exchange chip through a GE port, the sixth control chip of the fourth cross plate is connected with a ninth exchange chip, the ninth exchange chip is connected with a tenth exchange chip through a GE port, the seventh control chip of the fifth cross plate is connected with an eleventh exchange chip, the eleventh exchange chip is connected with a twelfth exchange chip through a GE port, the eighth control chip of the sixth cross plate is connected with a thirteenth exchange chip, and the thirteenth exchange chip is connected with the fourteenth exchange chip through a GE port;
the ninth control chip of the first service board is connected with the fifteenth switching chip, the tenth control chip of the second service board is connected with the sixteenth switching chip, the eleventh control chip of the third service board is connected with the seventeenth switching chip, the twelfth control chip of the fourth service board is connected with the eighteenth switching chip, the thirteenth control chip of the fifth service board is connected with the nineteenth switching chip, the fourteenth control chip of the sixth service board is connected with the twentieth switching chip, the fifteenth control chip of the seventh service board is connected with the twenty-first switching chip, and the sixteenth control chip of the eighth service board is connected with the twenty-second switching chip;
the third exchange chip of the first cross board, the fifth exchange chip of the second cross board, the seventh exchange chip of the third cross board, the ninth exchange chip of the fourth cross board, the eleventh exchange chip of the fifth cross board and the thirteenth exchange chip of the sixth cross board are respectively connected with the first exchange chip of the first main control board and the second exchange chip of the second main control board through GE interfaces;
the fifteenth switching chip of the first service board, the sixteenth switching chip of the second service board, the seventeenth switching chip of the third service board and the eighteenth switching chip of the fourth service board are simultaneously connected to the third cross chip of the first cross board, the fifth cross chip of the second cross board, the seventh cross chip of the third cross board, the ninth cross chip of the fourth cross board, the eleventh cross chip of the fifth cross board and the thirteenth cross chip of the sixth cross board through GE interfaces respectively; and the nineteenth switching chip of the fifth service board, the twentieth switching chip of the sixth service board, the twenty-first switching chip of the seventh service board and the twenty-second switching chip of the eighth service board are simultaneously connected to the fourth cross chip of the first cross board, the sixth cross chip of the second cross board, the eighth cross chip of the third cross board, the tenth cross chip of the fourth cross board, the twelfth cross chip of the fifth cross board and the fourteenth cross chip of the sixth cross board respectively through GE interfaces.
2. A method for realizing the control link suitable for orthogonal framework equipment as claimed in claim 1, wherein, first, the control chip and the switching chip on the main control board are led out RJ45 interface, SERDES interface and GE interface respectively, the RJ45 interface is connected with the PC through the network cable to realize the communication with the management software on the PC, the SERDES interface is interconnected through the horizontal plate to realize the information synchronization between the main and standby, the GE interface is connected with the first to sixth cross boards to realize the communication with the cross board and the service board; the priority of the first main control board is highest, the first main control board is defaulted to work, the first main control board synchronizes information with the second main control board in real time, and when the first main control board fails, the second main control board starts to work and has the function of main-standby switching;
10 GE interfaces are led out from the exchange chip on the cross board, wherein two GE interfaces are respectively connected with two main control boards, 8 GE interfaces are respectively connected with 8 service boards, communication between the control chip of the cross board and the main control boards is realized, and a communication bridge is built from the main control boards to the service boards; the GE channels from the first cross board to the first service board 1 to the eighth service board are respectively the highest priority and are defaulted to be the main control channel, the GE channels from the second cross board to the sixth cross board to the first service board 1 to the eighth service board are respectively the standby control channels, the default main control channel is effective, and the standby control channels are forbidden to prevent network storm; when the main control channel is abnormally disconnected, the standby control channel from the second cross board to the first service board to the eighth service board works, and when the standby channel of the second cross board is abnormally disconnected, the standby control channel from the third cross board to the first service board to the eighth service board works, and so on, so that the standby protection of multiple channels is realized;
the exchange chip on the service board leads out 6 GE interfaces, and is connected with the cross board to realize the communication with the main control board.
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| CN202011432030.1A CN112367573A (en) | 2020-12-10 | 2020-12-10 | Control link suitable for orthogonal architecture equipment and implementation method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113727161A (en) * | 2021-09-03 | 2021-11-30 | 南京大学 | Microblaze-based real-time video seam clipping method and system |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113727161A (en) * | 2021-09-03 | 2021-11-30 | 南京大学 | Microblaze-based real-time video seam clipping method and system |
| CN113727161B (en) * | 2021-09-03 | 2022-07-29 | 南京大学 | Microblaze-based real-time video seam clipping method and system |
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