CN112351596A - Selective electroplating method without conductive wire and packaging substrate - Google Patents
Selective electroplating method without conductive wire and packaging substrate Download PDFInfo
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- CN112351596A CN112351596A CN202110018001.9A CN202110018001A CN112351596A CN 112351596 A CN112351596 A CN 112351596A CN 202110018001 A CN202110018001 A CN 202110018001A CN 112351596 A CN112351596 A CN 112351596A
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- 239000000758 substrate Substances 0.000 title claims abstract description 191
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 70
- 238000000034 method Methods 0.000 title claims abstract description 43
- 238000009713 electroplating Methods 0.000 title claims abstract description 42
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 88
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 61
- 229910052737 gold Inorganic materials 0.000 claims abstract description 60
- 239000010931 gold Substances 0.000 claims abstract description 60
- 238000007747 plating Methods 0.000 claims abstract description 46
- 238000003825 pressing Methods 0.000 claims abstract description 42
- 229910000679 solder Inorganic materials 0.000 claims abstract description 27
- 239000007788 liquid Substances 0.000 claims abstract description 21
- 238000005553 drilling Methods 0.000 claims abstract description 15
- 239000011889 copper foil Substances 0.000 claims abstract description 14
- 239000002994 raw material Substances 0.000 claims abstract description 7
- 239000000126 substance Substances 0.000 claims abstract description 6
- 229910052802 copper Inorganic materials 0.000 claims description 74
- 239000010949 copper Substances 0.000 claims description 74
- 238000000151 deposition Methods 0.000 claims description 23
- 238000005530 etching Methods 0.000 claims description 23
- 230000008021 deposition Effects 0.000 claims description 19
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 14
- 229910052751 metal Inorganic materials 0.000 claims description 12
- 239000002184 metal Substances 0.000 claims description 12
- 238000007639 printing Methods 0.000 claims description 10
- 239000000523 sample Substances 0.000 claims description 9
- 238000012360 testing method Methods 0.000 claims description 9
- 239000003814 drug Substances 0.000 claims description 8
- 229910052759 nickel Inorganic materials 0.000 claims description 7
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 claims description 6
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 claims description 6
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 claims description 6
- 238000001035 drying Methods 0.000 claims description 6
- 238000003384 imaging method Methods 0.000 claims description 6
- 238000003466 welding Methods 0.000 claims description 6
- 230000003628 erosive effect Effects 0.000 claims description 5
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 5
- 230000007547 defect Effects 0.000 claims description 4
- 238000005516 engineering process Methods 0.000 claims description 4
- 238000004519 manufacturing process Methods 0.000 claims description 4
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 claims description 3
- 238000005234 chemical deposition Methods 0.000 claims description 3
- 239000003795 chemical substances by application Substances 0.000 claims description 3
- 229910017052 cobalt Inorganic materials 0.000 claims description 3
- 239000010941 cobalt Substances 0.000 claims description 3
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 3
- 238000001514 detection method Methods 0.000 claims description 3
- 238000005538 encapsulation Methods 0.000 claims description 3
- 239000010419 fine particle Substances 0.000 claims description 3
- 239000003292 glue Substances 0.000 claims description 3
- 238000007689 inspection Methods 0.000 claims description 3
- 229910052742 iron Inorganic materials 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 3
- 238000003801 milling Methods 0.000 claims description 3
- 230000003287 optical effect Effects 0.000 claims description 3
- 238000002791 soaking Methods 0.000 claims description 3
- 229910052725 zinc Inorganic materials 0.000 claims description 3
- 239000011701 zinc Substances 0.000 claims description 3
- 239000013078 crystal Substances 0.000 claims description 2
- XTFKWYDMKGAZKK-UHFFFAOYSA-N potassium;gold(1+);dicyanide Chemical compound [K+].[Au+].N#[C-].N#[C-] XTFKWYDMKGAZKK-UHFFFAOYSA-N 0.000 claims description 2
- 238000009792 diffusion process Methods 0.000 abstract description 5
- MSNOMDLPLDYDME-UHFFFAOYSA-N gold nickel Chemical compound [Ni].[Au] MSNOMDLPLDYDME-UHFFFAOYSA-N 0.000 abstract description 3
- 238000007598 dipping method Methods 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 18
- 206010034972 Photosensitivity reaction Diseases 0.000 description 4
- 230000036211 photosensitivity Effects 0.000 description 4
- 238000007650 screen-printing Methods 0.000 description 4
- 238000004140 cleaning Methods 0.000 description 3
- 238000001723 curing Methods 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 230000017525 heat dissipation Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000000016 photochemical curing Methods 0.000 description 2
- 238000005554 pickling Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- XFXPMWWXUTWYJX-UHFFFAOYSA-N Cyanide Chemical compound N#[C-] XFXPMWWXUTWYJX-UHFFFAOYSA-N 0.000 description 1
- ZLMJMSJWJFRBEC-UHFFFAOYSA-N Potassium Chemical compound [K] ZLMJMSJWJFRBEC-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000003889 chemical engineering Methods 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 229910052700 potassium Inorganic materials 0.000 description 1
- 239000011591 potassium Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
- H05K3/243—Reinforcing the conductive pattern characterised by selective plating, e.g. for finish plating of pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Geometry (AREA)
- Ceramic Engineering (AREA)
- Manufacturing Of Printed Wiring (AREA)
- Manufacturing Of Printed Circuit Boards (AREA)
Abstract
The invention discloses a selective electroplating method of a non-conductive wire and a packaging substrate. The method for selectively plating the non-conductive line and the packaging substrate are as follows, S1: raw material taking and baking, S2: thinning the double-sided copper foil, and S3: drilling a hole in the copper-clad substrate, S4: and (5) electroplating the copper-clad substrate after drilling, wherein S5: dry pressing the electroplated copper-clad substrate, S6: and (3) carrying out circuit exposure on the copper-clad substrate after the dry film is pressed, and S7: and (4) developing the exposed copper-clad substrate, wherein S8: according to the method, the space occupied by the conductive wire is reduced through the operation of S1-19, the nickel-gold electroplating layer is more uniform, the problems of gold dipping, upper diffusion plating and the like are solved, the problem that chemical liquid attacks the solder mask is solved, the quality of the selectively electroplated packaging substrate without the conductive wire is more excellent, and the space utilization efficiency of the packaging substrate is greatly improved.
Description
Technical Field
The invention relates to the field of processing, in particular to a selective electroplating method of a non-conductive wire and a packaging substrate.
Background
The package substrate is a term in printed wiring boards. The substrate can provide the effects of electric connection, protection, support, heat dissipation, assembly and the like for the chip so as to realize the purposes of multi-pin, reduction of the volume of a packaged product, improvement of electric performance and heat dissipation, ultrahigh density or multi-chip modularization. The package substrate should belong to the interdisciplinary technology, and it relates to the knowledge of electronics, physics, chemical engineering, etc.
In order to meet the requirement of a high-density packaging substrate with a thinner line pitch, more wiring space must be reserved as much as possible, and particularly, the wiring space is occupied after the conductive line used after electroplating is finished and is not needed to be etched back. Specifically, when the circuit layer of the package substrate is plated with ni/au, the current required for the plating must be conducted through the conductive wire connected to the circuit layer in order to conduct the current to the substrate, especially the circuit layer to be plated. If the wiring space occupied by the conductive line is desired to be reduced, and the width of the conductive line is made narrower, the thickness of the electroplated nickel-gold layer is not uniform, and therefore, it is still not a good way to increase the wiring density by reducing the width of the conductive line. Meanwhile, the method for electroplating gold on the conductive wire has the defects that an etching window is small, diffusion plating is easy to occur during nickel and gold electroplating to influence the yield, chemical liquid attacks the solder mask, gold is stained and the diffusion plating is performed, and the like, and if the dry film performance is insufficient, the dry film curing is insufficient, and the upper diffusion plating phenomenon is generated.
Disclosure of Invention
The present invention is directed to a method for selectively plating a non-conductive line and a package substrate, so as to solve the problems mentioned in the background art.
In order to achieve the purpose, the invention provides the following technical scheme:
a method for selective plating of an electrically non-conductive line, the method comprising the steps of:
s1: taking and baking the raw materials, taking the double-sided copper clad laminate, and baking for two hours at the temperature of 195 ℃;
s2: thinning the double-sided copper foil, and biting and eroding the copper foil layers on two sides of the raw material by using sulfuric acid and hydrogen peroxide microetching liquid to reduce the thickness of the copper foil layers and form a copper-clad substrate;
s3: drilling a hole on the copper-clad substrate, drilling a through hole on the copper-clad substrate from top to bottom on a numerical control drilling machine according to a drilling program, wherein the size of a drill bit is 90 mu m, and the tolerance of the hole diameter of the drill hole is within +/-0.005 mm;
s4: electroplating the copper-clad substrate after drilling, metalizing the hole by using electroless copper plating, ensuring the thickness requirement of the electroplated copper layer of the copper on the inner surface of the hole and the outer surface of the copper-clad substrate, and forming a layer of electroplated copper layer on the copper on the inner surface of the hole and the outer surface of the copper-clad substrate;
s5: pressing a dry film on the electroplated copper-clad substrate, and attaching the dry film on the electroplated copper-clad substrate by high-temperature pressing through a photosensitive dry film on a film pressing roller, wherein the film pressing temperature is 105-125 ℃, the film pressing time is 1-2 seconds, and a double-sided automatic film pressing mode is adopted;
s6: carrying out circuit exposure on the copper-clad substrate after the dry film is pressed, and imaging circuit graphic data on the electroplated copper layer by utilizing a photosensitive dry film through film negative film exposure or a laser direct imaging technology;
s7: developing the exposed copper-clad substrate, solidifying and reserving exposed part of the dry film through a developer solution, and dissolving and removing unexposed part of the dry film;
s8: etching the developed copper-clad substrate, and etching the unexposed part by using an etching solution to remove the copper layer to form a circuit pattern layer on the surface of the copper-clad substrate;
s9: removing the film from the etched substrate at 45 deg.C under 2.5Kg/cm2Removing the film under the environment, and exposing the dry film on the part to form a packaging substrate;
s10: performing AOI detection on the packaging substrate, performing optical scanning on a GTL surface and a GBL surface of the circuit board, and identifying open short circuit defect inspection;
s11: performing copper deposition on the package substrate scanned by the AOI, and depositing a layer of fine-particle thin chemical metal copper deposition layer on the inner surface of the hole wall of the package substrate and the circuit pattern layers on the upper surface and the lower surface by using a chemical deposition method, wherein the thickness of the metal copper deposition layer is within 1.0-1.4um, so that the short circuit phenomenon of the package substrate is formed;
s12: performing dry film covering on the packaging substrate after the metal copper layer is deposited, performing dry film removal on the part of the deposited copper layer needing gold electroplating by using an anti-electroplating dry film, and performing dry film covering on the part without gold electroplating;
s13: microetching the pressed packaging substrate to remove the copper deposit layer in the area needing electroplating gold, etching the copper deposit layer without the dry film to show the part of the gold layer to be electroplated by microetching solution with the concentration of 90-120g/L, the temperature of 28-32 ℃ and the pressure of a liquid medicine tank of 1.0-1.5Kg/cm2Drying the plate surface after micro etching to expose the area needing electroplating gold layer;
s14: performing electrogilding operation on a part of area needing electrogilding, plating a layer of metal layer containing nickel, gold, copper, zinc and iron on the part needing electrogilding, and simultaneously placing the encapsulation substrate after electrogilding in DI water for soaking and then drying moisture;
s15: stripping the film of the packaging substrate after the gold layer is electroplated, and removing the dry film of the part which is not electroplated with gold through the film stripping liquid;
s16: the packaging substrate with the dry film removed after the electrogilding is retreated is subjected to microetching, all copper deposition layers of the packaging substrate are corroded by microetching liquid, the packaging substrate with a complete circuit pattern is displayed, and the surface of the packaging substrate is dried after the microetching, so that the packaging substrate to be subjected to solder mask operation is obtained;
s17: performing solder mask operation on the package substrate after the gold electroplating to form a solder mask layer;
s18: forming, namely forming the packaging substrate with the size of the milled plugging strip, and milling the packaging substrate with the size of the plugging strip after the welding-resistant layer is finished;
s19: and (3) detecting the open and short circuit of the packaging substrate network by the flying probe to obtain a final selective electrogilding packaging substrate without the conductive wire, and detecting the open and short circuit by adopting an electric probe, wherein two probes are in contact with the network end point to be electrified to detect the open and short circuit.
As a still further scheme of the invention: and baking in the step S1 to take out moisture of the copper-clad substrate, eliminating internal stress of the copper-clad substrate and improving the dimensional stability of the material, wherein the copper foil of the step S2 is thinned to be used for laying for subsequent copper plating, so that the phenomenon that the circuit manufacturing process capability is increased due to too thick copper is avoided, and no etching lead is designed in the circuit pattern data in the step S6.
As a still further scheme of the invention: and (3) covering the dry film in S12, wherein the steps are as follows:
1): pressing the dry film to be electroplated on the copper deposition layer of the substrate by a film pressing roller heated by a heater of an upper film pressing roller and a lower film pressing roller, wherein the film pressing temperature is 130 ℃, the film pressing time is 2.5 seconds, the pressure during film pressing is controlled at 0.45Mpa, the hardness of the film pressing roller is 62.5 degrees, and dry film layers on the front side and the back side are formed after film pressing;
2): exposing, namely performing film exposure on the film-coated substrate after film pressing, setting the exposure energy at 6 levels and the uniformity to be more than 90% by utilizing the principle that a dry film has photosensitivity, transferring the virtual data of engineering manufacture onto the substrate by using an exposure machine to enable the dry film of the substrate to present a required pattern, and exposing the part which does not need to be electroplated;
3): and developing, dissolving and removing the unexposed part of the dry film of the exposed substrate through developer solution, and solidifying and reserving the exposed part of the dry film so as to ensure that the area of the electroplated gold is not covered by the dry film layer and the area of the electroplated gold is not covered by the dry film layer.
As a still further scheme of the invention: in the S14, the concentration of potassium aurocyanide in an electroplating pool is 1.8g/L, the content of nickel cakes is less than 200ppm, the content of copper is less than 5ppm, the content of cobalt is 1.0-1.3g/L, the content of a light agent P is 2.5-6g/L, the temperature is 35-40 ℃, the current density is 0.2ASD-0.4ASD during electroplating, so that two surfaces of a gold layer to be electroplated are both electroplated with a gold layer, the gold thickness and the crystal roughness of the electroplated gold are confirmed by a first piece after electroplating is finished, and a bonding tension test, a 3M glue test, a gold thickness test and the like are carried out on the electroplated gold area.
As a still further scheme of the invention: the concentration of the stripping solution in the S15 is 12%, the stripping temperature is controlled at 48-52 ℃, the stripping speed is 2m/min, the plating-resistant dry films on the double-sided packaging substrate are completely removed, the concentration of the micro-etching solution in the S16 is 90-120g/L, the temperature of the micro-etching solution is 28-32 ℃, and the pressure of the liquid medicine tank is 1.0-1.7Kg/cm2。
As a still further scheme of the invention: the step of operating the welding preventing layer of S17 is as follows:
1): the method comprises the following steps of performing solder mask pretreatment, cleaning a packaging substrate before solder mask, coarsening copper surfaces on two surfaces of the packaging substrate by using a super-coarsening liquid medicine to form a coarse structure so as to improve the bonding force between a solder mask layer and the copper surface of the packaging substrate, and then pickling the copper surface of the packaging substrate to prevent the copper surface from entering a dust-free chamber to be oxidized;
2): performing silk-screen printing operation on a solder mask layer, adding oil and water into photosensitive ink, modulating and standing for later use, mounting a screen plate, a scraper and a base plate, placing the package substrate subjected to super coarsening on a table top, selecting a screen plate with T number, adjusting silk-screen printing parameters, pouring the adjusted ink into the screen plate, and printing the oil on the copper surface of the package substrate by the silk-screen scraper to form a solder mask layer;
3): exposing and developing, namely, utilizing the photosensitivity of the printing ink, placing the package substrate after being printed with the printing ink on an exposure machine for contraposition, transferring the virtual data of the solder mask film to the photosensitive printing ink by an exposure system of the exposure machine, wherein the non-gold-electroplated area is exposed, and the gold-electroplated area is shielded and not exposed; removing ink in unexposed area of the packaging substrate subjected to double-sided exposure by using a developing solution, wherein the upper and lower pressures are 2.0/1.5kg/cm at a speed of 1.8m/min during development2The developing temperature is 30 +/-2 ℃, and the ink in the exposure area is cured and reserved;
4): and UV treatment, namely putting the developed packaging substrate into an oven, curing the printing ink of the welding-proof layer by adopting a high-temperature baking plate, and then carrying out photocuring on the product cured at high temperature by using a UV ultraviolet lamp to ensure the hardening degree of the printing ink.
The selective electroplating packaging substrate without the conductive wire comprises a substrate, wherein through holes are formed in the substrate, and circuit pattern layers are arranged on two sides of the substrate.
Compared with the prior art, the invention has the beneficial effects that:
according to the invention, through the operation of S1-19, the space occupied by the conductive wire is reduced, the nickel-gold electroplating layer is more uniform, the problems of gold dipping, upper diffusion plating and the like are avoided, and the problem that chemical liquid attacks the solder mask is avoided, so that the quality of the selectively electroplated packaging substrate without the conductive wire is more excellent, and the space utilization efficiency of the packaging substrate is greatly improved.
Drawings
FIG. 1 is a schematic diagram of a method for selectively plating a non-conductive line and a double-sided copper-clad laminate of a package substrate.
Fig. 2 is a schematic diagram of a method for selectively plating a non-conductive line and thinning a double-sided copper foil of a package substrate.
FIG. 3 is a schematic diagram of a method for selectively plating a non-conductive line and a copper-clad substrate drilling of a package substrate.
FIG. 4 is a schematic diagram of a method for selectively plating a non-conductive line and a copper layer for plating a package substrate.
FIG. 5 is a schematic diagram of a method for selectively plating a non-conductive line and a dry film pressing process after a pre-acid cleaning process for a circuit of a package substrate.
FIG. 6 is a schematic diagram of a method for selective plating without conductive lines and a film of a package substrate.
FIG. 7 is a schematic diagram of a method for selectively plating a non-conductive line and a circuit exposure of a package substrate.
FIG. 8 is a schematic diagram of a method for selective plating without conductive lines and the development of the circuitry of the package substrate.
FIG. 9 is a schematic diagram of a method for selective plating without conductive lines and etching of a circuit substrate of a package substrate.
FIG. 10 is a schematic diagram of a method for selectively plating a non-conductive line and a circuit substrate of a package substrate with a film removed.
Fig. 11 is a schematic diagram of a selective plating method without conductive lines and a copper deposition layer structure of a package substrate.
FIG. 12 is a schematic diagram of a method for selectively plating a non-conductive line and a dry film package of a package substrate with gold plating.
FIG. 13 is a schematic diagram of a selective plating method without conductive lines and a micro-etched copper-deposition layer of a gold-plated layer of a package substrate.
FIG. 14 is a schematic diagram of a method for selective plating of a non-conductive line and gold layer plating of a package substrate.
FIG. 15 is a schematic diagram of a method for selectively plating a non-conductive line and removing a dry film outside a plated gold layer of a package substrate.
FIG. 16 is a schematic diagram of a selective plating method without conductive lines and a copper layer of a substrate without a gold plating portion for micro-etching of a package substrate.
FIG. 17 is a schematic diagram of a method for selective plating without conductive lines and solder mask of a package substrate.
FIG. 18 is a flow chart of a method of selective plating without conductive lines and a method of packaging a substrate.
Fig. 19 is a diagram of a method for selective plating without conductive lines and a package substrate structure of a package substrate.
In the figure: 1 substrate, 2 through holes and 3 circuit pattern layers.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1 to 19, in an embodiment of the present invention, a method for selectively plating an electroless plating layer includes the following steps:
s1: taking and baking the raw materials, taking the double-sided copper clad laminate, and baking for two hours at the temperature of 195 ℃;
s2: thinning the double-sided copper foil, and biting and eroding the copper foil layers on two sides of the raw material by using sulfuric acid and hydrogen peroxide microetching liquid to reduce the thickness of the copper foil layers and form a copper-clad substrate;
s3: drilling a hole on the copper-clad substrate, drilling a through hole on the copper-clad substrate from top to bottom on a numerical control drilling machine according to a drilling program, wherein the size of a drill bit is 90 mu m, and the tolerance of the hole diameter of the drill hole is within +/-0.005 mm;
s4: electroplating the copper-clad substrate after drilling, metalizing the hole by using electroless copper plating, ensuring the thickness requirement of the electroplated copper layer of the copper on the inner surface of the hole and the outer surface of the copper-clad substrate, and forming a layer of electroplated copper layer on the copper on the inner surface of the hole and the outer surface of the copper-clad substrate;
s5: pressing a dry film on the electroplated copper-clad substrate, and attaching the dry film on the electroplated copper-clad substrate by high-temperature pressing through a photosensitive dry film on a film pressing roller, wherein the film pressing temperature is 105-125 ℃, the film pressing time is 1-2 seconds, and a double-sided automatic film pressing mode is adopted;
s6: carrying out circuit exposure on the copper-clad substrate after the dry film is pressed, and imaging circuit graphic data on the electroplated copper layer by utilizing a photosensitive dry film through film negative film exposure or a laser direct imaging technology;
s7: developing the exposed copper-clad substrate, solidifying and reserving exposed part of the dry film through a developer solution, and dissolving and removing unexposed part of the dry film;
s8: etching the developed copper-clad substrate, and etching the unexposed part by using an etching solution to remove the copper layer to form a circuit pattern layer on the surface of the copper-clad substrate;
s9: removing the film from the etched substrate at 45 deg.C under 2.5Kg/cm2Removing the film under the environment, and exposing the dry film on the part to form a packaging substrate;
s10: performing AOI detection on the packaging substrate, performing optical scanning on a GTL surface and a GBL surface of the circuit board, and identifying open short circuit defect inspection;
s11: performing copper deposition on the package substrate scanned by the AOI, and depositing a layer of fine-particle thin chemical metal copper deposition layer on the inner surface of the hole wall of the package substrate and the circuit pattern layers on the upper surface and the lower surface by using a chemical deposition method, wherein the thickness of the metal copper deposition layer is within 1.0-1.4um, so that the short circuit phenomenon of the package substrate is formed;
s12: performing dry film covering on the packaging substrate after the metal copper layer is deposited, performing dry film removal on the part of the deposited copper layer needing gold electroplating by using an anti-electroplating dry film, and performing dry film covering on the part without gold electroplating;
s13: and (3) microetching the packaged substrate after film pressing, microetching the copper deposition layer in the area needing electroplating gold, and eroding the copper deposition layer without the dry film cover by using microetching solution to show the part of the gold layer to be electroplated, wherein the concentration of the microetching solution is 90-120g/L, the temperature of the microetching solution is 28-32 ℃, and the pressure of the liquid medicine tank is 1.0-1.5Kg/cm2Drying the plate surface after micro etching to expose the area needing electroplating gold layer;
s14: performing electrogilding operation on a part of area needing electrogilding, plating a layer of metal layer containing nickel, gold, copper, zinc and iron on the part needing electrogilding, and simultaneously placing the encapsulation substrate after electrogilding in DI water for soaking and then drying moisture;
s15: stripping the film of the packaging substrate after the gold layer is electroplated, and removing the dry film of the part which is not electroplated with gold through the film stripping liquid;
s16: the packaging substrate with the dry film removed after the electrogilding is retreated is subjected to microetching, all copper deposition layers of the packaging substrate are corroded by microetching liquid, the packaging substrate with a complete circuit pattern is displayed, and the surface of the packaging substrate is dried after the microetching, so that the packaging substrate to be subjected to solder mask operation is obtained;
s17: performing solder mask operation on the package substrate after the gold electroplating to form a solder mask layer;
s18: forming, namely forming the packaging substrate with the size of the milled plugging strip, and milling the packaging substrate with the size of the plugging strip after the welding-resistant layer is finished;
s19: and (3) detecting the open and short circuit of the packaging substrate network by the flying probe to obtain a final selective electrogilding packaging substrate without the conductive wire, and detecting the open and short circuit by adopting an electric probe, wherein two probes are in contact with the network end point to be electrified to detect the open and short circuit.
And baking in S1 to take out moisture of the copper-clad substrate, eliminating internal stress of the copper-clad substrate and improving the dimensional stability of the material, wherein the copper foil of S2 is thinned for laying the subsequent copper plating, so that the phenomenon that the circuit processing capacity is increased due to too thick copper is avoided, and no etching lead is designed in the circuit pattern data in S6.
And S12, covering the dry film by the following steps:
1): pressing the dry film to be electroplated on the copper deposition layer of the substrate by a film pressing roller heated by a heater of an upper film pressing roller and a lower film pressing roller, wherein the film pressing temperature is 130 ℃, the film pressing time is 2.5 seconds, the pressure during film pressing is controlled at 0.45Mpa, the hardness of the film pressing roller is 62.5 degrees, and dry film layers on the front side and the back side are formed after film pressing;
2): exposing, namely performing film exposure on the film-coated substrate after film pressing, setting the exposure energy at 6 levels and the uniformity to be more than 90% by utilizing the principle that a dry film has photosensitivity, transferring the virtual data of engineering manufacture onto the substrate by using an exposure machine to enable the dry film of the substrate to present a required pattern, and exposing the part which does not need to be electroplated;
3): and developing, dissolving and removing the unexposed part of the dry film of the exposed substrate through developer solution, and solidifying and reserving the exposed part of the dry film so as to ensure that the area of the electroplated gold is not covered by the dry film layer and the area of the electroplated gold is not covered by the dry film layer.
In S14, the concentration of potassium aurum cyanide in an electroplating pool is 1.8g/L, the content of nickel cakes is less than 200ppm, the content of copper is less than 5ppm, the content of cobalt is 1.0-1.3g/L, the content of a light agent P is 2.5-6g/L, the temperature is 35-40 ℃, the current density is 0.2ASD-0.4ASD during electroplating, a layer of gold layer is electroplated on two surfaces of the gold layer to be electroplated, the gold thickness and the crystallization roughness of the electroplated gold are confirmed by a first piece after electroplating, and a bonding tension test, a 3M glue test, a gold thickness test and the like are carried out on the electroplated gold area.
The concentration of the stripping solution in S15 is 12%, the stripping temperature is controlled at 48-52 deg.C, the stripping speed is 2m/min, the dry film with plating resistance on the double-sided packaging substrate is completely removed, the concentration of the microetching solution in S16 is 90-120g/L, the temperature of the microetching solution is 28-32 deg.C, and the pressure of the liquid medicine tank is 1.0-1.7Kg/cm2。
S17, welding layer operation, comprising the following steps:
1): the method comprises the following steps of performing solder mask pretreatment, cleaning a packaging substrate before solder mask, coarsening copper surfaces on two surfaces of the packaging substrate by using a super-coarsening liquid medicine to form a coarse structure so as to improve the bonding force between a solder mask layer and the copper surface of the packaging substrate, and then pickling the copper surface of the packaging substrate to prevent the copper surface from entering a dust-free chamber to be oxidized;
2): performing silk-screen printing operation on a solder mask layer, adding oil and water into photosensitive ink, modulating and standing for later use, mounting a screen plate, a scraper and a base plate, placing the package substrate subjected to super coarsening on a table top, selecting a screen plate with T number, adjusting silk-screen printing parameters, pouring the adjusted ink into the screen plate, and printing the oil on the copper surface of the package substrate by the silk-screen scraper to form a solder mask layer;
3): exposure developmentThe packaging substrate after being printed with the oil is placed on an exposure machine for contraposition by utilizing the photosensitivity of the ink, the exposure machine transfers the virtual data of the solder mask film to the photosensitive ink by using an exposure system, wherein the region without electroplated gold is exposed, and the region without electroplated gold is shaded and not exposed; removing ink in unexposed area of the packaging substrate subjected to double-sided exposure by using a developing solution, wherein the upper and lower pressures are 2.0/1.5kg/cm at a speed of 1.8m/min during development2The developing temperature is 30 +/-2 ℃, and the ink in the exposure area is cured and reserved;
4): and UV treatment, namely putting the developed packaging substrate into an oven, curing the printing ink of the welding-proof layer by adopting a high-temperature baking plate, and then carrying out photocuring on the product cured at high temperature by using a UV ultraviolet lamp to ensure the hardening degree of the printing ink.
A selective electroplating packaging substrate without a conductive wire comprises a substrate 1, wherein through holes 2 are formed in the substrate 1, and circuit pattern layers 3 are arranged on two sides of the substrate 1.
Although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that various changes in the embodiments and/or modifications of the invention can be made, and equivalents and modifications of some features of the invention can be made without departing from the spirit and scope of the invention.
Claims (7)
1. A method for selectively plating a non-conductive line, comprising: the method comprises the following steps:
s1: taking and baking raw materials;
s2: thinning the double-sided copper foil, and biting and eroding the copper foil layers on two sides of the raw material by using sulfuric acid and hydrogen peroxide microetching liquid to reduce the thickness of the copper foil layers and form a copper-clad substrate;
s3: drilling a hole on the copper-clad substrate, drilling a through hole on the copper-clad substrate from top to bottom on a numerical control drilling machine according to a drilling program, wherein the size of a drill bit is 90 mu m, and the tolerance of the hole diameter of the drill hole is within +/-0.005 mm;
s4: electroplating the copper-clad substrate after drilling, metalizing the hole by using electroless copper plating, ensuring the thickness requirement of the electroplated copper layer of the copper on the inner surface of the hole and the outer surface of the copper-clad substrate, and forming a layer of electroplated copper layer on the copper on the inner surface of the hole and the outer surface of the copper-clad substrate;
s5: pressing a dry film on the electroplated copper-clad substrate, and attaching the dry film on the electroplated copper-clad substrate by high-temperature pressing through a photosensitive dry film on a film pressing roller, wherein the film pressing temperature is 105-125 ℃, the film pressing time is 1-2 seconds, and a double-sided automatic film pressing mode is adopted;
s6: carrying out circuit exposure on the copper-clad substrate after the dry film is pressed, and imaging circuit graphic data on the electroplated copper layer by utilizing a photosensitive dry film through film negative film exposure or a laser direct imaging technology;
s7: developing the exposed copper-clad substrate, solidifying and reserving exposed part of the dry film through a developer solution, and dissolving and removing unexposed part of the dry film;
s8: etching the developed copper-clad substrate, and etching the unexposed part by using an etching solution to remove the copper layer to form a circuit pattern layer on the surface of the copper-clad substrate;
s9: removing the film from the etched substrate at 45 deg.C under 2.5Kg/cm2Removing the film under the environment, and exposing the dry film on the part to form a packaging substrate;
s10: performing AOI detection on the packaging substrate, performing optical scanning on a GTL surface and a GBL surface of the circuit board, and identifying open short circuit defect inspection;
s11: performing copper deposition on the package substrate scanned by the AOI, and depositing a layer of fine-particle thin chemical metal copper deposition layer on the inner surface of the hole wall of the package substrate and the circuit pattern layers on the upper surface and the lower surface by using a chemical deposition method, wherein the thickness of the metal copper deposition layer is within 1.0-1.4um, so that the short circuit phenomenon of the package substrate is formed;
s12: performing dry film covering on the packaging substrate after the metal copper layer is deposited, performing dry film removal on the part of the deposited copper layer needing gold electroplating by using an anti-electroplating dry film, and performing dry film covering on the part without gold electroplating;
s13: microetching the pressed packaging substrate, microetching the copper deposition layer of the area needing electroplating gold, biting and eroding the copper deposition layer without the dry film cover by using microetching solution to show the part of the gold layer to be electroplated, wherein the concentration of the microetching solution is 90-120g/L, the microetching liquid temperature is 28-32 ℃, and the pressure of the liquid medicine tank is 1.0-1.5Kg/cm2Drying the plate surface after micro etching to expose the area needing electroplating gold layer;
s14: performing electrogilding operation on a part of area needing electrogilding, plating a layer of metal layer containing nickel, gold, copper, zinc and iron on the part needing electrogilding, and simultaneously placing the encapsulation substrate after electrogilding in DI water for soaking and then drying moisture;
s15: stripping the film of the packaging substrate after the gold layer is electroplated, and removing the dry film of the part which is not electroplated with gold through the film stripping liquid;
s16: the packaging substrate with the dry film removed after the electrogilding is retreated is subjected to microetching, all copper deposition layers of the packaging substrate are corroded by microetching liquid, the packaging substrate with a complete circuit pattern is displayed, and the surface of the packaging substrate is dried after the microetching, so that the packaging substrate to be subjected to solder mask operation is obtained;
s17: performing solder mask operation on the package substrate after the gold electroplating to form a solder mask layer;
s18: forming, namely forming the packaging substrate with the size of the milled plugging strip, and milling the packaging substrate with the size of the plugging strip after the welding-resistant layer is finished;
s19: and (3) detecting the open and short circuit of the packaging substrate network by the flying probe to obtain a final selective electrogilding packaging substrate without the conductive wire, and detecting the open and short circuit by adopting an electric probe, wherein two probes are in contact with the network end point to be electrified to detect the open and short circuit.
2. The method of claim 1, further comprising the step of: and baking in the step S1 to take out moisture of the copper-clad substrate, eliminating internal stress of the copper-clad substrate and improving the dimensional stability of the material, wherein the copper foil of the step S2 is thinned to be used for laying for subsequent copper plating, so that the phenomenon that the circuit manufacturing process capability is increased due to too thick copper is avoided, and no etching lead is designed in the circuit pattern data in the step S6.
3. The method of claim 1, further comprising the step of: and (3) covering the dry film in S12, wherein the steps are as follows:
1): film pressing;
2): exposing;
3): and (6) developing.
4. The method of claim 1, further comprising the step of: in the S14, the concentration of potassium aurocyanide in an electroplating pool is 1.8g/L, the content of nickel cakes is less than 200ppm, the content of copper is less than 5ppm, the content of cobalt is 1.0-1.3g/L, the content of a light agent P is 2.5-6g/L, the temperature is 35-40 ℃, the current density is 0.2ASD-0.4ASD during electroplating, so that two surfaces of a gold layer to be electroplated are both electroplated with a gold layer, the gold thickness and the crystal roughness of the electroplated gold are confirmed by a first piece after electroplating is finished, and a bonding tension test, a 3M glue test and a gold thickness test are carried out on the electroplated gold area.
5. The method of claim 1, further comprising the step of: the concentration of the stripping solution in the S15 is 12%, the stripping temperature is controlled at 48-52 ℃, the stripping speed is 2m/min, the plating-resistant dry films on the double-sided packaging substrate are completely removed, the concentration of the micro-etching solution in the S16 is 90-120g/L, the temperature of the micro-etching solution is 28-32 ℃, and the pressure of the liquid medicine tank is 1.0-1.7Kg/cm2。
6. The method of claim 1, further comprising the step of: the step of operating the welding preventing layer of S17 is as follows:
1): performing solder mask pretreatment;
2): performing silk printing operation on a solder mask layer;
3): exposing and developing;
4): and (5) UV treatment.
7. A selectively plated package substrate without conductive lines obtained on the basis of the method according to any of claims 1 to 6, comprising a substrate (1), characterized in that: the circuit board is characterized in that the substrate (1) is provided with a through hole (2), and both sides of the substrate (1) are provided with circuit pattern layers (3).
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01303789A (en) * | 1988-06-01 | 1989-12-07 | Hitachi Ltd | Formation of partial thickening gold film of ceramic wiring substrate |
| CN1402607A (en) * | 2001-08-13 | 2003-03-12 | 实密科技股份有限公司 | Method for selectively plating metal by screen printing |
| CN105578778A (en) * | 2015-12-17 | 2016-05-11 | 江门崇达电路技术有限公司 | Manufacturing method of single-face local thick-gold plated PCB |
| CN110351955A (en) * | 2019-06-17 | 2019-10-18 | 江门崇达电路技术有限公司 | A kind of production method of the PCB with local electric thick gold PAD |
-
2021
- 2021-01-07 CN CN202110018001.9A patent/CN112351596A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01303789A (en) * | 1988-06-01 | 1989-12-07 | Hitachi Ltd | Formation of partial thickening gold film of ceramic wiring substrate |
| CN1402607A (en) * | 2001-08-13 | 2003-03-12 | 实密科技股份有限公司 | Method for selectively plating metal by screen printing |
| CN105578778A (en) * | 2015-12-17 | 2016-05-11 | 江门崇达电路技术有限公司 | Manufacturing method of single-face local thick-gold plated PCB |
| CN110351955A (en) * | 2019-06-17 | 2019-10-18 | 江门崇达电路技术有限公司 | A kind of production method of the PCB with local electric thick gold PAD |
Cited By (16)
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|---|---|---|---|---|
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| CN113597118A (en) * | 2021-09-28 | 2021-11-02 | 深圳和美精艺半导体科技股份有限公司 | Electroless plating lead gold plating process method |
| CN113597118B (en) * | 2021-09-28 | 2021-12-31 | 深圳和美精艺半导体科技股份有限公司 | Electroless plating lead gold plating process method |
| CN113613414A (en) * | 2021-09-30 | 2021-11-05 | 江门市和美精艺电子有限公司 | Packaging substrate of four-layer Nano SIM cards and manufacturing method thereof |
| CN113613414B (en) * | 2021-09-30 | 2021-12-31 | 江门市和美精艺电子有限公司 | Packaging substrate of four-layer Nano SIM cards and manufacturing method thereof |
| CN114007343A (en) * | 2021-10-22 | 2022-02-01 | 深圳明阳电路科技股份有限公司 | Printed Circuit Board (PCB) electric thick gold, PCB and manufacturing method thereof |
| CN114007343B (en) * | 2021-10-22 | 2024-05-17 | 深圳明阳电路科技股份有限公司 | Printed circuit board electro-thick gold, printed circuit board and manufacturing method thereof |
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