CN112350669A - Reconfigurable injection locking multi-mode single-ended output frequency multiplier for ultra-wideband millimeter waves - Google Patents
Reconfigurable injection locking multi-mode single-ended output frequency multiplier for ultra-wideband millimeter waves Download PDFInfo
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Abstract
The invention discloses a reconfigurable injection locking multi-mode single-ended output frequency multiplier for ultra-wideband millimeter waves, which comprises a frequency tripling module and a frequency doubling module; for a frequency tripling module, the frequency tripling module comprises direct current power supplies DC 1-DC 2, triodes PMOS 1-PMOS 3, triodes NMOS 1-NMOS 4, a transformer T1, a transformer T2, an inductor L1, an inductor L4, a capacitor C1 and a capacitor C2; for the frequency doubling module, the frequency doubling module comprises a direct current power supply DC3, a transistor NMOS 5-NMOS 10, an inductor L2 and a transistor PMOS 4. The invention has scientific structural design, can effectively solve the problems of small output bandwidth, poor phase noise, large chip area, low working efficiency and the like of the traditional 5G frequency source, realizes the design of a high-performance frequency source system, and has great production practice significance.
Description
Technical Field
The invention relates to the technical field of millimeter wave 5G communication chips, in particular to a reconfigurable injection locking multi-mode single-ended output frequency multiplier for ultra-wideband millimeter waves.
Background
Millimeter wave communication systems are favored by the academic and industrial circles due to their advantages of high communication rate, high availability, and the like. Taking the fifth generation mobile communication (5G) as an example, a plurality of developable frequency bands are deployed in all countries, for example, the china industry and informatization department approves 24.75-27.5GHz and 37-42.5GHz frequency bands for 5G research and development; the U.S. Federal communications Commission opened three primary communications bands, 28(27.5-28.35GHz), 37(37-38.6GHz) and 39(38.6-40 GHz). Therefore, if a radio frequency communication system covering multiple frequency bands, such as 24.75GHz-42.5GHz bandwidth, can be developed, the range of use and the availability of the system will be greatly increased. However, the bandwidth and phase noise of the frequency source in the rf front end limit the development of the whole communication system, and a new technology is urgently needed to expand the bandwidth on the premise of ensuring the phase noise output by the frequency source.
At present, most frequency source systems directly utilize high-frequency and broadband phase-locked loop (PLL) output signals as local oscillation sources, but in the mode, the design of an ultra-wideband VCO (voltage-controlled oscillator) faces challenges, and the requirements of 5G communication cannot be met in terms of output phase noise, working efficiency and stability.
Another common mode is to use a wideband frequency multiplier to N-multiply the output signal of a Phase Locked Loop (PLL), and the output bandwidth of a Voltage Controlled Oscillator (VCO) is further reduced compared to the former one, but it is challenging to design a wideband frequency multiplier, and a single frequency multiplication mode is difficult to achieve the wideband requirement of 24.75-42.5 GHz.
In addition, the application of the multi-mode frequency multiplier can reduce the output bandwidth of a Voltage Controlled Oscillator (VCO) to the maximum extent and optimize the phase noise output by a Phase Locked Loop (PLL), but the traditional multi-mode frequency multiplier is accompanied with multi-port output, circuits among different modes are mutually independent, and equivalently, a plurality of frequency multiplication chips are integrated in a system, so that the area of the chip is large, and the power consumption is increased. Meanwhile, the multi-port is not beneficial to the cascade connection of the back-end circuit.
In summary, in order to solve the problems of the working bandwidth, the phase noise, the working efficiency and the miniaturization of the 5G frequency source module, a technology is urgently needed to be provided at present, which can meet the requirements of the 5G communication system on high speed and low bit error rate, so that the frequency source develops towards a broadband and low phase noise.
Disclosure of Invention
The invention aims to provide a reconfigurable injection locking multi-mode single-ended output frequency multiplier for ultra-wideband millimeter waves, aiming at the technical defects in the prior art.
Therefore, the invention provides an ultra-wideband millimeter wave reconfigurable injection locking multi-mode single-ended output frequency multiplier, which comprises a frequency tripling module and a frequency doubling module;
for a frequency tripling module, the frequency tripling module comprises direct current power supplies DC 1-DC 2, triodes PMOS 1-PMOS 3, triodes NMOS 1-NMOS 4, a transformer T1, a transformer T2, an inductor L1, an inductor L4, a capacitor C1 and a capacitor C2;
the positive electrode of the direct-current power supply DC2 is connected with the source electrode of the triode PMOS 3;
the negative pole of the direct current power supply DC2 is grounded;
the drain of the triode PMOS3 is connected with the common mode point of the inductor L1;
two ends of the inductor L1 are respectively connected with the drains of the cross pair transistors NMOS1 and NMOS2 through the output coil of the transformer T1 and the output coil of the transformer T2;
the source of the NMOS1 and the source of the NMOS2 are grounded respectively;
the positive electrode of the direct-current power supply DC1 is respectively connected with the source electrode of the triode PMOS1 and the source electrode of the PMOS 2;
the grid electrode of the transistor PMOS1 is connected with the grid electrode of the transistor NMOPS 3;
the grid electrode of the transistor PMOS2 is connected with the grid electrode of the transistor NMOPS 4;
the grid electrode of the transistor PMOS1 and the grid electrode of the transistor NMOPS3 are connected with the fundamental wave signal output end of the signal source after intersecting and converging;
the grid electrode of the triode PMOS2 and the grid electrode of the triode NMOPS4 are connected with the fundamental wave signal output end of the signal source after intersecting and converging;
the drain electrode of the triode PMOS is connected with the drain electrode of the NMOPS3 through the input coil of the transformer T1;
the drain electrode of the triode PMOS2 is connected with the drain electrode of the NMOS4 through an input coil of a transformer T2;
the source electrode of the transistor NMOS3 and the source electrode of the transistor NMOS4 are grounded respectively;
the drain electrode of the transistor NMOS3 is grounded through a capacitor C1;
the drain electrode of the transistor NMOS4 is grounded through a capacitor C2;
for the frequency doubling module, the frequency doubling module comprises a direct current power supply DC3, a triode NMOS 5-NMOS 10, an inductor L2 and a triode PMOS 4;
the positive electrode of the direct-current power supply DC3 is connected with the source electrode of the triode PMOS 4;
the negative pole of the direct current power supply DC3 is grounded;
the drain of the PMOS4 is connected with the common mode point of the inductor L2;
two ends of the inductor L2 are respectively connected with the drains of the cross pair transistors NMOS7 and NMOS8, the drains of the injection triodes NMOS5 and NMOS6 and the drains of the DUMMY triodes NMOS9 and NMOS 10;
the grid of the NMOS5 and the grid of the NMOS6 are connected with the fundamental wave signal output end of the signal source;
the source of the NMOS5 and the source of the NMOS6 are grounded together;
the source of the NMOS7 and the source of the NMOS8 are grounded together;
the gates and sources of the DUMMY structure DUMMY transistors NMOS9 and NMOS10 are grounded after being crossed and converged.
Preferably, the output end of the signal source is respectively connected with one end of the capacitor C4 and one end of the inductor L3;
the other end of the capacitor C4 is grounded;
the other end of the inductor L3 is respectively connected with one end of a resistor R3 and one end of a capacitor C3;
the other end of the capacitor C3 is grounded;
the other end of the resistor R3 is connected to ground.
Preferably, DC power supplies DC1, DC2 and DC3 are used to provide a DC voltage of 1.2V, respectively.
Compared with the prior art, the reconfigurable injection locking multi-mode single-ended output frequency multiplier for the ultra-wideband millimeter wave is scientific in structural design, can effectively solve the problems of small output bandwidth, poor phase noise, large chip area, low working efficiency and the like of the traditional 5G frequency source, realizes the design of a high-performance frequency source system, and has great production practice significance.
Drawings
Fig. 1 is a circuit diagram of an ultra-wideband millimeter wave reconfigurable injection-locked multi-mode single-ended output frequency multiplier provided by the invention.
Detailed Description
In order to make the technical means for realizing the invention easier to understand, the following detailed description of the present application is made in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant application and are not limiting of the application. It should be noted that, for convenience of description, only the portions related to the present application are shown in the drawings.
It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.
Referring to fig. 1, the invention provides a reconfigurable injection locking multi-mode single-ended output frequency multiplier for ultra-wideband millimeter waves, which can realize frequency doubling or frequency tripling of input narrowband low-frequency signals, and specifically comprises a frequency tripling module and a frequency doubling module;
for a frequency tripling module, the frequency tripling module comprises direct current power supplies DC 1-DC 2, triodes PMOS 1-PMOS 3, triodes NMOS 1-NMOS 4, a transformer T1, a transformer T2, an inductor L1, an inductor L4, a capacitor C1 and a capacitor C2;
the positive electrode of the direct-current power supply DC2 is connected with the source electrode of the triode PMOS 3;
the negative pole of the direct current power supply DC2 is grounded;
the drain of the triode PMOS3 is connected with the common mode point of the inductor L1;
two ends of the inductor L1 are respectively connected with the drains of the cross pair transistors NMOS1 and NMOS2 through the output coil of the transformer T1 and the output coil of the transformer T2;
the source of NMOS1 and the source of NMOS2 are grounded, respectively.
The positive electrode of the direct-current power supply DC1 is respectively connected with the source electrode of the triode PMOS1 and the source electrode of the PMOS 2;
the grid electrode of the transistor PMOS1 is connected with the grid electrode of the transistor NMOPS 3;
the grid electrode of the transistor PMOS2 is connected with the grid electrode of the transistor NMOPS 4;
the grid electrode of the transistor PMOS1 and the grid electrode of the transistor NMOPS3 are connected with the fundamental wave signal output end of the signal source after intersecting and converging;
the grid electrode of the triode PMOS2 and the grid electrode of the triode NMOPS4 are connected with the fundamental wave signal output end of the signal source after intersecting and converging;
the drain electrode of the triode PMOS is connected with the drain electrode of the NMOPS3 through the input coil of the transformer T1;
the drain electrode of the triode PMOS2 is connected with the drain electrode of the NMOS4 through an input coil of a transformer T2;
the source electrode of the transistor NMOS3 and the source electrode of the transistor NMOS4 are grounded respectively;
the drain electrode of the transistor NMOS3 is grounded through a capacitor C1;
the drain electrode of the transistor NMOS4 is grounded through a capacitor C2;
for the frequency doubling module, the frequency doubling module comprises a direct current power supply DC3, a triode NMOS 5-NMOS 10, an inductor L2 and a triode PMOS 4;
the positive electrode of the direct-current power supply DC3 is connected with the source electrode of the triode PMOS 4;
the negative pole of the direct current power supply DC3 is grounded;
the drain of the PMOS4 is connected with the common mode point of the inductor L2;
two ends of the inductor L2 are respectively connected with the drains of the cross pair transistors NMOS7 and NMOS8, the drains of the injection triodes NMOS5 and NMOS6 and the drains of the DUMMY triodes NMOS9 and NMOS 10;
the grid of the NMOS5 and the grid of the NMOS6 are connected with the fundamental wave signal output end of the signal source;
the source of the NMOS5 and the source of the NMOS6 are grounded together;
the source of the NMOS7 and the source of the NMOS8 are grounded together;
the gates and sources of the DUMMY structure DUMMY transistors NMOS9 and NMOS10 are grounded after being crossed and converged.
In the invention, in a specific implementation, the output end of the signal source is respectively connected with one end of a capacitor C4 and one end of an inductor L3;
the other end of the capacitor C4 is grounded;
the other end of the inductor L3 is respectively connected with one end of a resistor R3 and one end of a capacitor C3;
the other end of the capacitor C3 is grounded;
the other end of the resistor R3 is connected to ground.
It should be noted that, in the present invention, the signal source is specifically an existing signal source, for example, an existing version-level frequency source system. For the invention, a edition-level frequency source system is adopted to provide an input signal, the edition-level frequency source system mainly generates a local oscillation signal of 11-15GHz by a phase-locked loop chip LMX2594 produced by Texas instruments and is input into a multimode frequency multiplier to provide a fundamental wave signal required by frequency multiplication.
In the present invention, referring to fig. 1, the gate of the transistor PMOS3 and the gate of the transistor PMOS4 are respectively dc-powered by 2K Ω bias resistors, which mainly provide bias for the PMOS3 and the PMOS4, so that the transistors enter the amplification region.
In the invention, in concrete implementation, direct current power supplies DC1, DC2 and DC3 are respectively used for providing direct current voltage of 1.2V.
It should be noted that, for the present invention, the present invention includes a frequency tripler module and a frequency doubler module, each operating mode is coupled and output through a differential inductor L3, one end of an inductor L3 is connected to 50 ohms, and the other end is connected to an external test device to output a required frequency doubler signal.
In the invention, for a frequency tripling module, a triode PMOS1 and an NMOS3, and a triode PMOS2 and an NMOS4 are injected, and a direct current power supply DC1 provides 1.2V direct current voltage respectively; the positive electrode of the direct current power supply DC1 is respectively connected with the sources of the PMOS1 and the PMOS 2; the fundamental wave signal output by the signal source is injected into the grids of the transistors PMOS1 and NMOS3 and the transistors PMOS2 and NMOS4, and the drains of the PMOS1 and the PMOS2 are respectively connected with the drains of the NMOPS3 and the NMOS4 through the transformers T1 and T2. For the present invention, the third harmonic signal generated by the transistors PMOS1 and NMOPS3 and PMOS2 and NMOS4 is coupled to the drains of the cross-coupled transistors NMOS1 and NMOS2 through transformers T1, T2.
In the invention, in order to further expand the high-frequency bandwidth and improve the suppression capability of the second harmonic, the frequency tripler module is designed to be connected with the drain electrodes of the NMOS3 and the NMOS4 in series with capacitors C1, C2 and L4, wherein the common mode point of the inductor L4 corresponds to the ground point of the second harmonic.
In the invention, for the frequency doubling module, the drain of the PMOS4 is connected with the common mode point of the inductor L2, and supplies power to the drains of the cross-coupled transistors NMOS7 and NMOS8, the drains of the injection transistors NMOS5 and NMOS6, and the drains of the DUMMY transistors NMOS9 and NMOS 10. The gates and sources of the DUMMY transistor NMOS9 and NMOS10 are commonly grounded.
In the invention, for the frequency doubling module, the fundamental wave signal output by the signal source is differentially injected into the gates of NMOS5 and NMOS6, the sources of NMOS5 and NMOS6 are commonly grounded, and the drains of NMOS5 and NMOS6 are connected with the drains of cross-coupled transistors NMOS7 and NMOS 8. Therefore, the second harmonic signal generated by the drains of NOMS5 and NMOS6 is injected into the drains of cross-pair NMOS7 and NMOS 8.
In the present invention, for practical implementation, the resistor R1 may be a 50 ohm resistor; the capacitances C3 and C4 may be 226Ff capacitances; capacitances C1 and C2 may be capacitances of 233 fF; inductor L1 may be a 240PH inductor; inductor L2 may be a 340PH inductor; the inductance L3 may be a 160PH inductance.
It should be noted that, for the present invention, three inductors L1, L2, and L3 in fig. 1 are in a mutual coupling relationship, and L1 and L2 are weakly coupled and can be represented by a coupling coefficient K1; the coupling between L1 and L3 can be represented by a coupling coefficient K3; the coupling coefficient between L2 and L3 may be represented by K2.
It should be noted that, in the specific implementation of the present invention, the circuit structure is implemented based on a CMOS 55nm process, and the frequency doubling mode and the frequency tripling mode both use the same six-order LC resonant network, so that the chip area is reduced while the bandwidth is extended. In order to realize the switching between different modes, the PMOS tube is adopted as a current source in both modes, and the switching between different modes is realized by controlling the grid voltage of the PMOS tube.
For the invention, the frequency tripling mode and the frequency doubling mode both use the same six-order LC resonant network to expand the bandwidth, and L1, L2 and L3 in FIG. 1 form the inductance part of the resonant network. The three inductors are mutually coupled, and the designed coupling coefficient K1 is 0.29; k2 is 0.45; k3 was 0.59. Wherein the coupling between L1 and L2 is weak at 0.29, so that the influence between the two modes is reduced as much as possible. The coupling between L1 and L3 and between L2 and L3 is increased, 0.59 and 0.45 respectively, raising the output power. L3 is the common coupling end of two kinds of modes, adopts the mode of difference output, will double frequency and triple frequency signal output, and for the test of convenient chip, the one end of difference port inserts ground resistance R1(50 ohm) in the chip inside, and the other end is exported the frequency spectrograph and is tested.
In order to more clearly understand the technical solution of the present invention, the first and third frequency multiplication modes of the operating mode of the present invention are described below.
When the grid voltage of the PMOS3 for controlling the power supply of the frequency tripling module is 0.48V, the PMOS3 tube is conducted, current passes through the cross pair tube NMOS1 and NMOS2 in the frequency tripling module, and the frequency tripling module starts to work.
For the invention, a compensation PMOS and NMOS cascade mode is adopted to generate abundant third harmonic. To further extend the operating bandwidth at high frequencies, the differential injection structure introduces a defected ground structure.
In fig. 1, PMOS1 and NMOS3 and transformer T1, PMOS2 and NMOS4 and transformer T2 form a differential injection structure, and the gates of PMOS1, PMOS2 and NMOS3, and NMOS4) inject a fundamental current, which is biased below a threshold voltage.
The invention sets the bias voltage of each PMOS tube to be 0.7V and the bias voltage of each NMOS tube to be 0.3V, and generates a large amount of harmonic current signals by utilizing the strong nonlinearity of the triode, wherein the third harmonic is coupled to the NMOS1 and the NMOS2 of the cross pair tube through the transformers T1 and T2, and the traction oscillator (VCO) is oscillated at the required third harmonic. In order to further expand the working bandwidth at a high frequency, a ground defect structure L4 and a ground defect structure C1(L4 and C2) are introduced into the differential injection structure, wherein the capacitors C1 and C2 also play a role in isolating direct current, a resonant network is formed by L4 introduced by the ground defect and parasitic capacitors of a P tube and an N tube in the injection structure, the LC network resonates at the high frequency by adjusting the size of the inductor, the third harmonic injection current is further improved, and the locking bandwidth at the high frequency is improved.
The frequency tripling module of the invention can meet the frequency doubling requirement of 33.5-44.4 GHz.
In the invention, the other function of the defected ground structure is to make the phase of the second harmonic far away from the vicinity of 0 and pull down the real part of the LC resonance impedance at the second harmonic to reduce the second harmonic; a common mode point is introduced for the second harmonic of the input signal.
Two, frequency doubling mode.
When the grid voltage of the PMOS4 for controlling the power supply of the frequency doubling module is 0.4V, the PMOS4 tube is conducted, the current passes through the crossed pair tube in the frequency doubling, and the frequency doubling starts to work.
The present invention employs a PUSH-PUSH architecture (PUSH-PUSH). The injection structure only needs single-end injection, the other end of the injection structure is connected with a virtual space structure (DUMMY), and the parasitic capacitance in the DUMMY structure is utilized to reduce the LC resonance frequency, so that the free oscillation state of the oscillator (VCO) is positioned at a low frequency, and the frequency doubling requirement of 23-34GHz is met. At this time, the triode in the frequency tripling structure is in a non-working state, and the parasitic capacitance of the triode is used as a part of the LC matching network, so that the working bandwidth of low-frequency output is further improved.
It should be noted that the PUSH-PUSH structure (PUSH-PUSH) mainly comprises NMOS5 and NMOS6, the fundamental wave signal is injected into the gates of NMOS5 and NMOS6, the drains of the transistors are connected, the sources are grounded, the gates of the transistors are set to 0.55V, and the threshold voltage is close to, so as to generate a strong second harmonic current. The signal enters the drain of the triode, the fundamental wave voltage is mutually counteracted, the second harmonic voltage is mutually superposed, and the second harmonic current injected into the cross geminate transistors NMOS7 and NMOS8 is further enhanced
NMOS9 and NMOS10 in FIG. 1 form a DUMMY structure, and triodes with the same size as NMOS5 and NMOS6 are adopted to form symmetrical structures at two sides of the oscillator, so that the differential symmetrical characteristic of the circuit is ensured. The gates and the sources of the NMOS9 and the NMOS10 are connected and grounded, and the drains are connected to the drain of the NMOS 8.
In summary, for the present invention, the same chip can fulfill the operating requirement of frequency doubling or frequency tripling by only controlling the gate voltage of the PMOS transistor (i.e. PMOS3 and PMOS 4).
For the present invention, in particular operation, the design of the circuit mainly comprises the following steps:
first, the generation modes of the second harmonic and the third harmonic are determined.
Then, according to the adopted process, a module circuit is designed, and the free oscillation frequency of the module circuit is adjusted to be within the required frequency range.
Then, according to actual requirements, a multi-stage LC resonance network is adopted, and the adjustment is carried out by matching with a parasitic capacitor in the injection structure, so that the bandwidth is expanded.
The output structure is then optimized to avoid the use of buffers, depending on the low power requirements of the use.
The invention provides an ultra-wideband millimeter wave reconfigurable injection locking multi-mode single-ended output frequency multiplier, which relates to a high-performance radio frequency millimeter wave frequency source technology, is based on a reconfigurable technology, and is also based on an injection locking technology and a mode switching odd-even frequency multiplication technology.
Compared with the prior art, the injection locking multi-mode single-ended output frequency multiplier for ultra-wideband millimeter wave reconstruction provided by the invention has the following beneficial effects:
1. by adopting a double-time and triple-time switchable continuous frequency multiplier, the frequency doubling of a low-frequency narrow-band input signal of 11.5-17GHz (38.5 percent of effective bandwidth) can be realized, and a millimeter-wave broadband output signal of 23-44.5GHz (63.7 percent of effective bandwidth) is generated; the double-frequency mode and the triple-frequency mode use a common input and output end, the size of the chip is reduced, and one chip can meet the requirement of 5G communication.
2. Effectively reducing the output bandwidth of VCO (voltage controlled oscillator) in PLL (phase locked loop), reducing the design difficulty and improving the phase noise
3. And the switching of secondary and tertiary frequency multiplication can be completed only by changing the grid voltage of the power supply PMOS without introducing any calibration structure.
4. The output has no buffer (namely buffer), the power consumption is reduced, and the output bandwidth is not limited. Wherein, the highest power consumption of frequency tripling work is 7mW, and the highest power consumption of frequency doubling work is 11 mW.
In summary, compared with the prior art, the injection locking multi-mode single-ended output frequency multiplier for ultra-wideband millimeter wave reconstruction provided by the invention has scientific structural design, can effectively solve the problems of small output bandwidth, poor phase noise, large chip area, low working efficiency and the like of the traditional 5G frequency source, realizes the design of a high-performance frequency source system, and has great production practice significance.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (3)
1. The injection locking multi-mode single-ended output frequency multiplier for ultra-wideband millimeter wave reconstruction is characterized by comprising a frequency tripling module and a frequency doubling module;
for a frequency tripling module, the frequency tripling module comprises direct current power supplies DC 1-DC 2, triodes PMOS 1-PMOS 3, triodes NMOS 1-NMOS 4, a transformer T1, a transformer T2, an inductor L1, an inductor L4, a capacitor C1 and a capacitor C2;
the positive electrode of the direct-current power supply DC2 is connected with the source electrode of the triode PMOS 3;
the negative pole of the direct current power supply DC2 is grounded;
the drain of the triode PMOS3 is connected with the common mode point of the inductor L1;
two ends of the inductor L1 are respectively connected with the drains of the cross pair transistors NMOS1 and NMOS2 through the output coil of the transformer T1 and the output coil of the transformer T2;
the source of the NMOS1 and the source of the NMOS2 are grounded respectively;
the positive electrode of the direct-current power supply DC1 is respectively connected with the source electrode of the triode PMOS1 and the source electrode of the PMOS 2;
the grid electrode of the transistor PMOS1 is connected with the grid electrode of the transistor NMOPS 3;
the grid electrode of the transistor PMOS2 is connected with the grid electrode of the transistor NMOPS 4;
the grid electrode of the transistor PMOS1 and the grid electrode of the transistor NMOPS3 are connected with the fundamental wave signal output end of the signal source after intersecting and converging;
the grid electrode of the triode PMOS2 and the grid electrode of the triode NMOPS4 are connected with the fundamental wave signal output end of the signal source after intersecting and converging;
the drain electrode of the triode PMOS is connected with the drain electrode of the NMOPS3 through the input coil of the transformer T1;
the drain electrode of the triode PMOS2 is connected with the drain electrode of the NMOS4 through an input coil of a transformer T2;
the source electrode of the transistor NMOS3 and the source electrode of the transistor NMOS4 are grounded respectively;
the drain electrode of the transistor NMOS3 is grounded through a capacitor C1;
the drain electrode of the transistor NMOS4 is grounded through a capacitor C2;
for the frequency doubling module, the frequency doubling module comprises a direct current power supply DC3, a triode NMOS 5-NMOS 10, an inductor L2 and a triode PMOS 4;
the positive electrode of the direct-current power supply DC3 is connected with the source electrode of the triode PMOS 4;
the negative pole of the direct current power supply DC3 is grounded;
the drain of the PMOS4 is connected with the common mode point of the inductor L2;
two ends of the inductor L2 are respectively connected with the drains of the cross pair transistors NMOS7 and NMOS8, the drains of the injection triodes NMOS5 and NMOS6 and the drains of the DUMMY triodes NMOS9 and NMOS 10;
the grid of the NMOS5 and the grid of the NMOS6 are connected with the fundamental wave signal output end of the signal source;
the source of the NMOS5 and the source of the NMOS6 are grounded together;
the source of the NMOS7 and the source of the NMOS8 are grounded together;
the gates and sources of the DUMMY structure DUMMY transistors NMOS9 and NMOS10 are grounded after being crossed and converged.
2. The single-ended output frequency multiplier for ultra-wideband millimeter wave reconfigurable injection locking multi-mode according to claim 1, wherein the output terminal of the signal source is connected to one end of a capacitor C4 and one end of an inductor L3, respectively;
the other end of the capacitor C4 is grounded;
the other end of the inductor L3 is respectively connected with one end of a resistor R3 and one end of a capacitor C3;
the other end of the capacitor C3 is grounded;
the other end of the resistor R3 is connected to ground.
3. The single-ended output frequency multiplier for ultra-wideband millimeter wave reconfigurable injection locking multi-mode according to claim 1 or 2, wherein direct current power supplies DC1, DC2 and DC3 are respectively used for providing a direct current voltage of 1.2V.
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| US20180159516A1 (en) * | 2016-12-05 | 2018-06-07 | The Regents Of The University Of California | High-efficiency frequency doubler with a compensated transformer-based input balun |
| CN109510597A (en) * | 2018-12-19 | 2019-03-22 | 成都瑞迪威科技有限公司 | A kind of wideband enhanced injection locking quadrupler |
| US20190229675A1 (en) * | 2018-01-25 | 2019-07-25 | University College Dublin | Multi-Stage Sub-THz Frequency Generator Incorporating Injection Locking |
| CN110784178A (en) * | 2019-10-28 | 2020-02-11 | 东南大学 | Broadband injection locking frequency multiplier |
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| US20180159516A1 (en) * | 2016-12-05 | 2018-06-07 | The Regents Of The University Of California | High-efficiency frequency doubler with a compensated transformer-based input balun |
| CN107093984A (en) * | 2017-04-20 | 2017-08-25 | 中国电子技术标准化研究院 | One kind injection locking frequency tripler |
| US20190229675A1 (en) * | 2018-01-25 | 2019-07-25 | University College Dublin | Multi-Stage Sub-THz Frequency Generator Incorporating Injection Locking |
| CN109510597A (en) * | 2018-12-19 | 2019-03-22 | 成都瑞迪威科技有限公司 | A kind of wideband enhanced injection locking quadrupler |
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| WO2022226462A3 (en) * | 2021-04-22 | 2022-12-01 | Qualcomm Incorporated | Multimode frequency multiplier |
| US11677390B2 (en) | 2021-04-22 | 2023-06-13 | Qualcomm Incorporated | Multimode frequency multiplier |
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