CN117559915B - Dual-path inductance-based dual-mode oscillator - Google Patents
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- 230000008859 change Effects 0.000 description 3
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- OUXCBPLFCPMLQZ-WOPPDYDQSA-N 4-amino-1-[(2r,3s,4s,5r)-4-hydroxy-5-(hydroxymethyl)-3-methyloxolan-2-yl]-5-iodopyrimidin-2-one Chemical compound C[C@H]1[C@H](O)[C@@H](CO)O[C@H]1N1C(=O)N=C(N)C(I)=C1 OUXCBPLFCPMLQZ-WOPPDYDQSA-N 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
- H03B5/08—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
- H03B5/12—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
- H03B5/1237—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device comprising means for varying the frequency of the generator
- H03B5/1256—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device comprising means for varying the frequency of the generator the means comprising a variable inductance
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
- H03B5/02—Details
- H03B5/04—Modifications of generator to compensate for variations in physical values, e.g. power supply, load, temperature
Abstract
The invention discloses a dual-mode oscillator based on dual-path inductance, which comprises: the first negative resistance pair, the second negative resistance pair, the third negative resistance pair and the double-path inductor are respectively connected with the first negative resistance pair and the second negative resistance pair, the first negative resistance pair and the second negative resistance pair are connected with the double-path inductor, and each negative resistance pair can supplement energy consumed by the resonant cavity during operation. The current path of the dual-path inductor can be changed by controlling the working state of each negative resistance pair, so that the equivalent inductance value is changed, broadband coverage is realized, and meanwhile, the phase noise is reduced due to higher resonant cavity impedance.
Description
Technical Field
The invention belongs to the technical field of oscillators, and particularly relates to a dual-mode oscillator based on dual-path inductance.
Background
The oscillator is a core of a frequency source system, is a device for converting direct-current power supply energy into alternating-current signals with specific frequency, is widely applied to various fields such as wireless communication, automatic control, remote control mobile equipment and the like, and is mainly used for generating local oscillation signals, and the frequency range of the signals determines the working bandwidth of the wireless communication system.
The prior art broadband oscillator is generally composed of two LC oscillators, a coupling capacitor and a mode switching circuit, and the two LC oscillators are made to operate in two different modes of in-phase and anti-phase coupling by controlling the switch in the mode switching circuit, so as to expand the bandwidth. However, as the operating frequency increases, the parasitic coupling capacitance compresses the frequency tuning range and can degrade the oscillator phase noise, resulting in the inability of existing oscillators to meet the requirements of broadband applications.
Therefore, how to achieve broadband coverage and low phase noise at high frequency at the same time is a technical problem to be solved by those skilled in the art.
Disclosure of Invention
The invention aims to solve the technical problem that the oscillator in the prior art is difficult to realize broadband coverage and low phase noise at the same time under high frequency.
In order to achieve the above technical object, the present invention provides a dual-path inductance-based dual-mode oscillator, which includes a first negative resistance pair, a second negative resistance pair, a third negative resistance pair and a dual-path inductance, wherein the first negative resistance pair, the second negative resistance pair and the third negative resistance pair are used for generating a high-frequency band oscillation signal, and the dual-path inductance-based dual-mode oscillator comprises:
the dual-path inductor comprises a first inductor, a second inductor, a third inductor, a fourth inductor, a fifth inductor and a sixth inductor, wherein the second end of the fifth inductor and the first end of the sixth inductor are connected and are also connected with a power supply end, the second end of the first inductor is connected with the first end of the second inductor, the second end of the second inductor is connected with the first end of the third inductor, the second end of the third inductor is connected with the first end of the fourth inductor, the first end of the fifth inductor is connected with the joint of the first inductor and the second inductor, and the second end of the sixth inductor is connected with the joint of the third inductor and the fourth inductor;
the first end of the first negative resistance pair is connected with the first end of the first inductor, and the second end of the first negative resistance pair is connected with the second end of the second inductor;
the first end of the second negative resistance pair is connected with the second end of the fourth inductor, and the second end of the second negative resistance pair is connected with the first end of the third inductor;
the first end of the third negative resistance pair is connected with the third end of the first negative resistance pair, and the second end of the third negative resistance pair is connected with the third end of the second negative resistance pair.
Further, the first negative resistance pair specifically includes a first MOS transistor, a second MOS transistor, and a third MOS transistor, wherein:
the source electrode of the first MOS tube is grounded, the gate electrode of the first MOS tube is connected with a bias voltage end, the drain electrode of the first MOS tube is respectively connected with the source electrode of the second MOS tube and the source electrode of the third MOS tube, and the connecting part is also used as the third end of the first negative resistance pair;
the drain electrode end of the second MOS tube is connected with the gate electrode end of the third MOS tube, and the connecting part is used as the first end of the first negative resistance pair;
the drain end of the third MOS tube is connected with the gate end of the second MOS tube, and the connection part is used as the second end of the first negative resistance pair.
Further, a first capacitor and a second capacitor are connected in series between the first end and the second end of the first negative resistance pair.
Further, the second negative resistance pair specifically includes a fourth MOS transistor, a fifth MOS transistor, and a sixth MOS transistor, wherein:
the source electrode of the fourth MOS tube is grounded, the gate electrode of the fourth MOS tube is connected with a bias voltage end, the drain electrode of the fourth MOS tube is respectively connected with the source electrode of the fifth MOS tube and the source electrode of the sixth MOS tube, and the connecting part is also used as a third end of the second negative resistance pair;
the drain end of the fifth MOS tube is connected with the gate end of the sixth MOS tube, and the connection part is used as the first end of the second negative resistance pair;
the drain end of the sixth MOS tube is connected with the gate end of the fifth MOS tube, and the connection part is used as the second end of the second negative resistance pair.
Further, a third capacitor and a fourth capacitor are connected in series between the first end and the second end of the second negative resistance pair.
Further, the third negative resistance pair specifically includes a seventh MOS transistor, an eighth MOS transistor, and a ninth MOS transistor, wherein:
the source electrode of the seventh MOS tube is grounded, the gate electrode of the seventh MOS tube is connected with a bias voltage end, and the drain electrode of the seventh MOS tube is respectively connected with the source electrode of the eighth MOS tube and the source electrode of the ninth MOS tube;
the drain end of the eighth MOS tube is connected with the gate end of the ninth MOS tube, and the connection part is used as the first end of the third negative resistance pair;
the drain terminal of the ninth MOS transistor is connected with the gate terminal of the eighth MOS transistor, and the connection is used as the second terminal of the third negative resistance pair.
Further, a fifth capacitor and a sixth capacitor are connected in series between the first end and the second end of the third negative resistance pair.
Further, all the MOS tubes are N-type MOS tubes.
Compared with the prior art, the dual-mode oscillator based on the dual-path inductance comprises a first negative resistance pair, a second negative resistance pair, a third negative resistance pair and a dual-path inductance, wherein the third negative resistance pair is respectively connected with the first negative resistance pair and the second negative resistance pair, the first negative resistance pair and the second negative resistance pair are connected with the dual-path inductance, the first negative resistance pair, the second negative resistance pair and the third negative resistance pair are used for generating a high-frequency band oscillation signal, the dual-path inductance can change an equivalent inductance value through changing a current path, broadband coverage is realized, the impedance of a resonant cavity is high, and low phase noise can be simultaneously obtained under high frequency.
Drawings
In order to more clearly illustrate the embodiments of the present description or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments described in the present description, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a dual-path inductance-based dual-mode oscillator according to an embodiment of the present disclosure;
FIG. 2 is a simulation diagram of the operating frequency range in the embodiment of the present disclosure;
fig. 3 is a phase noise simulation diagram in the embodiment of the present specification.
Detailed Description
In order to enable those of ordinary skill in the art to better understand the technical solutions in the present specification, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
While the present description provides the following embodiments or the device structures shown in the drawings, more or fewer module units may be included in the device based on conventional or non-creative labor, or after partial merging, and there is no logically necessary causal relationship structure, the module structures of these devices are not limited to the module structures shown in the embodiments or the drawings. The module structure may be sequentially or parallel executed according to the embodiment or the module structure shown in the drawings when the actual device, the server or the end product is applied.
The dual-path inductance-based dual-mode oscillator provided in the embodiments of the present disclosure may be applied to various required devices, as shown in fig. 1, where the dual-mode oscillator includes a first negative resistance pair, a second negative resistance pair, a third negative resistance pair, and a dual-path inductance, and the first negative resistance pair, the second negative resistance pair, and the third negative resistance pair are used to generate a high-frequency band oscillation signal, where:
the dual-path inductor comprises a first inductor L1, a second inductor L2, a third inductor L3, a fourth inductor L4, a fifth inductor L5 and a sixth inductor L6, wherein the second end of the fifth inductor L5 and the first end of the sixth inductor L6 are connected and are also connected with a power supply end, the second end of the first inductor L1 is connected with the first end of the second inductor L2, the second end of the second inductor L2 is connected with the first end of the third inductor L3, the second end of the third inductor L3 is connected with the first end of the fourth inductor L4, the first end of the fifth inductor L5 is connected with the joint of the first inductor L1 and the second inductor L2, and the second end of the sixth inductor L6 is connected with the joint of the third inductor L3 and the fourth inductor L4;
the first end of the first negative resistance pair is connected with the first end of the first inductor L1, and the second end of the first negative resistance pair is connected with the second end of the second inductor L2;
the first end of the second negative resistance pair is connected with the second end of the fourth inductor L4, and the second end of the second negative resistance pair is connected with the first end of the third inductor L3;
the first end of the third negative resistance pair is connected with the third end of the first negative resistance pair, and the second end of the third negative resistance pair is connected with the third end of the second negative resistance pair.
Specifically, the dual-mode oscillator in the present application mainly comprises three negative resistance pairs and a dual-path inductor, the dual-path inductor can change equivalent inductance value by changing the flowing direction of current, so as to realize switching of working frequency, the first negative resistance pair and the second negative resistance pair are used for generating high-frequency band oscillating signals, in the high-frequency band working mode, the first negative resistance pair and the second negative resistance pair are turned on, the power supply end supplies power, that is, the bias current source first MOS tube M1 and the bias current source fourth MOS tube M4 are turned on, so as to turn on the first negative resistance pair and the second negative resistance pair, the first inductor L1 and the second inductor L2 form a first oscillator, the second negative resistance pair, the third inductor L3 and the fourth inductor L4 form a second oscillator, the first oscillator and the second oscillator are structurally connected in series, and at this time, the oscillating frequency f H Can be determined by the following formula:
，
wherein C is a capacitor.
Since the two oscillators are now operating in series, the phase noise is also reduced by 3dB.
In the low-frequency band working mode, only the third negative resistance pair is started to work, and the three negative resistances can be usedThe bias current source switch is connected to control the on/off of the corresponding negative resistance pair, because the grid ends of the first MOS tube M1, the fourth MOS tube M4 and the seventh MOS tube M7 are connected with the bias voltage end, the three MOS tubes can be used as bias current sources, the third negative resistance pair and all the inductors in the double-path inductor form an oscillator, and the oscillation frequency f at the moment L Can be determined by the following formula:
，
since the frequency is reduced by increasing the inductance at this time, the impedance of the resonant cavity is high, thereby achieving a technical effect of improving the phase noise performance.
In this embodiment of the present application, the first negative resistance pair specifically includes a first MOS transistor M1, a second MOS transistor M2, and a third MOS transistor M3, where:
the source electrode of the first MOS tube M1 is grounded, the gate electrode of the first MOS tube M1 is connected with a bias voltage end, the drain electrode of the first MOS tube M1 is respectively connected with the source electrode of the second MOS tube M2 and the source electrode of the third MOS tube M3, and the connection part is also used as the third end of the first negative resistance pair;
the drain end of the second MOS tube M2 is connected with the gate end of the third MOS tube M3, and the connection part is used as the first end of the first negative resistance pair;
the drain end of the third MOS transistor M3 is connected to the gate end of the second MOS transistor M2, and the junction is used as the second end of the first negative resistance pair.
The structure of the second negative resistance pair and the third negative resistance pair are consistent with that of the first negative resistance pair, and the second negative resistance pair specifically comprises a fourth MOS tube M4, a fifth MOS tube M5 and a sixth MOS tube M6, wherein:
the source electrode of the fourth MOS tube M4 is grounded, the gate electrode of the fourth MOS tube M4 is connected with a bias voltage end, the drain electrode of the fourth MOS tube M4 is respectively connected with the source electrode of the fifth MOS tube M5 and the source electrode of the sixth MOS tube M6, and the connection part is also used as a third end of the second negative resistance pair;
the drain end of the fifth MOS tube M5 is connected with the gate end of the sixth MOS tube M6, and the connection part is used as the first end of the second negative resistance pair;
the drain terminal of the sixth MOS transistor M6 is connected to the gate terminal of the fifth MOS transistor M5, and the connection is used as the second terminal of the second negative resistance pair.
The third negative resistance pair specifically comprises a seventh MOS tube M7, an eighth MOS tube M8 and a ninth MOS tube M9, wherein:
the source electrode of the seventh MOS tube M7 is grounded, the gate electrode of the seventh MOS tube M7 is connected with a bias voltage terminal Vb1, and the drain electrode of the seventh MOS tube M7 is respectively connected with the source electrode of the eighth MOS tube M8 and the source electrode of the ninth MOS tube M9;
the drain terminal of the eighth MOS transistor M8 is connected to the gate terminal of the ninth MOS transistor M9, and the connection is used as the first terminal of the third negative resistance pair;
the drain terminal of the ninth MOS transistor M9 is connected to the gate terminal of the eighth MOS transistor M8, and the connection is used as the second terminal of the third negative resistance pair.
Specifically, the MOS tubes are N-type MOS tubes, the N-type MOS tubes are used as tail current sources and negative resistance pairs, the output voltage swing is increased, meanwhile, the MOS tubes have the characteristics of low voltage and low power consumption, wherein the grid electrode of the first MOS tube M1 is connected with the bias voltage end Vb, the first MOS tube M1 can play the role of the bias current sources and can control the current size through the voltage of the grid end, the source electrode end of the first MOS tube M1 is grounded, the drain electrode end of the first MOS tube M1 is respectively connected with the source ends of the second MOS tube M2 and the third MOS tube M3, the second MOS tube M2 and the third MOS tube M3 are connected in a cross coupling mode, negative resistance can be formed to supplement the energy consumed by the resonant cavity,
in addition, a first capacitor C1 and a second capacitor C2 are further connected in series between the first end and the second end of the first negative resistance pair, a third capacitor C3 and a fourth capacitor C4 are further connected in series between the first end and the second end of the second negative resistance pair, a fifth capacitor C5 and a sixth capacitor C6 are further connected in series between the first end and the second end of the third negative resistance pair, and the first negative resistance pair and the second negative resistance pair are turned on or only the third negative resistance pair is turned on to operate, so that the first negative resistance pair and the second negative resistance pair can be regarded as primary adjustment, the second negative resistance pair can be regarded as secondary adjustment of the capacitors, the capacitors comprise a switch capacitor array and a variable capacitor, and the frequency adjustment and continuous tuning can be realized through the capacitors.
According to the dual-mode oscillator, the working state of the negative resistance pair is controlled, so that inductance paths through which current flows are different, the change of inductance values is realized, the working frequency is changed, the bandwidth is expanded, positive coupling among inductors in the dual-path inductor enhances magnetic flux passing through the inductor, the impedance of a resonant cavity is improved, and phase noise in the oscillator is restrained.
Simulation experiments are carried out based on the dual-mode oscillator:
the simulation experiment element adopts an SMIC 40nm RF CMOS process, and the simulation circuit is built on the basis of a cadence IC617 simulation experiment platform under a Redhat system.
The simulation of the invention adopts a spectrum RF simulation tool to simulate the circuit of the invention, the given power supply voltage VDD is 0.6V, the working temperature is 27 ℃, and the bias voltages Vb and Vb1 are 0.5V.
Simulation 1, under the above working conditions, a spectrum RF simulation tool is adopted, corresponding output ports are respectively added at two output ends of each negative resistance unit, and simulation is performed on the invention, and the result is shown in fig. 2, and fig. 2 is a simulation diagram of the working frequency range in the simulation 1, wherein the abscissa represents a frequency control word, and the ordinate represents the frequency of an oscillation signal in GHz. As can be seen from FIG. 2, the simulation frequency range is 9.1-18.9 GHz.
Simulation 2, under the above working conditions, a spectrum RF simulation tool is adopted, corresponding output ports are respectively added at two output ends of each negative resistance unit, and the PSS+PNOISE simulation is performed on the invention, and the result is shown in fig. 3, and fig. 3 is a phase noise simulation diagram in the simulation 2, wherein the abscissa is offset frequency, the unit is Hz, the ordinate is phase noise of an output signal, and the unit is dBc/Hz. As can be seen from FIG. 3, the phase noise at each working frequency of the invention is smaller than-113 dBc/Hz at the frequency offset of 1MHz, the frequency band of the low-frequency working mode in the simulation is 9.7GHz, the frequency band of the high-frequency working mode is 18.9GHz in the frequency range of the simulation 1.
Simulation results show that the dual-mode oscillator provided by the invention has the advantages of ultra-wideband and low phase noise while ensuring low power consumption and low voltage.
The above-described embodiments of the apparatus are merely illustrative, and the division of the modules is merely a logical function division, and there may be additional divisions when actually implemented, for example, multiple units or plug-ins may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.
In this specification, each embodiment is described in a progressive manner, and identical and similar parts of each embodiment are referred to each other, and each embodiment is mainly described in a different manner from other embodiments. In particular, for system embodiments, the description is relatively simple as it is substantially similar to method embodiments, and reference is made to the section of the method embodiments where relevant. In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present specification. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.
Those of ordinary skill in the art will recognize that the embodiments described herein are for the purpose of aiding the reader in understanding the principles of the present invention and should be understood that the scope of the invention is not limited to such specific statements and embodiments. Those of ordinary skill in the art can make various other specific modifications and combinations from the teachings of the present disclosure without departing from the spirit thereof, and such modifications and combinations remain within the scope of the present disclosure.
Claims (2)
1. A dual-path inductance-based dual-mode oscillator, comprising a first negative resistance pair, a second negative resistance pair, a third negative resistance pair, and a dual-path inductance, the first negative resistance pair, the second negative resistance pair, and the third negative resistance pair being configured to generate a high-band oscillating signal, wherein:
the dual-path inductor comprises a first inductor, a second inductor, a third inductor, a fourth inductor, a fifth inductor and a sixth inductor, wherein the first end of the fifth inductor and the first end of the sixth inductor are connected and are also connected with a power supply end, the second end of the first inductor is connected with the first end of the second inductor, the second end of the second inductor is connected with the first end of the third inductor, the second end of the third inductor is connected with the first end of the fourth inductor, the other end of the fifth inductor is connected with the joint of the first inductor and the second inductor, and the other end of the sixth inductor is connected with the joint of the third inductor and the fourth inductor;
the first end of the first negative resistance pair is connected with the first end of the first inductor, and the second end of the first negative resistance pair is connected with the second end of the second inductor;
the first end of the second negative resistance pair is connected with the second end of the fourth inductor, and the second end of the second negative resistance pair is connected with the first end of the third inductor;
the first end of the third negative resistance pair is connected with the third end of the first negative resistance pair, and the second end of the third negative resistance pair is connected with the third end of the second negative resistance pair;
the first negative resistance pair specifically comprises a first MOS tube, a second MOS tube and a third MOS tube, wherein:
the source electrode of the first MOS tube is grounded, the gate electrode of the first MOS tube is connected with a bias voltage end, the drain electrode of the first MOS tube is respectively connected with the source electrode of the second MOS tube and the source electrode of the third MOS tube, and the connecting part is also used as the third end of the first negative resistance pair;
the drain electrode end of the second MOS tube is connected with the gate electrode end of the third MOS tube, and the connecting part is used as the first end of the first negative resistance pair;
the drain end of the third MOS tube is connected with the gate end of the second MOS tube, the connection is used as the second end of the first negative resistance pair, and a first capacitor and a second capacitor are connected in series between the first end and the second end of the first negative resistance pair;
the second negative resistance pair specifically comprises a fourth MOS tube, a fifth MOS tube and a sixth MOS tube, wherein:
the source electrode of the fourth MOS tube is grounded, the gate electrode of the fourth MOS tube is connected with a bias voltage end, the drain electrode of the fourth MOS tube is respectively connected with the source electrode of the fifth MOS tube and the source electrode of the sixth MOS tube, and the connecting part is also used as a third end of the second negative resistance pair;
the drain end of the fifth MOS tube is connected with the gate end of the sixth MOS tube, and the connection part is used as the first end of the second negative resistance pair;
the drain electrode end of the sixth MOS tube is connected with the gate electrode end of the fifth MOS tube, the connection is used as a second end of the second negative resistance pair, and a third capacitor and a fourth capacitor are further connected in series between the first end and the second end of the second negative resistance pair;
the third negative resistance pair specifically comprises a seventh MOS tube, an eighth MOS tube and a ninth MOS tube, wherein:
the source electrode of the seventh MOS tube is grounded, the gate electrode of the seventh MOS tube is connected with a bias voltage end, and the drain electrode of the seventh MOS tube is respectively connected with the source electrode of the eighth MOS tube and the source electrode of the ninth MOS tube;
the drain end of the eighth MOS tube is connected with the gate end of the ninth MOS tube, and the connection part is used as the first end of the third negative resistance pair;
the drain terminal of the ninth MOS tube is connected with the gate terminal of the eighth MOS tube, the junction is used as the second terminal of the third negative resistance pair, and a fifth capacitor and a sixth capacitor are further connected in series between the first terminal and the second terminal of the third negative resistance pair.
2. The dual-path inductance-based dual-mode oscillator of claim 1, wherein all MOS transistors are N-type MOS transistors.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1889365A (en) * | 2006-08-01 | 2007-01-03 | 华东师范大学 | Radio frequency double-channel voltage controlled oscillator based on central tapped inductive switch |
| CN105827237A (en) * | 2015-01-06 | 2016-08-03 | 中芯国际集成电路制造(上海)有限公司 | Time delay circuit and voltage-controlled oscillator |
| CN110690897A (en) * | 2019-09-30 | 2020-01-14 | 西安电子科技大学 | Low-power injection locking frequency divider with wide frequency band locking range |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4282412B2 (en) * | 2003-09-02 | 2009-06-24 | 株式会社東芝 | Current source circuit |
| US7737795B2 (en) * | 2006-11-30 | 2010-06-15 | Rangan Giri N K | Voltage controlled oscillator |
-
2024
- 2024-01-12 CN CN202410044070.0A patent/CN117559915B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1889365A (en) * | 2006-08-01 | 2007-01-03 | 华东师范大学 | Radio frequency double-channel voltage controlled oscillator based on central tapped inductive switch |
| CN105827237A (en) * | 2015-01-06 | 2016-08-03 | 中芯国际集成电路制造(上海)有限公司 | Time delay circuit and voltage-controlled oscillator |
| CN110690897A (en) * | 2019-09-30 | 2020-01-14 | 西安电子科技大学 | Low-power injection locking frequency divider with wide frequency band locking range |
Non-Patent Citations (2)
| Title |
|---|
| 一种1.84GHz低噪声电容电感压控振荡器;张为;张旭;刘洋;;北京理工大学学报;20101215(第12期) * |
| 正交相位输出压控振荡器的低相位噪声优化设计;祁楠;李国林;;电子技术应用;20080806(第08期) * |
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