CN111884595B - Second harmonic enhanced broadband three-frequency divider - Google Patents
Second harmonic enhanced broadband three-frequency divider Download PDFInfo
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- CN111884595B CN111884595B CN202010746591.2A CN202010746591A CN111884595B CN 111884595 B CN111884595 B CN 111884595B CN 202010746591 A CN202010746591 A CN 202010746591A CN 111884595 B CN111884595 B CN 111884595B
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Abstract
The invention discloses a second harmonic enhanced broadband divider, which comprises a first inductor, a second inductor, a third inductor, a fourth inductor, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a first bias voltage, a second bias voltage and a third bias voltage. The invention uses a differential pair and a transformer to enhance the intensity of second harmonic in the frequency division of three frequencies and increase the frequency range of the frequency divider. In addition, the invention is not required to be frequency-tuned, is used in a phase-locked loop circuit and is easier to apply.
Description
Technical Field
The invention relates to the field of millimeter wave front end circuits of electronic communication technology, in particular to a second harmonic enhanced broadband divider three-way frequency divider.
Background
In recent years, the fifth generation (5G) communication is favored by the academics industry, and the millimeter wave transceiver is an indispensable loop of the 5G communication system, wherein one key circuit is the first-stage frequency divider, i.e., the injection-locked frequency divider, following the voltage-controlled oscillator in the phase-locked loop. The frequency divider belongs to a front-end module in a phase-locked loop system, has the working frequency consistent with the frequency of an oscillator, and can track the frequency change of the oscillator and divide the frequency of the oscillator. The most important performance indicator for an injection locked frequency divider is the input signal bandwidth.
In the existing scheme, 1 common mode point second harmonic wave injected by difference is utilized to perform Frequency division by Two on the basis of the original Three Frequency division, the input Frequency range is increased, and the input Frequency range does not exceed 1GHz under the condition of no tuning (1 Wu J, Chen C, Kao H, et al, diode-by-Three Injection-Locked diode Combined With diode-by-Two Locking [ J ]. IEEE Microwave and Wireless Components Letters, 2013, 23(11): 590-592.). [2] A30 GHz Injection locking frequency divider With a frequency range of 4.5GHz is realized by adopting a switch Injection structure (2) Seow B, Huang T, Wu C, et al A Low-Voltage 30-GHz CMOS divider-by-Three ILFD With Injection-Switched Cross-Coupled Pair Technique [ J ]. IEEE Transactions on Microwave Theory and Techniques, 2017, 65(5): 1560-; [3] a double-injection triplexer With tail injection is proposed, With a relative bandwidth of 8.5% ([ 3] Abdulaziz M, Forsberg T, Tomanen M, et al A10-mW mm-Wave Phase-Locked Loop With Improved Lock Time in 28-nm FD-SOI CMOS [ J ]. IEEE Transactions on Microwave Theory and Techniques, 2019, 67(4): 1588-1600.). The frequency divider is suitable for a millimeter wave communication front-end circuit. The frequency division bandwidth of the existing frequency divider is not large enough, a varactor is needed for frequency tuning, and the relative bandwidth of an input frequency range is small under the condition of no tuning.
Disclosure of Invention
The invention aims to enhance the intensity of second harmonic in a frequency divider for dividing three frequencies, increase the bandwidth of an input signal and realize a broadband frequency divider under the condition of no frequency tuning
The invention is realized by at least one of the following technical schemes.
A second harmonic enhancement type broadband division three-frequency divider comprises a first inductor L1x, a second inductor L1y, a third inductor L2, a fourth inductor L3, a first capacitor C1x, a second capacitor C1y, a third capacitor C2x, a fourth capacitor C2y, a fifth capacitor C3x, a sixth capacitor C3y, a seventh capacitor C4, a first transistor M1x, a second transistor M1y, a third transistor M2x, a fourth transistor M2y, a fifth transistor M3x, a sixth transistor M3y, a seventh transistor M4, an eighth transistor M5x, a ninth transistor M5x, a first resistor R1x, a second resistor R1x, a third resistor R3x, a fourth resistor R3x, a fifth resistor R3x, a first bias voltage VB, a second bias voltage VB x and a third bias voltage x;
the positive terminals of the first inductor L1x and the second inductor L1y are connected with a first power supply VDD 1;
one end of the first capacitor C1x is connected to the negative terminal of the first inductor L1x, and the other end is grounded;
one end of the second capacitor C1y is connected to the negative terminal of the second inductor L1y, and the other end is grounded;
the sources of the eighth transistor M5x and the ninth transistor M5y are connected to the CM point, the drain of the eighth transistor M5x is connected to the negative terminal of the first inductor L1x, the drain of the ninth transistor M5y is connected to the negative terminal of the second inductor L1y, and the eighth transistor M5x and the ninth transistor M5y form a differential injection tube;
one end of the third capacitor C2x is connected to the positive VINP of the input signal, and the other end is connected to the gate of the eighth transistor M5 x;
one end of the fourth resistor R3x is connected to the gate of the eighth transistor M5x, and the other end is connected to the first bias voltage VB;
one end of the fourth capacitor C2y is connected to the positive VINN of the input signal, and the other end is connected to the gate of the ninth transistor M5 y;
one end of the fifth resistor R3y is connected with the gate of the ninth transistor M5y, and the other end is connected with the first bias voltage VB;
one end of the seventh capacitor C4 is connected to the positive terminal of the third inductor L2, and the other end is connected to the common mode point CM;
one end of the third resistor R2 is connected with the second bias voltage VB1, and the other end is connected with the gate of the seventh transistor M4;
the negative end of the third inductor L2 is connected with the gate of a seventh transistor M4;
the source of the seventh transistor M4 is connected to the drain of the eighth transistor M5x, and the drain of the seventh transistor M4 is connected to the drain of the ninth transistor M5 y;
the positive end of the fourth inductor L3 is connected with a power supply VDD2, the negative end of the fourth inductor L3 is connected with the drains of the third transistor M2x and the fourth transistor M2y, and the sources of the third transistor M2x and the fourth transistor M2y are grounded;
the third inductor L2 and the fourth inductor L3 form a transformer T1, the coupling coefficient is k, and the third transistor M2x and the fourth transistor M2y form a push-push differential pair;
one end of the fifth capacitor C3x is connected to the drain of the eighth transistor M5x, and the other end is connected to the gate of the third transistor M2 x;
one end of the sixth capacitor C3y is connected to the drain of the ninth transistor M5y, and the other end is connected to the gate of the fourth transistor M2 y;
one end of the second resistor R1x is connected to the gate of the third transistor M2x, and the other end is connected to the third bias voltage VB 2;
one end of the first resistor R1y is connected with the gate of the fourth transistor M2y, and the other end is connected with the third bias voltage VB 2;
the drain of the first transistor M1x is connected to the drain of the eighth transistor M5x, the gate is connected to the drain of the second transistor M1y, and the source is grounded;
the drain of the second transistor M1y is connected to the drain of the ninth transistor M5y, the gate is connected to the drain of the first transistor M1x, and the source is grounded;
the first transistor M1x and the second transistor M1y form a cross-coupled pair, and the cross-coupled pair, the first inductor L1x, the second inductor L1y, the first capacitor C1x and the second capacitor C1y form an oscillator;
the grid electrode of the fifth transistor M3x is connected with the drain electrode of the first transistor M1x, the source electrode is grounded, and the drain electrode is an open-drain output OUTP; the gate of the sixth transistor M3y is connected to the drain of the third transistor M2x, the source is grounded, and the drain is the open-drain output OUTN; the fifth transistor M3x and the sixth transistor M3y are open drain output buffer stages.
The core circuit of the injection locking frequency divider of the invention oscillates near omega 0, a differential signal is injected through the gates of the eighth transistor M5x and the ninth transistor M5y, and the injection signal is 3 omega0. When the oscillator starts oscillation, the second harmonic frequency 2 omega will be generated at the common mode point CM (CM point)0. Taking the eighth transistor M5x as an example, when the gate injection frequency of the eighth transistor M5x is 3 ω0Will be related to 2 omega of the point CM0Mixing the signals to generate 5 omega0And ω0Signals of two frequencies, but with oscillator oscillating at ω0Near, 5 ω0The frequencies are filtered out. And finally, dividing three by three.
Except that the eighth transistor M5x and the ninth transistor M5y divide the input signal by three, the seventh transistor M4 divides the second harmonic of the CM point by two, so that one path of frequency division by two is added on the basis of the original three-frequency division, and the three-frequency division performance of the whole circuit is enhanced.
The invention aims to improve the second harmonic intensity of a CM point. The Push-Push differential pair doubles the frequency of the oscillation signal omega 0 and is coupled to the CM point through the transformer T1, so that compared with the traditional structure, the invention enhances the second harmonic of the CM point.
Compared with the prior art, the invention has the beneficial effects that:
the invention utilizes the push-push differential pair and the transformer to enhance the intensity of second harmonic in the frequency divider for dividing three frequencies and increase the frequency range of the frequency divider. In addition, the invention is not required to be frequency-tuned, is used in a phase-locked loop circuit and is easier to apply.
Drawings
FIG. 1 is a schematic diagram of a frequency divider of the present embodiment;
FIG. 2 is a diagram showing the second harmonic voltage amplitude at the point CM in the circuit of the present embodiment;
fig. 3 is a sensitivity graph of the present embodiment.
Detailed Description
The present invention will be described in further detail with reference to examples and drawings, but the present invention is not limited to these examples.
The second-harmonic enhancement type broadband divider shown in fig. 1 includes a first inductor L1x, a second inductor L1y, a third inductor L2, a fourth inductor L3, a first capacitor C1x, a second capacitor C1y, a third capacitor C2x, a fourth capacitor C2y, a fifth capacitor C3x, a sixth capacitor C3y, a seventh capacitor C4, a first transistor M1x, a second transistor M1y, a third transistor M2x, a fourth transistor M2y, a fifth transistor M3x, a sixth transistor M3y, a seventh transistor M4, an eighth transistor M5x, a ninth transistor M5x, a first resistor R1x, a second resistor R1x, a third resistor R x, a fourth resistor R3x, a fifth resistor R3x, a first bias voltage VB, a second bias voltage VB, and a third bias voltage x;
the positive terminals of the first inductor L1x and the second inductor L1y are connected with a first power supply VDD 1;
one end of the first capacitor C1x is connected to the negative terminal of the first inductor L1x, and the other end is grounded;
one end of the second capacitor C1y is connected to the negative terminal of the second inductor L1y, and the other end is grounded;
the sources of the eighth transistor M5x and the ninth transistor M5y are connected to the CM point, the drain of the eighth transistor M5x is connected to the negative terminal of the first inductor L1x, the drain of the ninth transistor M5y is connected to the negative terminal of the second inductor L1y, and the eighth transistor M5x and the ninth transistor M5y form a differential injection tube;
one end of the third capacitor C2x is connected to the positive VINP of the input signal, and the other end is connected to the gate of the eighth transistor M5 x;
one end of the fourth resistor R3x is connected to the gate of the eighth transistor M5x, and the other end is connected to the first bias voltage VB;
one end of the fourth capacitor C2y is connected to the positive VINN of the input signal, and the other end is connected to the gate of the ninth transistor M5 y;
one end of the fifth resistor R3y is connected with the gate of the ninth transistor M5y, and the other end is connected with the first bias voltage VB;
one end of the seventh capacitor C4 is connected to the positive terminal of the third inductor L2, and the other end is connected to the common mode point CM;
one end of the third resistor R2 is connected with the second bias voltage VB1, and the other end is connected with the gate of the seventh transistor M4;
the negative end of the third inductor L2 is connected with the gate of a seventh transistor M4;
the source of the seventh transistor M4 is connected to the drain of the eighth transistor M5x, and the drain of the seventh transistor M4 is connected to the drain of the ninth transistor M5 y;
the positive end of the fourth inductor L3 is connected with a power supply VDD2, the negative end of the fourth inductor L3 is connected with the drains of the third transistor M2x and the fourth transistor M2y, and the sources of the third transistor M2x and the fourth transistor M2y are grounded;
the third inductor L2 and the fourth inductor L3 form a transformer T1, the coupling coefficient is k, and the third transistor M2x and the fourth transistor M2y form a push-push differential pair;
one end of the fifth capacitor C3x is connected to the drain of the eighth transistor M5x, and the other end is connected to the gate of the third transistor M2 x;
one end of the sixth capacitor C3y is connected to the drain of the ninth transistor M5y, and the other end is connected to the gate of the fourth transistor M2 y;
one end of the second resistor R1x is connected to the gate of the third transistor M2x, and the other end is connected to the third bias voltage VB 2;
one end of the first resistor R1y is connected with the gate of the fourth transistor M2y, and the other end is connected with the third bias voltage VB 2;
the drain of the first transistor M1x is connected to the drain of the eighth transistor M5x, the gate is connected to the drain of the second transistor M1y, and the source is grounded;
the drain of the second transistor M1y is connected to the drain of the ninth transistor M5y, the gate is connected to the drain of the first transistor M1x, and the source is grounded;
the first transistor M1x and the second transistor M1y form a cross-coupled pair, and the cross-coupled pair, the first inductor L1x, the second inductor L1y, the first capacitor C1x and the second capacitor C1y form an oscillator;
the grid electrode of the fifth transistor M3x is connected with the drain electrode of the first transistor M1x, the source electrode is grounded, and the drain electrode is an open-drain output OUTP; the gate of the sixth transistor M3y is connected to the drain of the third transistor M2x, the source is grounded, and the drain is the open-drain output OUTN; the fifth transistor M3x and the sixth transistor M3y are open drain output buffer stages.
When the core circuit of the injection locking frequency divider oscillates near omega 0, the differential signal is injected through the gates of the eighth transistor M5x and the ninth transistor M5y, and the injection signal is 3 omega0. When the oscillator starts oscillation, the second harmonic frequency 2 omega will be generated at the common mode point CM (CM point)0. Taking the eighth transistor M5x as an example, when the gate injection frequency of the eighth transistor M5x is 3 ω0Will be related to 2 omega of the point CM0Mixing the signals to generate 5 omega0And ω0Signals of two frequencies, but with oscillator oscillating at ω0Near, 5 ω0The frequencies are filtered out. And finally, dividing three by three.
Except that the eighth transistor M5x and the ninth transistor M5y divide the input signal by three, the seventh transistor M4 divides the second harmonic of the CM point by two, so that one path of frequency division by two is added on the basis of the original three-frequency division, and the three-frequency division performance of the whole circuit is enhanced.
The invention improves the second harmonic intensity of the CM point. The Push-Push differential pair doubles the frequency of the oscillation signal omega 0 and is coupled to the CM point through a transformer T1, so that the second harmonic of the CM point is enhanced. As shown in fig. 2, the second harmonic CM2 voltage amplitude, which is the CM point within the entire frequency band, can be up to 210 mV. On one hand, the mixing performance of the differential pair (namely, the performance of dividing by three) is enhanced, and on the other hand, the mixing performance of M4 (namely, the performance of dividing by two) is enhanced, so that the frequency dividing range of the whole frequency divider is further improved. As shown in fig. 3, which is a sensitivity curve of the frequency divider, the frequency range of the frequency divider is 24.24-30.75 GHz and the relative bandwidth is 23.7% when 0dBm of power is injected.
The above embodiments are preferred embodiments of the present invention, but the present invention is not limited to the above embodiments, and any other changes, modifications, substitutions, combinations, and simplifications which do not depart from the spirit and principle of the present invention should be construed as equivalents thereof, and all such changes, modifications, substitutions, combinations, and simplifications are intended to be included in the scope of the present invention.
Claims (5)
1. A second harmonic enhancement type broadband division three-frequency divider is characterized by comprising a first inductor L1x, a second inductor L1y, a third inductor L2, a fourth inductor L3, a first capacitor C1x, a second capacitor C1y, a third capacitor C2x, a fourth capacitor C2y, a fifth capacitor C3x, a sixth capacitor C3y, a seventh capacitor C4, a first transistor M1x, a second transistor M1y, a third transistor M2x, a fourth transistor M2y, a fifth transistor M3x, a sixth transistor M3 6852, a seventh transistor M4, an eighth transistor M5x, a ninth transistor M5x, a first resistor R1x, a second resistor R1x, a third resistor R3x, a fourth resistor R3x, a fifth resistor R3x, a first resistor VB x, a second resistor VB x and a third bias voltage x;
the positive terminals of the first inductor L1x and the second inductor L1y are connected with a first power supply VDD 1;
one end of the first capacitor C1x is connected to the negative terminal of the first inductor L1x, and the other end is grounded;
one end of the second capacitor C1y is connected to the negative terminal of the second inductor L1y, and the other end is grounded;
the sources of the eighth transistor M5x and the ninth transistor M5y are connected to the point CM, the drain of the eighth transistor M5x is connected to the negative terminal of the first inductor L1x, the drain of the ninth transistor M5y is connected to the negative terminal of the second inductor L1y, and the eighth transistor M5x and the ninth transistor M5y form a differential injection tube;
one end of the third capacitor C2x is connected to the positive VINP of the input signal, and the other end is connected to the gate of the eighth transistor M5 x;
one end of the fourth resistor R3x is connected to the gate of the eighth transistor M5x, and the other end is connected to the first bias voltage VB;
one end of the fourth capacitor C2y is connected to the positive VINN of the input signal, and the other end is connected to the gate of the ninth transistor M5 y;
one end of the fifth resistor R3y is connected to the gate of the ninth transistor M5y, and the other end is connected to the first bias voltage VB;
one end of the seventh capacitor C4 is connected to the positive terminal of the third inductor L2, and the other end is connected to the common mode point CM;
one end of the third resistor R2 is connected with the second bias voltage VB1, and the other end is connected with the gate of the seventh transistor M4;
the negative end of the third inductor L2 is connected to the gate of the seventh transistor M4;
the source of the seventh transistor M4 is connected to the drain of the eighth transistor M5x, and the drain of the seventh transistor M4 is connected to the drain of the ninth transistor M5 y;
the positive end of the fourth inductor L3 is connected with a power supply VDD2, the negative end of the fourth inductor L3 is connected with the drains of the third transistor M2x and the fourth transistor M2y, and the sources of the third transistor M2x and the fourth transistor M2y are grounded; the positive terminals of the third inductor L2 and the fourth inductor L3 are positively coupled to each other;
one end of the fifth capacitor C3x is connected to the drain of the eighth transistor M5x, and the other end is connected to the gate of the third transistor M2 x;
one end of the sixth capacitor C3y is connected to the drain of the ninth transistor M5y, and the other end is connected to the gate of the fourth transistor M2 y;
one end of the second resistor R1x is connected to the gate of the third transistor M2x, and the other end is connected to the third bias voltage VB 2;
one end of the first resistor R1y is connected with the gate of the fourth transistor M2y, and the other end is connected with the third bias voltage VB 2;
the drain of the first transistor M1x is connected to the drain of the eighth transistor M5x, the gate is connected to the drain of the second transistor M1y, and the source is grounded;
the drain of the second transistor M1y is connected to the drain of the ninth transistor M5y, the gate is connected to the drain of the first transistor M1x, and the source is grounded;
the grid electrode of the fifth transistor M3x is connected with the drain electrode of the first transistor M1x, the source electrode is grounded, and the drain electrode is an open-drain output OUTP; the gate of the sixth transistor M3y is connected to the drain of the third transistor M2x, the source is grounded, and the drain is an open-drain output OUTN; the fifth transistor M3x and the sixth transistor M3y are open drain output buffer stages.
2. The second-harmonic-enhanced wideband divider according to claim 1, wherein the third inductor L2 and the fourth inductor L3 form a transformer T1 with a coupling coefficient of k.
3. The second-harmonic-enhanced wideband divider three-way divider according to claim 2, wherein the third transistor M2x and the fourth transistor M2y form a push-push differential pair.
4. The second-harmonic enhancement type wideband divider three-way divider according to claim 3, wherein the first transistor M1x and the second transistor M1y form a cross-coupled pair.
5. The second-harmonic-enhanced wideband divider according to claim 4, wherein the cross-coupled pair, the first inductor L1x, the second inductor L1y, the first capacitor C1x, and the second capacitor C1y form an oscillator.
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