JP2020195058A - Voltage control oscillator - Google Patents

Abstract

To provide a voltage control oscillator that has high power efficiency and can decrease a corner frequency.SOLUTION: A voltage control oscillator 5 that oscillates at a frequency in accordance with the applied control voltage and outputs a differential oscillation signal includes a pair of transistors M1 and M2 having their gates and drains cross-connected to each other through capacitors 53A and 53B, a varactor 54 connected between the drains of the pair of transistors M1 and M2 and changing in electrostatic capacitance due to the control voltage, a pair of harmonic resonators 51A and 51B that is connected between output terminals 56A and 56B of the differential oscillation signals and the drains of the pair of transistors M1 and M2, and resonates with the harmonic wave of the oscillation frequency of the pair of transistors M1 and M2.SELECTED DRAWING: Figure 3

Description

The present invention relates to an oscillator, and more particularly to a voltage controlled oscillator whose oscillation frequency changes depending on an applied voltage.

A voltage controlled oscillator is used as a basic element of a phase locked loop (PLL), and is widely used as a local oscillator of a wireless transmitter or a wireless receiver. In particular, a voltage controlled oscillator used as a local oscillator is required to have low power consumption and large output power. One approach is to eliminate the oscillator output buffer and optimize the load impedance of the oscillator core to achieve high output power, low phase noise and high power efficiency (DC / RF efficiency) (eg). , See Non-Patent Document 1). On the other hand, in general, the in-band phase noise of an oscillator increases in proportion to the square of the oscillation frequency, so that the phase noise of the local oscillator affects the performance of wireless communication equipment that handles high-frequency RF (Radio Frequency) signals in the millimeter wave band or higher. It has a big impact. Therefore, as another approach, a harmonic resonator is provided in the output portion of the oscillator to reduce the corner frequency, which is the boundary between the third-order harmonic region and the second-order harmonic region of the fundamental frequency, to reduce the phase noise of the oscillator. We are trying to reduce it (see, for example, Non-Patent Document 2).

H. Khatibi et al., “An Efficient High-Power Fundamental Oscillator Above fmax / 2: A Systematic Sesign,” IEEE Trans. Microw. Theory Tech., Vol. 65, no. 11, pp. 4176-4189, Nov. 2017. M. Shahmohammadi et al., “A 1 / f Noise Upconversion Reduction Technique for Voltage-Biased RF CMOS Oscillators,” IEEE J. Solid-State Circuits, vol. 51, no. 11, pp. 2610-2623, Nov. 2016 ..

As described above, there are technologies for improving power efficiency and lowering the corner frequency for voltage controlled oscillators, but there is no technology for solving these problems at once.

Therefore, an object of the present invention is to provide a voltage controlled oscillator having high power efficiency and capable of lowering a corner frequency.

A voltage controlled oscillator according to one aspect of the present invention is a voltage controlled oscillator that oscillates at a frequency corresponding to a given control voltage and outputs a differential oscillation signal, in which a gate and a drain pass through a capacitor. A pair of transistors that are cross-connected to each other, a varicap that is connected between the drains of the pair of transistors and whose capacitance changes depending on the control voltage, and between each drain of the pair of transistors and the output terminal of the differential oscillation signal. It is provided with a pair of harmonic resonators that are connected to and resonate with the harmonics of the oscillation frequency of the pair of transistors.

According to the present invention, it is possible to output a high-frequency oscillation signal with high output power, low phase noise, and high power efficiency without providing an output buffer, and it is possible to reduce the corner frequency.

Block diagram of a subsampling phase-locked loop provided with a voltage controlled oscillator according to an embodiment of the present invention. Circuit diagram of the part related to subsampling phase comparison in the subsampling phase-locked loop of FIG. Circuit diagram of a voltage controlled oscillator according to an embodiment of the present invention A graph showing the simulation results of the input impedance of the harmonic resonator in the voltage controlled oscillator of FIG. Graph of output power during self-propelled oscillation Graph of power consumption during self-propelled oscillation Graph of 10kHz offset phase noise during self-propelled oscillation Graph of 10MHz offset phase noise during self-propelled oscillation Graph of phase noise during self-propelled oscillation Graph of phase noise in various modes

Hereinafter, embodiments will be described in detail with reference to the drawings as appropriate. However, more detailed explanation than necessary may be omitted. For example, detailed explanations of already well-known matters and duplicate explanations for substantially the same configuration may be omitted. This is to avoid unnecessary redundancy of the following description and to facilitate the understanding of those skilled in the art. It should be noted that the inventor provides the accompanying drawings and the following description in order for those skilled in the art to fully understand the present invention, and is not intended to limit the subject matter described in the claims by these. Absent.

<< Embodiment of Subsampling Phase-Locked Loop >>
FIG. 1 is a block diagram of a subsampling phase-locked loop (SSPLL) including a voltage controlled oscillator according to an embodiment of the present invention. The SSPLL10 according to the present embodiment includes a 1/2 divider 1A, a 1/6 divider 1B, a phase frequency comparator (PFD) 2, a charge pump (CP) 3, and a loop filter (LF) 4. , A voltage controlled oscillator (VCO) 5, an injection synchronous frequency divider (ILFD) 6A, a 1/3 divider 6B, a 1 / N division period 6C, and two subsampling phase comparators (SSPD). It includes 7A and 7B and two subsampling charge pumps (SCSPs) 8A and 8B. These circuit elements can be formed on a semiconductor chip. For example, the SSPLL10 multiplies the frequency of the input 1.4 GHz reference oscillation signal REF and outputs a 45 GHz differential oscillation signal OUT / OUTB.

The 1/2 frequency divider 1A is a circuit element that divides the input REF by 1/2 and outputs a differential frequency division reference clock signal. The duty ratio of the frequency divider reference clock signal output from the 1/2 frequency divider 1A is preferably 50%. The 1/2 divider 1A that outputs such a clock signal having a detail ratio of 50% can be easily configured by a binary counter or the like using a flip-flop circuit. The 1/6 divider 1B is a circuit element that receives a differential frequency divider reference clock signal output from the 1/2 divider 1A and further divides it by 1/6.

The PFD2 is a frequency divider reference clock signal output from the 1/6 divider 1B (this signal is a signal obtained by dividing the REF by 1/12) and a divider output from the 1 / N divider 6C. It is a circuit element that receives a feedback oscillation signal (this signal is a signal obtained by dividing OUT / OUTB by 1 / 12N) and outputs a phase difference pulse signal corresponding to the phase difference of these signals.

The CP3 is a circuit element that receives a phase difference pulse signal output from the PFD 2 and outputs a current corresponding to the phase difference pulse signal. The LF4 is a circuit element that converts the current output from the CP3 and the SCSP8A and 8B into a voltage. Specifically, the LF4 can be configured by a low-pass filter composed of a resistance element and a capacitor.

The VCO 5 is a circuit element that oscillates at a frequency corresponding to a given control voltage and outputs a differential oscillation signal OUT / OUTB. The voltage converted by LF4 is given to VCO5 as the control voltage of VCO5.

The ILFD6A is a circuit element that receives a differential feedback oscillation signal fed back from the VCO 5 and divides it. That is, the ILFD6A acts as a prescaler for feeding back the oscillation signal generated by the VCO5 to the PFD2. The division ratio of ILFD6A is, for example, 4. The differential feedback oscillation signal is not the differential oscillation signal OUT / OUTB itself output from the VCO5, but a signal different from the oscillation signal OUT / OUTB extracted from the inside of the VCO5.

The 1/3 divider 6B is a circuit element that receives the frequency division feedback oscillation signal output from the ILFD6A and further divides it by 1/3. The 1 / N frequency divider 6C is a circuit element that receives the frequency division feedback oscillation signal output from the 1/3 frequency divider 6B and further divides it by 1 / N. The frequency division ratio N of the 1 / N frequency divider 6C can be switched by appropriately selecting an arbitrary value from, for example, 32, 33, 34, and 35.

The SSPD7A returns from one of the differential division reference clock signals output from the 1/2 frequency divider 1A (for convenience, this signal is referred to as a positive phase signal of the differential division reference clock signal) and VCO5. The differential feedback oscillation signal (this signal is the same as the signal input to the ILFD6A) is input, and the phase difference signal representing the phase difference between the positive phase signal and the differential feedback oscillation signal and the said It is a circuit element that outputs a pulse Pul that does not overlap with a positive phase signal. The SSPD7B returns from the other side of the differential division reference clock signal output from the 1/2 frequency divider 1A (for convenience, this signal is referred to as a reverse phase signal of the differential division reference clock signal) and VCO5. The differential feedback oscillation signal (this signal is the same as the signal input to the ILFD6A) is input, and the phase difference signal representing the phase difference between the opposite phase signal and the differential feedback oscillation signal and the said It is a circuit element that outputs a pulse Pul that does not overlap with a reverse phase signal.

The SCSP8A is a circuit element in which a phase difference signal and a pulse Pul are input from the SSPD7A, and a current corresponding to the phase difference signal is output while the pulse Pul is on. The SCSP8B is a circuit element in which a phase difference signal and a pulse Pul are input from the SSPD7B, and a current corresponding to the phase difference signal is output while the pulse Pul is on. That is, the SCSP 8A outputs a current corresponding to the phase difference between the positive phase signal of the frequency dividing reference clock signal and the feedback oscillation signal, and the SCSP 8B corresponds to the phase difference between the negative phase signal of the frequency dividing reference clock signal and the feedback oscillation signal. Outputs the current. Then, the currents output from the SCSPs 8A and 8B are converted into a voltage by the LF4 and become the control voltage of the VCO5.

FIG. 2 is a circuit diagram of a portion related to subsampling phase comparison in SSPLL10. The SSPD 7A and 7B include six transistors M1 to M6, capacitors 71A and 71B, and a pulsar generator 72. The source of transistor M1, the source of transistor M2, and the drain of transistor M3 are connected to each other, and SSPD _IN, which is one of the differential feedback oscillation signals fed back from VCO5, is connected to the drain of transistor M1 to the train of transistor M2. The SSPD _INB, which is the other side of the differential feedback oscillation signal fed back from the VCO5, is connected, the gate of the transistor M2 is grounded, and in the SSPD7A, the differential output from the 1/2 divider 1A to the gate of the transistor M1. The reverse-phase signal CKB of the frequency-dividing reference clock signal is connected, and the positive-phase signal CK of the differential frequency-dividing reference clock signal output from the 1/2 frequency divider 1A is connected to the gate of the transistor M3. Is connected to the gate of transistor M1 and CKB is connected to the gate of transistor M3. The source of transistor M4, the source of transistor M5 and the drain of transistor M6 are connected to each other, SSPD _INB is connected to the drain of transistor M4, SSPD _IN is connected to the train of transistor M5, the gate of transistor M5 is grounded, SSPD7A In SSPD7B, the CKB is connected to the gate of the transistor M4, the CK is connected to the gate of the transistor M6, the CK is connected to the gate of the transistor M4, and the CKB is connected to the gate of the transistor M6. One end of the capacitors 71A and 71B is connected to each source of the transistors M3 and M6, and the other end is grounded. The voltage signals V _samP / V _samN charged in the capacitors 71A and 71B in SSPD7A are given to SCSP8A as a phase signal indicating the phase difference between CK and SSPD _IN / SSPD _INB, and the voltage charged in capacitors 71A and 71B in SSPD7B. The signal V _samP / V _samN is given to the SCSP 8B as a phase signal representing the phase difference between the CKB and the SSPD _IN / SSPD _INB . The pulsar generator 72 is a circuit element that generates Pul from the delay signal of CK in SSPD7A and generates Pul from the delay signal of CKB in SSPD7B.

-Operation and effect-
The operation of SSPLL10 having the above configuration is as follows. If the phase difference between the REF and OUT / OUTB is relatively large at the start of operation or when switching the frequency division ratio of the 1 / N frequency divider 6C, the 1/2 frequency divider 1A and 1/6 frequency divider The part consisting of the device 1B, PFD2, CP3, LF4, VCO5, ILFD6A, 1/3 frequency divider 6B and 1 / N frequency divider 6C, that is, the loop that divides the output of VCO5 and returns it mainly functions. The VCO5 is feedback-controlled so that the phase of OUT / OUTB substantially matches the phase of REF. As a result, the SSPLL 10 performs the same phase lock operation as a general PLL, and the loop gain can be increased at the initial stage of the phase synchronization operation.

When the phase of OUT / OUTB roughly matches the phase of REF, this time, the part consisting of 1/2 dividers 1A, SSPD7A and 7B, SCSP8A and 8B, LF4 and VCO5, that is, the output of VCO5 is divided. The loop that feeds back as it is without going through the device mainly functions, and the VCO 5 is feedback-controlled so that the phase of OUT / OUTB matches the phase of REF. At this time, each of the SSPD & CP composed of SSPD7A and SSCP8A and the SSPD & CP composed of SSPD7B and SSCP8B perform subsampling operations in synchronization with CK and CKB obtained by dividing the REF by 1/2, respectively, but these two SSPD & CPs complement each other. By operating, SSPD7A and 7B and SCSP8A and 8B perform subsampling operation in a pseudo-double frequency of CK / CKB as a whole, that is, substantially phase-locked to REF. Generally, the in-band phase noise of SSPLL is inversely proportional to the frequency of the reference clock signal and the pulse width of Pul, and the loop gain is proportional to the frequency of the reference clock signal. The SSPLL10 has a 1/2 frequency divider 1A arranged in the first stage to divide the REF by 1/2. However, since the above two SSPD & CPs perform sampling operation at twice the frequency of CK / CKB as a whole, the SSPLL10 is a REF. The in-band phase noise can be lowered and the loop gain can be improved without being affected by the division of 1/2.

<< Embodiment of voltage controlled oscillator >>
In general, the phase noise S of the VCO can be expressed by the following Leeson equation.
Here, F is an empirical parameter, k is the Boltzmann constant, T is the absolute temperature, P _S is the average power loss due to the resistance component of the tank circuit, f ₀ is the oscillation frequency, Delta] f is the offset frequency from the carrier frequency, Delta] f 1 _{/ f3} is the corner frequency that is the boundary between the ^3rd harmonic 1 / f ³ region and the 2nd harmonic 1 / f ² region, and _QL is the load Q value of the tank circuit. From this equation, the lower the VCO phase noise S (Delta] f) is to increase the _{P S,} it can be seen that it lowered the Δf _{1 / f3.}

FIG. 3 is a circuit diagram of a voltage controlled oscillator according to an embodiment of the present invention. Generally, the VCO 5 according to the present embodiment includes a pair of transistors M1 and M2, a pair of harmonic resonators 51A and 51B, and a pair of buffers 52A and 52B. The gate and drain of the transistors M1 and M2 are cross-connected to each other via capacitors 53A and 53B, and a bias voltage _Vg is applied to each gate. A varicap 54 is connected between the drains of the transistors M1 and M2. The varicap 54 is a circuit element whose capacitance changes depending on the applied voltage. A control voltage V _{tune of} VCO5 output from LF4 is applied to the varicap 54. Another varicap 55 is connected between the gates of the transistors M1 and M2. A 2-bit control voltage is applied to the varicap 55. The portion including the transistors M1 and M2, the capacitors 53A and 53B, and the varicaps 54 and 55 functions as a tank circuit and oscillates. By changing the capacitance of the varicap 54 by the V _tune, the oscillation operation of the transistors M1 and M2 is changed, and the oscillation frequency of the VCO 5 can be controlled. Further, the oscillation of VCO5 can be roughly adjusted by appropriately setting the bit control voltage of the varicap 55. It is preferable to use large transistors M1 and M2 (for example, 138.2 μm / 40 nm size) so that the harmonic signal is output with a large power. The capacitance of the capacitors 53A and 53B is, for example, 155 fF.

The harmonic resonators 51A and 51B are circuit elements that resonate with harmonics (here, secondary harmonics) of the oscillation frequency of the transistors M1 and M2. That is, the harmonic resonators 51A and 51B are resonators that perform an inverse class F operation. The harmonic resonator 51A is connected between the drain of the transistor M1 and the output terminal 56A of the OUT. The harmonic resonator 51B is connected between the drain of the transistor M2 and the output terminal 56B of the OUTB. Specifically, the harmonic resonators 51A and 51B include a capacitor 511 and a plurality of on-chip transmission lines L1, L2, L3 and L4. Capacitor 511 is connected to each drain of transistors M1 and M2. A line L1 is also connected to each of the drains of the transistors M1 and M2, and a bias voltage V _d is applied to each of the drains of the transistors M1 and M2 through the line L1. One ends of the lines L2, L3 and L4 are connected to each other, the other end of the line L2 is connected to the capacitor 511, the other end of the line L3 is opened, and the other end of the line L4 is connected to each output terminal 56A and 56B. It is connected. With this line L4, the impedance matching between the VCO 5 and the load Z _L connected to each of the output terminals 56A and 56B can be optimized. Each line length, for example, line L1 is 551μm (λ _0/6 equivalent), the line L2 is 284μm (λ _0/12 equivalent), the line L3 is 416μm (λ _0/8 equivalent), the line L4 is 95 .mu.m. A pad 59 is connected to the other end of the line L4, but this is merely provided for signal measurement.

FIG. 4 is a graph showing the simulation results of the input impedances of the harmonic resonators 51A and 51B, that is, the impedances of the harmonic resonators 51A and 51B as seen from the transistors M1 and M2. The input impedance Z _in of the harmonic resonators 51A and 51B is sharply increased near the frequency 2f ₀ , which is twice the fundamental frequency f ₀ , and the harmonic resonators 51A and 51B are operating in reverse class F. Understand.

Returning to FIG. 3, the buffers 52A and 52B are circuit elements that receive signals from the drains of the transistors M1 and M2 and output a differential feedback oscillation signal. The buffer 52A is connected to the drain of the transistor M1 and receives a signal from the drain of the transistor M1 to output ILFD _IN which is one of the differential inputs of ILFD6A and SSPD _IN which is one of the differential inputs of SSPD7A and 7B. .. The buffer 52B is connected to the drain of the transistor M2, receives a signal from the drain of the transistor M2, and outputs the ILFD _INB which is the other of the differential inputs of the ILFD6A and the SSPD _INB which is the other of the differential inputs of the SSPD7A and 7B. ..

-Operation and effect-
The operation of the VCO 5 having the above configuration is roughly as follows. Transistors M1 and M2 in which the train and the gate are cross-connected to each other oscillate at a frequency determined by the capacitances of the capacitors 53A and 53B and the varicaps 54 and 55. A part of the signal generated in each drain of the transistors M1 and M2 is returned to each gate of the transistors M1 and M2, the transistors M1 and M2 maintain the oscillating operation, and the rest is OUT via the harmonic resonators 51A and 51B. It is output as / OUTB. As a result, the VCO 5 can output a high-frequency oscillation signal with high output power, low phase noise, and high power efficiency without providing an output buffer.

Furthermore, it is possible to increase the P _S by returning a portion of the signal occurring in the drains of the transistors M1 and M2 transistors M1 and M2, also harmonics by providing the harmonic resonators 51A and 51B The phase of can be changed to lower Δf _{1 / f3} . As a result, low phase noise is achieved.

≪Results of demonstration experiment≫
Next, the post-layout simulation result of SSPLL10 will be described. 5A through 5D are off the circuit elements other than VCO5 in _{SSPLL10, V tune = 0V, V} d, buf = 0V, V g, V in a state in which the VCO5 in the SSPD = 0.51 V was self-oscillation It is a graph of various measured values when one of _g and V _d is changed. FIG. 5A is a graph of output power during self-propelled oscillation. FIG. 5B is a graph of power consumption during self-propelled oscillation. FIG. 5C is a graph of 10 kHz offset phase noise during self-propelled oscillation. FIG. 5D is a graph of 10 MHz offset phase noise during self-propelled oscillation. For example, the 10 MHz offset phase noise marks the best -137.6 dBc / Hz when V _g = 0.7 V and V _d = 0.65 at an oscillation frequency of 45.2 GHz. In FIG. 6, circuit elements other than VCO5 are turned off in SSPLL10, and V _tune = 0V, V _{d, buf} = 0V, V _{g, SSPD} = 0.51V, V _g = 0.7V, V _d = 0.65V. It is a graph of the phase noise when the VCO5 is oscillated by itself. Under this condition, the corner frequency Δf _{1 / f3} is about 600 kHz.

FIG. 7 is a graph of each phase noise of the self-propelled mode of SSPLL10, the phase lock mode of SSPLL10, the phase lock mode of general PLL, and the reference clock signal RF. For example, the 10 kHz offset phase noise of SSPLL10 (phase locked state) is −98.7 dBc / Hz, which is 30.6 dB higher than REF but suppressed lower than general PLL. The 40 MHz offset phase noise of SSPLL10 (phase locked state) is -138.8 dBc / Hz.

≪Modification example≫
A dead zone may be provided in the PFD2. That is, the phase difference between the frequency divider reference clock signal output from the 1/6 divider 1B and the frequency divider feedback oscillation signal output from the 1 / N divider 6C is output from the 1/6 divider 1B. The PFD2 may be configured so that the phase difference pulse signal to be output is set to zero within a half cycle (dead zone) of the frequency division reference clock signal.

The 1/6 divider 11B, ILFD16A, and 1/3 divider 16B may be appropriately replaced with a division circuit having a different division ratio, or may be omitted.

In the SSPD7A and 7B, the transistors M1, M2, M4 and M5 are provided to cancel the LO leak when the transistors M3 and M6 are on and reduce spurious. These transistors M1, M2, M4 and M5 may be omitted and the SSPD _IN / SSPD _INB may be directly connected to each gate of the transistors M3 and M6.

The harmonic resonators 51A and 51B may resonate with a third harmonic or a higher harmonic instead of the second harmonic. For example, the purpose of lowering the corner frequency Δf _{1 / f3} can be achieved even if the harmonic resonator resonates with the third harmonic is replaced.

The VCO5 can be used as an oscillator for various electronic circuits other than the SSPLL10. In that case, the buffers 52A and 52B are unnecessary and can be omitted.

As described above, an embodiment has been described as an example of the technique in the present invention. To that end, the accompanying drawings and detailed description are provided. Therefore, among the components described in the attached drawings and the detailed description, not only the components essential for solving the problem but also the components not essential for solving the problem in order to exemplify the above technology. Can also be included. Therefore, the fact that these non-essential components are described in the accompanying drawings or detailed description should not immediately determine that those non-essential components are essential. Further, since the above-described embodiment is for exemplifying the technique of the present invention, various changes, replacements, additions, omissions, etc. can be made within the scope of claims or the equivalent scope thereof.

5 ... Voltage controlled oscillator, M1, M2 ... Pair of transistors, 53A, 53B ... Capacitor, 54 ... Varicap, 56A, 56B ... Output terminal, 51A, 51B ... Harmonic resonator, 511 ... Capacitor, L1, L2, L3, L4 ... On-chip transmission line

Claims (3)

A voltage-controlled oscillator that oscillates at a frequency corresponding to a given control voltage and outputs a differential oscillation signal.
A pair of transistors in which the gate and drain are cross-connected to each other via a capacitor,
A varicap that is connected between the drains of the pair of transistors and whose capacitance changes according to the control voltage.
A voltage controlled oscillator including a pair of harmonic resonators connected between each drain of the pair of transistors and an output terminal of the differential oscillation signal and resonating with harmonics of the oscillation frequency of the pair of transistors. .. The voltage-controlled oscillator according to claim 1, wherein the harmonic resonator has a capacitor at a connection portion with the drain of the transistor. The voltage-controlled oscillator according to claim 2, wherein the harmonic resonator is composed of the capacitor and a plurality of on-chip transmission lines connected to the capacitor.