CN112349723A - 集成电路及其形成方法 - Google Patents

集成电路及其形成方法 Download PDF

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Publication number
CN112349723A
CN112349723A CN201911416488.5A CN201911416488A CN112349723A CN 112349723 A CN112349723 A CN 112349723A CN 201911416488 A CN201911416488 A CN 201911416488A CN 112349723 A CN112349723 A CN 112349723A
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region
gate
layer
polysilicon
dielectric
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林孟汉
邱德馨
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本案提供一种集成电路元件，包括多个金属栅极及多个多晶硅栅极，每个金属栅极具有金属电极及高介电常数介电质，每个多晶硅栅极具有多晶硅电极及习用(非高介电常数)介电质。多晶硅栅极已经为作为高压栅极操作进行了改进，此高压栅极包括厚介电层及大于1μm2的面积。具有这些改进的多晶硅栅极可在10V或更高的栅极电压下操作，并且可用于嵌入式记忆体元件中。

Description

集成电路及其形成方法
技术领域
本揭露是有关于一种集成电路(IC)及其形成方法。
背景技术
集成电路(integrated circuit；IC)制造工业在过去几十年已经经历了指数生长。随着IC发展，功能密度(即，单位晶片面积互连元件的数目)已经增加，同时特征尺寸已经减小。其他进展包括嵌入式记忆体技术及高介电常数金属栅极(high-K metal gate；HKMG)技术的引进。嵌入式记忆体技术为同一半导体晶片上具有逻辑元件的记忆体元件的整合。相比于针对不同类型元件使用单独的晶片，记忆体元件支持逻辑元件的操作并改进效能。高介电常数金属栅极(HKMG)技术为使用金属栅电极及高介电常数栅极介电层制造半导体元件。
发明内容
根据本揭露的一些实施例的一种集成电路(IC)，包括：多个金属栅极及多个多晶硅栅极。多个金属栅极，每个包括金属电极及高介电常数介电质；多个多晶硅栅极，每个包括多晶硅电极、通道区域、及从通道区域跨至多晶硅电极的一或多个介电质；其中多晶硅栅极的一或多个介电质中的每一者具有一介电常数，介电常数低于任意高介电常数介电质的介电常数；以及多晶硅栅极中的一或多者为一高压元件。
根据本揭露的一些实施例的一种集成电路(IC)，包括：半导体基板、记忆体元件、高介电常数金属栅极以及多晶硅栅极。半导体基板，包括记忆体区域及周边区域；记忆体元件形成于记忆体区域中；高介电常数金属栅极形成于周边区域中；以及多晶硅栅极形成于周边区域中；其中多晶硅栅极具有一面积，面积大于所述高介电常数金属栅极的一面积。
根据本揭露的一些实施例的一种集成电路(IC)的形成方法，包括以下步骤：提供半导体基板，半导体基板包括第一区域及第二区域；形成栅极氧化物层于第一区域中；形成多晶硅层于第一区域及第二区域上方，借此在栅极氧化物层上方形成多晶硅层；形成保护层于多晶硅层上方；掩蔽第一区域；在掩蔽第一区域的情况下，从第二区域选择性地去除保护层及多晶硅层；形成高介电常数介电层于第一区域及第二区域上方；形成虚设电极层于高介电常数介电层上方；图案化虚设电极层及高介电常数介电层以在第二区域中形成多个虚设栅极并从第一区域去除虚设电极层及高介电常数介电层；图案化保护层及多晶硅层以在第一区域中界定多个多晶硅栅极；邻近虚设栅极形成多个间隔物；填充邻近间隔物的一区域；平坦化第一区域及第二区域；从虚设栅极去除虚设电极层以形成多个空隙区域；在第一区域及第二区域上方沉积金属，借此金属填充空隙区域以形成多个高介电常数金属栅极；以及平坦化第一区域及第二区域以去除多余金属。
附图说明
当结合附图阅读时，根据以下详细描述可更好地理解本揭露的一实施例的态样。根据标准行业实务，特征并未按比例会制。此外，个别附图内不同特征的尺寸可相对于另一者任意地增加或减小，以便于说明或提供强调。
图1绘示根据本揭露的一些态样的集成电路(IC)的横截面视图；
图2至图52绘示根据本揭露的一些态样的IC经历根据本揭露的一些态样的制造制程的一系列横截面视图；
图53A及图53B呈现根据本揭露的一些态样的制造制程的流程图。
【符号说明】
1...IC元件
2...金属线
3...介电质
5...ILD1层
7...控制栅电极
9...硅化物垫
11...控制栅极间隔物
13...控制栅极介电质
14...浮动栅电极
15...浮动栅极介电质
17...硅化物垫
18...擦除栅电极
19...擦除栅极介电质
21...轻掺杂记忆体源极/漏极区域
22...选择栅极介电质
23...选择栅电极
25...记忆体区域
26...重掺杂记忆体源极/漏极区域
27...布植记忆体源极/漏极区域
29...ILD0层
30...硅化物垫
31...通孔
33...选择栅极侧壁间隔物
34...硅化物垫
38...第二侧壁间隔物
39...间隔物
41...深井布植
43...基板
45...高压栅极介电质
46...高压区域
47...高压栅电极
49...重掺杂高压栅极源极/漏极区域
50...轻掺杂高压源极/漏极区域
51...硅化物垫
57...金属栅电极
59...深井布植
62...核心区域
63...轻掺杂HKMG源极/漏极区域
65...重掺杂HKMG源极/漏极区域
68...氧化物介电质
69...高介电常数介电质
70...HKMG栅极
71...高压栅极
73...分裂式栅极快闪记忆体单
74...通道区域
81...垫氧化物层
82...垫氮化物层
84...氧化物层
85...隔离区域
86...氮化物覆盖层
87...氧化物覆盖层
90...记忆体区域
91...周边区域
200...横截面视图
201...垫氧化物层
202...垫氮化物层
203...光阻
300...横截面视图
400...横截面视图
500...横截面视图
600...横截面视图
700...横截面视图
701...光阻
800...横截面视图
900...横截面视图
901...浮动栅电极层
902...浮动栅极介电层
903...边界区域
904...边界隔离结构
1000...横截面视图
1100...横截面视图
1101...控制栅极介电层
1102...控制栅电极层
1103...控制栅极硬遮罩层
1105...控制栅极堆叠
1106...下氧化物层
1107...中间氮化物层
1108...上氧化物层
1110...第一氮化物层
1111...氧化物层
1112...第二氮化物层
1200...横截面视图
1201...控制栅极硬遮罩
1203...光阻层
1300...横截面视图
1400...横截面视图
1401...浮动栅极间隔物
1500...横截面视图
1501...光阻层
1502...共用源极/漏极缝隙
1600...横截面视图
1700...横截面视图
1800...横截面视图
1801...光阻层
1802...选择栅极缝隙
1900...横截面视图
2000...横截面视图
2001...选择栅电极层
2002...记忆体抗反射涂层
2100...横截面视图
2200...横截面视图
2201...记忆体选择栅极硬遮罩层
2300...横截面视图
2302...擦除栅极硬遮罩
2400...横截面视图
2401...遮罩
2500...横截面视图
2600...横截面视图
2700...横截面视图
2701...记忆体覆盖层
2702...底部抗反射涂层
2800...横截面视图
2900...横截面视图
2901...光阻遮罩
3000...横截面视图
3100...横截面视图
3101...硬遮罩
3400...横截面视图
3401...多晶硅电极层
3402...高压栅极硬遮罩
3403...高压栅极堆叠
3404...厚栅极氧化物层
3500...横截面视图
3501...光阻
3600...横截面视图
3601...氧化物层
3602...高介电常数介电层
3603...虚设栅电极层
3604...虚设栅极硬遮罩层
3605...虚设栅极堆叠
3700...横截面视图
3701...光阻
3702...虚设栅电极
3703...虚设栅极
3800...横截面视图
3801...光阻
3802...高压栅极硬遮罩
3900...横截面视图
4000...横截面视图
4001...光阻
4100...横截面视图
4101...光阻
4200...横截面视图
4201...光阻
4300...横截面视图
4400...横截面视图
4500...横截面视图
4600...横截面视图
4700...横截面视图
4800...横截面视图
4900...横截面视图
5000...横截面视图
5001...光阻
5002...空隙区域
5100...横截面视图
5101...上表面
5102...上表面
5200...横截面视图
5201...硬遮罩
5300...制程
5301...动作
5302...动作
5303...动作
5304...动作
5305...动作
5306...动作
5307...动作
5308...动作
5309...动作
5310...动作
5311...动作
5312...动作
5313...动作
5314...动作
5315...动作
5316...动作
5317...动作
5318...动作
5319...动作
5320...动作
5321...动作
5322...动作
5323...动作
5324...动作
5325...动作
5326...动作
5327...动作
5328...动作
5329...动作
5330...动作
5331...动作
5332...动作
5333...动作
5334...动作
5335...动作
5336...动作
5337...动作
5338...动作
5339...动作
5340...动作
5341...动作
5342...动作
5343...动作
5344...动作
5345...动作
5346...动作
5347...动作
5348...动作
5349...动作
5350...动作
5351...动作
5352...动作
具体实施方式
本揭露内容提供许多不同实施例或实例，以用于实施本揭露内容的不同特征。下文描述组件及排列的特定实例以简化本揭露内容。当然，此等实例仅为实例且不意欲为限制性。举例而言，在随后描述中在第二特征上方或在第二特征上第一特征的形成可包括第一及第二特征形成为直接接触的实施例，以及亦可包括额外特征可形成在第一及第二特征之间，使得第一及第二特征可不直接接触的实施例。
空间相对用语，诸如“之下”、“下方”、“下部”、“上方”、“上部”及类似者，在此为便于描述可用于描述诸图中所绘示一个元件或特征与另一(些)元件或(多个)特征的关系。除图形中描绘的方向外，这些空间相对用语意图是包含元件或设备在使用或操作中的不同方向。元件或设备可为不同朝向(旋转90度或在其他的方向)及在此使用的空间相对的描述词可因此同样地解释。术语“第一”、“第二”、“第三”、“第四”等仅为通用识别字，并且因而在不同实施例中可互换。例如，当元件(例如，开口)在一些实施例中可称为“第一元件”时，元件在其他实施例中可称为“第二元件”。
本揭露的一实施例提供结构及制造制程，用于将高压元件并入具有HKMG的元件内，此HKMG包括具有嵌入式记忆体的元件。具有嵌入式记忆体的元件可为分裂式栅极快闪记忆体元件。在分裂式栅极快闪记忆体元件中，记忆体单元阵列设置于半导体基板中或上方。周边电路系统，包括诸如地址解码器及/或读写电路系统及/或微控制器的逻辑元件，布置在记忆体阵列外并可控制记忆体单元的操作及/或执行其他任务。具有隔离结构的隔离区域将记忆体阵列与周边电路系统分隔。
本揭露的一实施例特别涉及利用置换栅极制程或栅极最后制程形成的HKMG元件，此制程为在退火源极/漏极区域之后沉积HKMG电极的金属的制程。使用在初始栅极形成之后进行的自对准制程，来掺杂源极/漏极区域。基板掺杂之后进行退火，其可为在1000℃处至少5秒的热处理。高介电常数介电质及金属栅电极在退火的热处理下交互作用，其改变了HKMG栅极的阈电压。置换栅极制程通过掺杂源极/漏极区域来控制HKMG栅极的阈电压，掺杂源极/漏极区域通过对虚设栅极对准来实现。虚设栅极具有虚设电极(其可为多晶硅)，其由退火后的期望栅极金属来替换。
在置换栅极制程中，沉积金属以填充由去除虚设栅电极而空置的区域。在此金属沉积之后进行化学机械研磨(chemical mechanical polishing；CMP)以去除沉积在栅极区域外的金属。此制程的限制为相比于其他材料，栅极金属对CMP更加敏感，这导致使金属栅电极薄化的凹陷。一些此薄化可通过使基板相对于隔离结构凹陷而抵消。但当栅极面积增大时薄化变得更加严重，其导致金属栅极区域上的众所周知的设计极限。彼极限值低于1μm2。彼极限为将高压元件引进具有HKMG栅极的元件的阻碍。
根据本教示的一些态样，将高压元件并入具有HKMG栅极的元件的问题，通过使用具有厚栅极氧化物的多晶硅栅极来实施高压元件而解决。多晶硅栅极使用与高介电常数介电质不同的习用介电质。形成高介电常数介电质及习用介电质栅极两者的问题，通过包括以下步骤的制程来解决：形成厚栅极氧化物，沉积多晶硅电极层，用硬遮罩覆盖多晶硅电极层，从预期的HKMG栅极的区域蚀刻掉所述层，沉积虚设栅极堆叠，图案化虚设栅极，图案化多晶硅栅极，邻近虚设栅极形成间隔物，掺杂对准至间隔物的源极/漏极区域，以及继续置换栅极制程。此制程允许从多晶硅栅极区域蚀刻高介电常数介电质，而不损害厚氧化物。
图1提供根据本教示的一些态样的IC元件1的选定部分的横截面视图。这些部分包括记忆体区域25的部分、高压区域46的部分、及核心区域62的部分，其全部形成于基板43上。高压区域46包括高压栅极71，核心区域62包括高介电常数金属栅极70，以及记忆体区域25包括分裂式栅极快闪记忆体单元73。尽管IC元件1包括分裂式栅极快闪记忆体单元73以及本揭露的一实施例的制程与嵌入快闪记忆体相容，但本揭露的一实施例适于没有嵌入式记忆体的IC元件。
高电压栅极71为可在高栅极电压下操作的元件。高栅极电压可为大于5V的电压。在这些教示的一些中，高电压栅极71可在10V或更高的栅极电压下操作。在这些教示的一些中，高电压栅极71可在20V或更高的栅极电压下操作。
高压栅极71具有厚氧化物层，其形成高压栅极介电质45的全部或部分。高压栅极介电质45可具有
Figure BDA0002351322750000111
或更大的厚度。在这些教示的一些中，高压栅极介电质45可具有
Figure BDA0002351322750000112
或更大的厚度。在这些教示的一些中，高压栅极介电质45可具有
Figure BDA0002351322750000113
或更大的厚度。高压栅极介电质45可包括一或多个介电质层。在高压栅极介电质45直接下方的基板43的区域为高压栅极71的通道区域74。高压栅极介电质45包括通道区域74与高压栅电极47之间的所有层。根据本教示的一些，高压栅极介电质45中没有一层为高介电常数介电质。高介电常数介电质为具有大于约7的介电常数的介电质。IC元件1亦可包括低压栅极(诸如5V栅极)，其具有与高压栅极71相同或类似的介电质及电极组成物，但具有更薄的栅极氧化物。
高压栅极71具有多晶硅或类似物的高压栅电极47。高压栅电极47可具有任何适当的厚度。在这些教示的一些中，高压栅电极47的厚度范围为
Figure BDA0002351322750000121
至
Figure BDA0002351322750000122
高压栅极71可为大面积元件。大面积元件为具有大于1μm2面积的元件，即面积为高压栅电极47的面积。在这些教示的一些中，高压栅极71可具有3μm2或更大的栅极面积。在这些教示的一些中，高压栅极71具有8μm2或更大的栅极面积。
高压栅极71可形成于深井布植41上方。轻掺杂高压栅极源极/漏极区域50及重掺杂高压栅极源极/漏极区域49可为高压栅极71提供源极/漏极区域，并且可分别对准至间隔物38及间隔物39。重掺杂高压栅极源极/漏极区域49可在其表面具有硅化物垫51。硅化物垫34亦可形成于高压栅电极47上方。
HKMG栅极70包括高介电常数介电质69及金属栅电极57。高介电常数介电质可为金属氧化物或以下各者的硅酸盐：铪(Hf)、铝(Al)、锆(Zr)、镧(La)、镁(Mg)、钡(Ba)、钛(Ti)、铅(Pb)等。高介电常数介电质的实例包括TiO2、HfZrO、Ta2O3、HfSiO4、ZrO2及ZrSiO2等。高介电常数介电质69可具有范围在约
Figure BDA0002351322750000123
至约
Figure BDA0002351322750000124
的厚度。在这些教示的一些中，高介电常数介电质69可具有范围在约
Figure BDA0002351322750000125
至约
Figure BDA0002351322750000126
的厚度。高介电常数介电质69可通过氧化物介电质68与基板43分隔。氧化物介电质68为非高介电常数介电质。IC元件1可包括具有不同厚度氧化物介电质68的各种HKMG栅极70。一些HKMG栅极可具有厚度范围在约
Figure BDA0002351322750000127
至约
Figure BDA0002351322750000128
的氧化物介电质68。其他HKMG栅极可具有厚度范围在约
Figure BDA0002351322750000129
至约
Figure BDA00023513227500001210
的氧化物介电质68。
金属栅电极57的上表面可相对于基板43以上的距离与高压栅电极47的上表面对准。金属栅电极57可具有任何适当的厚度。在这些教示的一些中，金属栅电极57的厚度范围为
Figure BDA00023513227500001211
至
Figure BDA00023513227500001212
HKMG栅极70可具有小于高压栅极71的面积。HKMG栅极70具有小于1μm2的栅极面积。
HKMG栅极70可形成于深井布植59上方。轻掺杂HKMG源极/漏极区域63及重掺杂HKMG源极/漏极区域65可为HKMG栅极70提供源极/漏极区域，并且可分别对准至侧壁间隔物39及第二侧壁间隔物38。重掺杂HKMG源极/漏极区域65可在其表面具有硅化物垫51。HKMG栅极70可通过栅极最后制程而形成。因此，HKMG栅极70尚未经历退火重掺杂HKMG源极/漏极区域65中的布植所要求的条件。若HKMG栅极70经历过此种条件，则高介电常数介电质69及金属栅电极57将以改变HKMG栅极70的阈电压的方式来交互作用。
分裂式栅极快闪记忆体单元73包括通过浮动栅极介电质15与基板43分隔的浮动栅电极14，通过控制栅极介电质13与浮动栅电极14分隔的控制栅电极7，通过擦除栅极介电质19与基板43分隔的擦除栅电极18，以及通过选择栅极介电质22与基板43及浮动栅电极14分隔的选择栅电极23。重掺杂记忆体源极/漏极区域26通过对准至选择栅极侧壁间隔物33的掺杂而形成于基板43中。
不同金属化层可形成于分裂式栅极快闪记忆体单元73、HKMG栅极70及高压栅极71上方。这些包括第一金属化层，第一金属层包括形成于介电质3中的金属线2。介电质3可为低介电常数介电质。附加金属化层可形成于示出的金属化层上方。金属化层通过通孔31耦接至源极/漏极区域。通孔31穿过介电层，介电层包括：在分裂式栅极快闪记忆体单73、HKMG栅极70、及高压栅极71的高度处的ILD0层29，及在分裂式栅极快闪记忆体单元73、HKMG栅极70、及高压栅极71上方的ILD1层5。
基板43为半导体及可为或另外包括例如块材硅基板、SOI基板、第III-V族基板、及另一适当半导体基板。基板43亦可为二元半导体基板(例如，GaAs)、三元半导体基板(例如，AlGaAs)、高阶半导体基板。
图2至图44提供一系列横截面视图600至4400，其绘示根据本揭露的一实施例的集成电路元件在根据本揭露的一实施例的制造制程的各个阶段。尽管图2至图44关于一系列动作描述，但应理解，在一些情况下这些动作的顺序可改变，且此系列动作适于除绘示结构外的结构。在一些实施例中，可全部或部分地省去这些动作中的一些。此外，图2至图44关于一系列动作描述，应理解图2至图44中绘示的结构并不限于制造方法，而是可单独作为与此方法分隔的结构。
图2提供横截面视图200，绘示在基板43上方形成垫氧化物层201及垫氮化物层202的初始步骤。光阻203可经形成及图案化以在周边区域91中覆盖垫氮化物层202。如图3的横截面视图300绘示，光阻203可用以从记忆体区域90选择性地蚀刻垫氮化物层202。如图3的横截面视图300进一步绘示，在剥离光阻203之后，可进行氧化制程以使基板43在记忆体区域90中凹陷。使基板43在区域90中凹陷允许分裂式栅极快闪记忆体单元73的顶部与HKMG栅极70及高压栅极71的顶部对准，尽管分裂式栅极快闪记忆体单元73具有更大的高度。氧化制程产生氧化物层84。氧化制程可为湿式氧化制程。另外，氧化可利用干式氧化、蒸汽氧化、或其他一些适当制程来完成。
氧化物层84可薄化以接近垫氧化物层201的厚度，如图4的横截面视图400绘示。原始垫氧化物层201及垫氮化物层202可随后剥离并替换为垫氧化物层81及垫氮化物层82，如图5的横截面视图500绘示。隔离区域85可随后通过以下步骤而形成：放设图案化遮罩，蚀刻穿透垫氧化物层81、垫氮化物层82并进入基板43，通过沉积氧化物或氧化物前驱物而形成隔离区域85的氧化物。在形成氧化物之后，化学机械研磨(CMP)可用以产生由图5的横截面视图500示出的水平表面。
如图6的横截面视图600绘示，随后可形成氮化物覆盖层86及氧化物覆盖层87。氧化物覆盖层87可为光阻保护氧化物，或一些其他适当种类的氧化物。不包括氮化物覆盖层86或氧化物覆盖层87的替代处理亦是可行的。
如图7的横截面视图700绘示，从记忆体区域90去除垫层时，光阻701可用以保护周边区域。随后可剥离光阻701，之后沉积浮动栅极介电层902及浮动栅电极层901，然后执行CMP以从周边区域91去除这些层及氧化物覆盖层87，如图8的横截面视图800绘示。浮动栅极介电层902可为任何适当的介电层。浮动栅极介电层902可生长于基板43上或沉积于基板43上。浮动栅电极层901可共形地沉积于浮动栅极介电层902上，并可为掺杂多晶硅等。浮动栅电极层901可通过CVD、PVD、溅射等形成。
如图9的横截面视图900绘示，可随后进行蚀刻制程以将浮动栅电极层901减小至要求厚度。此回蚀可利用氢氟酸(HF)浸泡等来完成。图9绘示通过具有边界隔离结构904的边界区域903分隔开的记忆体区域90及周边区域91。图9亦识别记忆体区域25，其为记忆体区域90内的示例性区域。图9进一步识别高压区域46及核心区域62，其为周边区域91内经历不同类型处理的两个示例性区域。图10绘示对应于图9的横截面视图900的横截面视图1000，不同之处在于它仅关注这三个方面，随后的横截面视图也是如此。
如图11的横截面视图1100绘示，控制栅极堆叠1105可形成于浮动栅电极层901上方。控制栅极堆叠1105包括控制栅极介电层1101、控制栅电极层1102、及控制栅极硬遮罩层1103。控制栅极介电层1101可包括氧化物、氮化物、另一适当介电质等中的一或多层。控制栅极介电层1101可包括多层不同介电层。在一些实施例中，控制栅极介电层1101包括：具有下氧化物层1106的ONO膜、覆盖下氧化物层1106的中间氮化物层1107、及覆盖中间氮化物层1107的上氧化物层1108。控制栅极介电层1101可通过CVD、PVD、另一适当沉积制程、上述任意组合等形成。
控制栅极介电层1101非常薄。下氧化物层1106可具有范围在10至100埃的厚度。在一些实施例中，下氧化物层1106可具有范围在20至50埃，例如约40埃的厚度。中间氮化物层1107可具有范围在25至200埃的厚度。在一些实施例中，中间氧化物层1107可具有范围在50至100埃，例如约80埃的厚度。上氧化物层1108可具有范围在10至100埃的厚度。在一些实施例中，上氧化物层1108具有范围在20至50埃，例如约40埃的厚度。在一些实施例中，控制栅极介电层1101的总厚度范围在25至400埃。在一些实施例中，控制栅极介电层1101的总厚度范围在50至200埃。
控制栅电极层1102可共形地形成并且可由掺杂多晶硅等形成。在一些实施例中，形成控制栅电极层1102的制程包括以下步骤：沉积材料，将掺杂剂布植进材料中，以及退火以活化掺杂剂。控制栅电极层1102的材料可通过CVD、PVD或另一适当沉积制程而沉积。在一些实施例中，控制栅电极层1102具有范围在600至2000埃的厚度。在一些实施例中，控制栅电极层1102具有范围在300至1000埃的厚度。在一些实施例中，控制栅电极层1102具有约600埃的厚度。
控制栅极硬遮罩层1103可包括多层不同材料。控制栅极硬遮罩层1103可包括氧化物、氮化物、或其他适当材料。在一些实施例中，控制栅极硬遮罩层1103包括第一氮化物层1110上方的氧化物层1111。在一些实施例中，这些层的厚度范围为100至3000埃。在一些实施例中，这些层的厚度范围为例如200至700埃。在一些实施例中，这些层为约400埃厚。在一些实施例中，控制栅极硬遮罩层1103进一步包括氧化物层1111上方的第二氮化物层1112。控制栅极硬遮罩层1103可通过CVD、PVD、另一适当沉积制程、上述任意组合等形成。
如图12的横截面视图1200绘示，可执行选择性蚀刻以从记忆体区域25去除控制栅极堆叠1105的部分，借此在浮动栅极层901上方形成控制栅极硬遮罩1201、控制栅电极7、及控制栅极介电质13。在一些实施例中，执行选择性蚀刻的制程包括形成并图案化光阻层1203。光阻层1203可经图案化以覆盖高压区域46、核心区域62、及记忆体区域25的部分形成控制栅电极7的负影像。在光阻层1203就位的情况下可应用蚀刻制程，直到暴露浮动栅电极层901。随后可剥离光阻层1203。
如图13的横截面视图1300绘示，可邻近控制栅极硬遮罩1201形成控制栅极间隔物11。控制栅极间隔物11覆盖控制栅电极7的侧壁。控制栅极间隔物11可通过沉积间隔物材料层，之后蚀刻而形成。控制栅极间隔物11可具有任何适当的组成物。控制栅极间隔物11可包括氧化物、氮化物、另一适当介电质等的一或多层。在一些实施例中，控制栅极间隔物11包括ONO膜，例如下氧化物层、中间氮化物层及上氧化物层。间隔物材料可通过CVD、PVD或另一适当沉积制程而沉积。蚀刻制程可包括电浆蚀刻或选择性地去除间隔物材料相对于垂直面最薄位置的任何其他适当蚀刻制程。为便于说明，控制栅极间隔物11被示为具有垂直侧壁。间隔物形成的蚀刻制程可产生圆角及光滑锥形侧壁。
如图14的横截面视图1400绘示，可对浮动栅电极层901及浮动栅极介电层902执行蚀刻(见图13)以形成浮动栅电极14及浮动栅极介电质15。控制栅极间隔物11及控制栅极硬遮罩1201可充当用于此蚀刻的遮罩。如图14的横截面视图1400绘示，可在浮动栅电极14及控制栅极间隔物11的侧壁上形成浮动栅极间隔物1401。浮动栅极间隔物1401可为氧化物、另一适当介电质等。形成浮动栅极间隔物1401的制程可包括以下步骤：在如图14的横截面视图1400绘示的结构上方沉积浮动栅极间隔物层，之后进行电浆蚀刻或选择性去除浮动栅极间隔物层相对于垂直面最薄之处的任何其他适当蚀刻制程。浮动栅极间隔物层可通过CVD、PVD或另一适当沉积制程而共形地沉积。
如图15的横截面视图1500绘示，轻掺杂记忆体源极/漏极区域21可形成于基板43中，横向位于浮动栅电极14之间。形成轻掺杂记忆体源极/漏极区域21的制程可包括以下步骤：形成并图案化光阻层1501，光阻层1501覆盖高压区域46、核心区域62、及记忆体区域25在共用源极/漏极缝隙1502之外的部分。在光阻层1501就位的情况下，可执行离子布植或另一适当掺杂制程。光阻层1501可使用光微影来图案化。
如图16的横截面视图1600绘示，可去除共用源极/漏极缝隙1502内的浮动栅极间隔物1401。用于去除浮动栅极间隔物1401的制程可包括在光阻层1501就位的情况下进行蚀刻。此后可剥离光阻层1501。
如图17的横截面视图1700绘示，可形成擦除栅极介电质19，以覆盖记忆体源极/漏极区域21及浮动栅电极14的线侧壁及共用源极/漏极缝隙1502内的控制栅极间隔物11。擦除栅极介电质19可由氧化物、氮化物或另一适当介电质形成。形成擦除栅极介电质19的制程可包括高温氧化(high temperature oxidation；HTO)、原位蒸汽产生(in situ steamgeneration；ISSG)氧化、另一适当沉积或生长制程、上述任意组合等。在一些实施例中，通过氧化物沉积制程及之后执行氧化物生长制程，来形成擦除栅极介电质19。在一些实施例中，由于记忆体源极/漏极区域21中的离子布植，擦除栅极介电质19形成弯曲或球状面轮廓。记忆体源极/漏极区域21的中央区域接收更大剂量的掺杂剂，并且因而比记忆体源极/漏极区域21的边缘区域经历更多的损伤。相比于边缘区域，氧化物可在中央区域必然更快速地生长。
如图18的横截面视图1800绘示，可形成光阻层1801以覆盖高压区域46、核心区域62、及记忆体区域25在选择栅极缝隙1802之外的部分，并且用以从选择栅极缝隙1802内去除浮动栅极间隔物1401及擦除栅极介电质1701(见图17的横截面视图1700)。如图19的横截面视图1900绘示，在去除光阻层1801之后，选择栅极介电质22可随后形成于选择栅极缝隙1802中。选择栅极介电质22可为氧化物、氮化物、另一适当介电质等的一或多层。选择栅极介电质22可通过HTO、ISSG氧化、另一适当沉积或生长制程、上述任何组合等而形成。
又如图20的横截面视图2000绘示，可形成选择栅电极层2001以覆盖选择栅极介电质22及高压区域46、核心区域62及记忆体区域25中的其他结构。选择栅电极层2001可由掺杂多晶硅等或另一适当导电材料形成，并且可通过CVD、PVD或另一适当沉积制程而形成。图20的横截面视图2000亦绘示形成于选择栅电极层2001上方的记忆体抗反射涂层(antireflective coating；ARC)2002。记忆体ARC 2002可例如通过旋转涂布制程由可流动有机材料而形成，其中基板43的晶圆围绕其中心而旋转，而液体ARC涂层在晶圆表面上。由于其可流动性，液体ARC涂层趋向于形成水平面。在旋涂液体ARC涂层之后，可进行烘烤步骤以硬化记忆体ARC 2002。
如图21的横截面视图2100绘示，可进行制程以去除记忆体ARC 2002(见图20)并薄化选择栅电极层2001。此制程形成擦除栅电极18。可利用蚀刻制程进行去除及薄化，其中记忆体ARC 2002及选择栅电极层2001具有近似相等的敏感性。可回蚀记忆体ARC 2002直到暴露选择栅电极层2001，在此之后可一起回蚀选择栅电极层2001及记忆体ARC 2002直到完全去除记忆体ARC2002。随后可回蚀选择栅电极层2001直到其顶表面与控制栅电极7的顶表面约对齐。蚀刻制程留下具有大体上平坦表面的凹陷选择栅电极层2001。掺杂剂可布植进选择栅电极层2001中，并之后进行退火以活化掺杂剂。
如图22的横截面视图2200绘示，可在图21的横截面视图2100绘示的结构上方共形地形成记忆体选择栅极硬遮罩层2201。记忆体选择栅极硬遮罩层2201可由氮化物、氧化物或另一适当硬遮罩材料形成。记忆体选择栅极硬遮罩层2201可通过CVD、PVD或另一适当沉积制程而形成。
如图23的横截面视图2300绘示，蚀刻可用以从记忆体选择栅极硬遮罩层2201(见图22)形成选择栅极硬遮罩2301及擦除栅极硬遮罩2302。选择栅极硬遮罩2301覆盖选择栅电极23。擦除栅极硬遮罩2302覆盖擦除栅电极18。此蚀刻制程不需要遮罩。此所需结构可通过去除记忆体选择栅极硬遮罩层2201相对于垂直面最薄之处而形成。
如图24的横截面视图2400绘示，可在遮罩2401覆盖绘示的记忆体区域25的部分的情况下，执行附加蚀刻。此附加蚀刻可终结导电线，此导电线通过绘示结构在页面方向上的一些而形成。此蚀刻可薄化高压区域46及核心区域62上方的控制栅极硬遮罩层1103。
如图25的横截面视图2500绘示，可在图24的横截面视图2400绘示的结构上方形成第二ARC 2501。可形成第二ARC 2501，顶表面平坦或大体上平坦。第二ARC 2501可与非选择性回蚀制程结合使用以凹陷图24的横截面视图2400绘示的结构的最高部分，以产生图26的横截面视图2600绘示的结构。回蚀制程可停止于控制栅极硬遮罩层1103、控制栅极硬遮罩1201、及选择栅极硬遮罩2301之上或之中。在回蚀制程后，可去除第二ARC 2501，如图26的横截面视图2600绘示。
如图27的横截面视图2700绘示，可在图26的横截面视图2600绘示的结构上方形成记忆体覆盖层2701，及在记忆体覆盖层2701上方形成底部抗反射涂层(bottom anti-reflective coating；BARC)2702。记忆体覆盖层2701可为多晶硅，但可使用另一适当材料。记忆体覆盖层2701可部分地符合其覆盖的表面。记忆体覆盖层2701可通过CVD、PVD、另一适当沉积制程、上述任意组合等形成。BARC 2702可由液体涂层形成，液体涂层在记忆体覆盖层2701上方旋涂以提供平坦或大体上平坦的顶表面。在旋涂BARC 2702之后，可进行烘烤步骤以硬化BARC 2702。
如图28的横截面视图2800绘示，可进行制程以去除BARC 2702(见图24)并留下具有凹陷及相对水平表面的记忆体覆盖层2701。制程可为蚀刻，在此蚀刻下BARC 2702及记忆体覆盖层2701具有非常类似的蚀刻速率。最初，蚀刻继续穿透BARC 2702，直到暴露记忆体覆盖层2701。蚀刻继续同时地蚀刻BARC 2702及记忆体覆盖层2701，直到完全去除BARC2702。此蚀刻制程可留下记忆体覆盖层2701，此记忆体覆盖层2701在记忆体区域25上方具有明确的厚度。
如图29的横截面视图2900绘示，在记忆体区域25中，可在记忆体覆盖层2701上方形成并图案化光阻遮罩2901。类似其他光阻遮罩，光阻遮罩2901可通过包括以下步骤的制程形成：在结构表面上旋涂或以另外方式形成光阻，经由主光罩或其他光微影遮罩将光阻选择性地暴露于光，以及使用化学显影剂去除暴露或未暴露的部分。在遮罩2901就位的情况下，可执行蚀刻以从高压区域46及核心区域62去除控制栅电极层1102及控制栅极硬遮罩层1103。蚀刻之后，可去除光阻遮罩2901。类似其他光阻遮罩，光阻2901可通过全曝光及显影、蚀刻、灰化、或任何其他适当去除制程而去除。如图30的横截面视图3000绘示，可执行附加蚀刻以从高压区域46及核心区域62去除控制栅极介电层1101及氮化物覆盖层86。
如图31的横截面视图3100绘示，可在记忆体区域25、高压区域46及核心区域62上方形成硬遮罩3101。硬遮罩3101可为氮化硅、氧化物等。如图32的横截面视图3200绘示，可形成并图案化光阻3201以覆盖记忆体区域25及核心区域62，同时从高压区域46去除硬遮罩3101、垫氧化物层81、及垫氮化物层82。如图33的横截面视图3300绘示，可去除光阻3201，及离子布植用以在高压区域46中形成深井布植41。
如图34的横截面视图3400绘示，随后可形成高压栅极堆叠3403。高压栅极堆叠3403包括厚栅极氧化物层3404、多晶硅电极层3401、及高压栅极硬遮罩3402。厚栅极氧化物层3404可通过湿式或干式氧化制程而从基板43生长。或者，厚栅极氧化物层3404可通过CVD等沉积。厚栅极氧化物层3404亦可通过氧化生长及沉积的组合而形成。多晶硅电极层3401可通过CVD沉积。在高压区域46外，多晶硅电极层3401可沉积于硬遮罩3101上方，其可便于稍后从这些其他区域去除多晶硅电极层3401。在一些实施例中，掺杂剂可布植进多晶硅电极层3401中，并之后进行退火以活化掺杂剂。光阻遮罩可用以允许掺杂剂类型在N型与P型之间变化，或以另外方式允许不同区域及元件类型中掺杂不同。高压栅极硬遮罩3402可形成于多晶硅电极层3401上方，并可由氮化物、氧化物、多晶硅等形成。
如图35的横截面视图3500绘示，在用光阻3501掩蔽住记忆体区域25及高压区域46后，可从核心区域62去除高压栅极硬遮罩3402、硬遮罩3101、多晶硅电极层3401、垫氧化物层81及垫氮化物层82。如图35的横截面视图3500进一步绘示，随后可进行离子布植及退火以在核心区域62中形成深井布植59。
如图36的横截面视图3600绘示，可在去除光阻3501之后，在图35的横截面视图3500绘示的结构上方形成虚设栅极堆叠3605。虚设栅极堆叠3605可包括氧化物层3601、高介电常数介电层3602、虚设栅电极层3603、及虚设栅极硬遮罩层3604。一般地，虚设栅极堆叠介电质可包括任意适当数目及组合的介电层，并且可由在核心区域62中的不同元件之间变化的厚度及/或组成物制成。虚设栅电极层3603可为多晶硅等或另一适当材料。虚设栅极硬遮罩层3604可为氮化物、氧化物、多晶硅等。虚设栅极堆叠3605的层可通过CVD、PVD、化学镀、电镀、另一适当生长或沉积制程、上述任意组合等而共形地形成。氧化物层3601尤其可在基板43上生长。
如图37的横截面视图3700绘示，光阻3701可用以界定核心区域62中的虚设栅极3703，同时可从其他位置去除氧化物层3601、高介电常数介电层3602、虚设栅电极层3603、及虚设栅极硬遮罩层3604。此蚀刻从氧化物层3601形成氧化物介电质68、从高介电常数介电层3602形成高介电常数介电质69、及从虚设栅电极层3603形成虚设栅电极3702。此制程可从核心区域62外的区域有效地去除高介电常数介电层3602。高压栅极硬遮罩3402及多晶硅电极层3401在此处理期间保护厚栅极氧化物层3404。
如图38的横截面视图3800绘示，光阻3801可经形成、图案化、及随后用以掩蔽核心区域62，同时选择性地蚀刻高压栅极堆叠3403以形成高压栅极71及从记忆体区域25去除高压栅极堆叠3403。此蚀刻从高压栅极硬遮罩3402形成高压栅极硬遮罩3802、从多晶硅电极层3401形成高压栅电极47、及从厚栅极氧化物层3404形成高压栅极介电质45。选择性蚀刻可包括一系列电浆蚀刻，以蚀刻穿透不同层。在此制程结尾处可去除光阻3801。
如图39的横截面视图3900绘示，随后可沿高压栅极71及虚设栅极3703的外侧壁形成侧壁间隔物39。侧壁间隔物39可为氧化物、氮化物、另一适当介电质、上述任意组合等。侧壁间隔物39可通过沉积间隔物材料，及之后蚀刻以从其中最薄的部分去除间隔物材料，来形成。间隔物材料可通过CVD、PVD、另一适当沉积制程、上述任意组合等而共形地沉积。间隔物材料可通过任何适当蚀刻制程来蚀刻以形成侧壁间隔物39。
如图40的横截面视图4000绘示，随后光阻4001可用以掩蔽高压区域46及核心区域62，同时从记忆体区域25蚀刻记忆体覆盖层2701。随后可布植掺杂剂以在记忆体区域25中形成记忆体源极/漏极区域27。如图41的横截面视图4100绘示，随后光阻4101可用以掩蔽核心区域62及记忆体区域25，同时在高压区域46中形成轻掺杂高压漏极区域50。同样地，如图42的横截面视图4200绘示，随后光阻4201可用于记忆体区域25及高压区域46，同时在核心区域62中形成轻掺杂核心源极/漏极区域63。
如图43的横截面视图4300绘示，随后可邻近高压栅极71及虚设栅极3703形成第二侧壁间隔物38。视情况，可同时邻近选择栅电极23形成选择栅极侧壁间隔物33。这些间隔物可通过共形地沉积间隔物材料及随后蚀刻，直到材料仅剩下需要间隔物的地方，而形成。
如图44的横截面视图4400绘示，随后可分别在记忆体区域25、高压区域46、及核心区域62中形成重掺杂记忆体源极/漏极区域26、重掺杂高压栅极源极/漏极区域49、及重掺杂HKMG源极/漏极区域65。在掩蔽不同区域及子区域的情况下，可以一系列步骤进行掺杂以提供掺杂浓度的范围及不同元件的类型。在掺杂之后，可执行退火以活化基板43内的掺杂剂。如图44的横截面视图4400进一步绘示，可进行硅化制程以分别在重掺杂记忆体源极/漏极区域26、重掺杂高压栅极源极/漏极区域49、及重掺杂HKMG源极/漏极区域65上形成硅化物垫30、硅化物垫51、及硅化物垫67。硅化物可为硅化镍、硅化钛、硅化钴、另一硅化物等，并且可由任何适当硅化制程形成。
如图45的横截面视图4500绘示，可在图44的横截面视图4400绘示的结构上方形成接触蚀刻停止层8及第二ARC 4501。可形成第二ARC 4501，顶表面平坦或大体上平坦。形成第二ARC 4501的制程可包括旋涂有机ARC涂层。如图46的横截面视图4600绘示，随后可执行制程以从图44的横截面视图4400绘示的结构去除上层。此可为CMP制程。然而，在一些实施例中，使用一种制程进行蚀刻来完成去除，对于此制程，被去除的不同材料具有类似的敏感性，借此上表面保持大体上平坦。适当蚀刻制程可为包括来自碳氟化合物及He蚀刻剂的电浆的干式蚀刻。
如图47的横截面视图4700绘示，随后可去除第二ARC 4501，之后形成ILD0层29，如图48的横截面视图4800绘示。ILD0层29可为氧化物、低介电常数介电质、另一适当介电质、上述任意组合等。第二ARC 4501可通过蚀刻或任意其他适当去除制程而去除。形成ILD0层29的制程可包括CVD、PVD、溅射或任意其他适当制程。如图49的横截面视图4900绘示，下ILD层1741可经平坦化并且其顶表面经凹陷以暴露虚设栅电极3702。平坦化及凹陷可通过CMP或任意其他适当制程或制程的组合来完成。
如图50的横截面视图5000绘示，光阻5001可用以覆盖记忆体区域25及高压区域46，同时执行蚀刻以去除虚设栅电极3702，从而留下空隙区域5002。如图51的横截面视图5100绘示，随后可通过填充空隙区域5002来形成金属栅电极57。填充步骤可包括由CVD、PVD、化学镀、电镀、或另一适当生长或沉积制程形成的不同金属的一或多层。在空隙区域5002外沉积或生长的金属随后可通过平坦化来去除。平坦化制程可为CMP等。
如图52的横截面视图5200绘示，可形成及图案化硬遮罩5201以覆盖核心区域62及控制栅电极7，同时分别在选择栅电极23、擦除栅电极18、及高压栅电极47上形成硅化物垫9、硅化物垫17、及硅化物垫34。硅化物可为硅化镍、另一硅化物等，并且可由任何适当硅化制程形成。
可发生附加操作以形成图1的结构。此附加操作形成ILD1层5、介电质3、通孔31、及金属线2。这些可通过任何适当制程或制程组合形成，这些制程包括例如镶嵌制程、双重镶嵌制程等。
图53A及图53B提供根据本揭露的一些态样的制程5300的流程图，其可用以根据本揭露的一实施例产生集成电路元件。尽管制程5300在本文绘示及描述为一些列动作或事件，但应理解，此等动作或事件的所示顺序不应被解释为限制意义。例如，除了本文绘示及/或描述的彼等之外，一些动作可以与其他动作不同的顺序及/或与其他动作同步地进行。另外，并非所有所示动作对于实施本文描述的一或多个态样或实施例为必需。此外，本文描绘的动作的一或多个可在一或多个单独的动作及/或阶段中进行。
制程5300开始于动作5301，在如图2绘示的基板43上形成垫层，其可为垫氧化物层201及垫氮化物层202。制程5300继续进行动作5302，从记忆体区域90去除垫氧化物层201及垫氮化物层202，如图3绘示。动作5303为在记忆体区域90中凹陷基板43，亦如图3所示。
动作5304为去除垫氧化物层201及垫氮化物层202。动作5305为形成新的垫氧化物层81及新的垫氮化物层82，其在图5绘示。动作5306为形成隔离区域85，如图8绘示。
动作5307为形成氮化物覆盖层86及氧化物覆盖层87，如图6绘示。动作5308为从记忆体区域90去除氮化物覆盖层86及氧化物覆盖层87，如图7绘示。动作5309为形成包括浮动栅极介电层902及浮动栅电极层901的浮动栅极堆叠。动作5310为平坦化以从周边区域91去除浮动栅极，如图8绘示。动作5311为将浮动栅电极层901薄化至要求厚度，如图9及图10绘示。
动作5312为形成包括控制栅极介电层1101、控制栅电极层1102、及控制栅极硬遮罩1103的控制栅极堆叠1105，如图11绘示。动作5313为图案化以界定包括控制栅极介电质13、控制栅电极7、及控制栅极硬遮罩1201的控制栅极，如图12绘示。动作5314为形成控制栅极间隔物11，如图13绘示。
动作5315为蚀刻以界定包括浮动栅极介电质15及浮动栅电极14的浮动栅极。动作5316为形成浮动栅极间隔物1401，如图14绘示。动作5317为掺杂以在记忆体区域25中提供记忆体源极/漏极区域21，如图15绘示。
动作5318为形成擦除栅极介电质19，如图17绘示。动作5319为形成选择栅极介电质22，如图19绘示。动作5320为沉积选择栅电极层2001，如图20绘示。动作5321为将选择栅电极层2001回蚀至约为控制栅电极7的高度以界定擦除栅电极18，如图21绘示。
动作5322为形成选择栅极硬遮罩层2201，如图22绘示。动作5323为自对准蚀刻以从选择栅电极层2001界定选择栅电极23，如图23绘示。动作5324为带去除蚀刻。这导致在高压区域46及核心区域62中薄化控制栅极硬遮罩1103，如图24绘示。动作5325为形成第二ARC2501，如图25绘示。动作5326为减少记忆体堆叠的高度的平坦化蚀刻，如图26绘示。动作5327为沉积记忆体覆盖层2701及虚设BARC 2702，如图27绘示。动作5328为去除虚设BARC2702的平坦化蚀刻，如图28绘示。动作5329为从高压区域46及核心区域62去除记忆体单元堆叠，如图30绘示。
在继续图53B上的流程图之后，制程5300继续动作5330，形成硬遮罩3101，如图30绘示。动作5330为形成光阻及从高压区域46去除硬遮罩3101、垫氮化物层82、及垫氧化物层81，如图32绘示。动作5331为在高压区域46中形成深井布植，如图33绘示。
动作5332为形成高压栅极堆叠3403，如图34绘示。高压栅极堆叠3403包括厚栅极氧化物层3404、多晶硅电极层3401、及高压栅极硬遮罩3402。如图34绘示，这些层中，至少多晶硅电极层3401及高压栅极硬遮罩3402在记忆体区域25及核心区域62中的硬遮罩3101上方形成。
动作5333为形成光阻3501及从核心区域62去除高压栅极堆叠3403、硬遮罩3101、垫氮化物层82、及垫氧化物层81，如图35绘示。动作5334为在核心区域62中形成深井布植，亦如图35绘示。
动作5335为形成虚设栅极堆叠3605，如图36绘示。虚设栅极堆叠3605可包括氧化物层3601、高介电常数介电层3602、虚设电极层3603、及虚设栅极硬遮罩层3604。如图36绘示，这些层中，至少高介电常数介电层3602、虚设栅电极层3603、及虚设栅极硬遮罩层3604在高压区域46及记忆体区域25中的高压栅极硬遮罩3402上方形成。
动作5336为图案化以从高压区域46及记忆体区域25去除虚设栅极堆叠3605，同时在核心区域62中界定虚设栅极3703，如图37绘示。高压栅极硬遮罩3402可为此制程提供蚀刻停止。
动作5337为图案化以从记忆体区域25去除高压栅极堆叠3403，同时在高压区域46中界定高压栅极71，如图38中绘示。硬遮罩3101可为此制程提供蚀刻停止。
动作5338为邻近虚设栅极3703及高压栅极71形成间隔物39，如图39绘示。动作5339为从记忆体区域25去除硬遮罩3101及记忆体覆盖层2701，如图40绘示。动作5340为布植记忆体源极/漏极区域27、轻掺杂高压源极/漏极区域50、及轻掺杂HKMG源极/漏极区域63，分别如图40、图41及图42绘示。遮罩及掺杂步骤的数目取决于不同源极/漏极掺杂类型及浓度的所要求数目。
动作5341为形成第二侧壁间隔物38及选择栅极侧壁间隔物33，如图43绘示。可单独地或同时地形成这些间隔物。动作5342为布植重掺杂记忆体源极/漏极区域26、重掺杂高压栅极源极/漏极区域49、及重掺杂HKMG源极/漏极区域65，如图44绘示。此外，遮罩及掺杂步骤的数目取决于不同源极/漏极掺杂类型及浓度的要求数目。动作5342为退火。此退火修复由布植及活化布植而导致的对基板43的损坏。动作5343为硅化以分别在记忆体区域25、高压区域46、及核心区域62中形成硅化物垫30、硅化物垫51、及硅化物垫67，如图44绘示。
动作5344为从记忆体区域25去除选择栅极硬遮罩2301、控制栅极硬遮罩1201、及擦除栅极硬遮罩2302。此举可通过沉积第二ARC 4501(如图45绘示)及非选择性蚀刻以凹陷所产生表面(如图46绘示)来完成。可随后去除第二ARC 4501，如图47绘示。
动作5345为沉积第一层间介电层，ILD0层29，如图48绘示。此动作之后为动作5346，暴露虚设栅电极3702。此动作可通过平坦化实现，如图49绘示。动作5347为去除虚设栅电极3702，如图50绘示。
动作5348为针对HKMG栅极70沉积及/或生长金属。此动作之后为动作5349，进行CMP以去除多余金属，仅留下形成金属电极57的金属，如图51绘示。此CMP可为将在1μm2或更大面积的金属栅极中导致过度下陷的操作。CMP之后，具有高压栅极71的上表面5101与HKMG栅极70的上表面5102对准。
动作5350为硅化以分别在选择栅电极23、擦除栅电极18、及高压栅电极47上形成硅化物垫9、硅化物垫17、及硅化物垫34，如图52绘示。遮罩可用以防止硅化物形成于控制栅电极7上。
动作5351为形成包括通孔31、金属线2、及ILD1层5的第一金属互连层，如图1绘示。动作5352为附加操作以完成IC元件的形成，包括进一步后段(back-end-of-line；BEOL)处理。应理解，制程5300为置换栅极制程或栅极最后制程。
本教示的一些态样涉及IC，IC包括多个金属栅极及多个多晶硅栅极，每个金属栅极具有金属电极及高介电常数介电质，每个多晶硅栅极具有多晶硅电极及习用(非高介电常数)介电质。多晶硅栅极为具有厚介电层的高压栅极。度晶硅栅极可适于在10V或更高的栅极电压下操作。在这些教示的一些中，多晶硅栅极的介电质比金属栅极的介电质厚。在这些教示的一些中，多晶硅栅极的面积大于1μm2。在这些教示的一些中，多晶硅栅极的面积大于3μm2。在这些教示的一些中，多晶硅电极的顶表面与金属电极的顶表面对准。在这些教示的一些中，IC元件包括嵌入式快闪记忆体。在这些教示的一些中，金属栅极为置换栅极制程的产物。金属栅极可具有在1000℃下由5秒热处理改变的阈电压。
在所述的IC中，多晶硅栅极具有一面积，面积大于所述高介电常数金属栅极的设计极限。
在所述的IC中，半导体基板在源极及漏极区域中布植有掺杂剂，源极及漏极区域可操作地与该高介电常数金属栅极相关联；源极及漏极区域具有布植掺杂剂后由退火产生的物理结构；以及高介电常数金属栅极具有结构，若高介电常数金属栅极已经受退火步骤，则所述结构将不为可能的。
在所述的IC中，多晶硅栅极包括多晶硅电极、通道区域、及从通道区域跨至多晶硅电极的一或多个介电质；以及多晶硅栅极的一或多个介电质中的每一者具有一介电常数，介电常数低于任意高介电常数介电质的介电常数。
本教示的一些态样涉及包括半导体基板的IC，半导体基板具有记忆体区域及周边区域。记忆体元件形成于记忆体区域中，及高介电常数金属栅极形成于周边区域中。多晶硅栅极亦形成于周边区域中。多晶硅栅极具有一面积，此面积大于高介电常数金属栅极的面积。多晶硅栅极可具有大于高介电常数金属栅极的设计极限的一面积，其小于1μm2。在这些教示的一些中，在可操作地与高介电常数金属栅极相关联的源极及漏极区域中，半导体基板布植入掺杂剂，及高介电常数金属栅极具有将由最小热处理改变的阈电压，此最小热处理将使布植有掺杂剂的半导体基板退火。最小热处理可大于1000℃下的5秒热处理。
本教示的一些态样涉及形成IC的方法，此方法包括以下步骤：在基板的第一区域中形成栅极氧化物层，在基板的第一区域及基板的第二区域中的每一者上方形成多晶硅层，以及在多晶硅层上方形成保护层。在掩蔽第一区域的情况下，从第二区域去除保护层及多晶硅层。随后在第一区域及第二区域上方形成高介电常数介电层及虚设电极层。随后图案化虚设电极层及高介电常数介电层以在第二区域中形成虚设栅极并从第一区域去除虚设电极层及高介电常数介电层。随后图案化保护层及多晶硅层以在第一区域中界定多晶硅栅极。邻近虚设栅极形成间隔物。在填充相邻间隔物之后，平坦化第一区域及第二区域。接着虚设电极层从虚设栅极去除并且替换为金属。接着平坦化第一区域及第二区域以去除多余金属。
在这些教示的一些中，在图案化虚设电极层及高介电常数介电层以形成虚设栅极之前，在虚设电极层上方形成硬遮罩。在这些教示的一些中，在形成栅极氧化物层之前，形成硬遮罩并从第一区域选择性地去除硬遮罩。在这些教示的一些中，在形成间隔物之后布植源极/漏极区域，及在用金属替换虚设电极层之前退火布植区域。在平坦化第一区域及第二区域以去除多余金属之后，对多晶硅栅极执行硅化制程。在这些教示的一些中，方法进一步包括在基板的第三区域中形成快闪记忆体元件的步骤。
在所述的方法中，多晶硅栅极每个具有大于1μm2的面积。
在所述的方法中，多晶硅栅极可作为高压栅极操作。
在所述的方法中，栅极氧化物具有一厚度，该厚度适于10V或更高的栅极电压。
上文概述若干实施例的特征或实例，使得熟悉此项技术者可更好地理解本揭露的一实施例的态样。熟悉此项技术者应了解，可轻易使用本揭露的一实施例作为设计或修改其他制程及结构的基础，以便实施本文所介绍的实施例或实例的相同目的及/或实现相同优势。熟悉此项技术者亦应认识到，此类等效结构并未脱离本揭露的一实施例的精神及范畴，且可在不脱离本揭露的一实施例的精神及范畴的情况下产生本文的各种变化、替代及更改。

Claims (10)

1.一种集成电路，其特征在于，包括：
多个金属栅极，每个包括一金属电极及一高介电常数介电质；以及
多个多晶硅栅极，每个包括一多晶硅电极、一通道区域、及从该通道区域跨至该多晶硅电极的一或多个介电质；
其中该些多晶硅栅极的该一或多个介电质中的每一者具有一介电常数，该介电常数低于任意高介电常数介电质的一介电常数；以及
该些多晶硅栅极中的一或多者为一高压元件。
2.根据权利要求1所述的集成电路，其特征在于，该些多晶硅电极具有与该些金属电极的多个顶表面对准的多个顶表面。
3.根据权利要求1所述的集成电路，其特征在于，进一步包括嵌入式快闪记忆体。
4.根据权利要求1所述的集成电路，其特征在于，该一或多个介电质具有一厚度，该厚度大于该高介电常数介电质的一厚度。
5.根据权利要求1所述的集成电路，其特征在于，该些多晶硅栅极每个具有大于1μm2的一面积。
6.一种集成电路，其特征在于，包括：
一半导体基板，包括一记忆体区域及一周边区域；
一记忆体元件，形成于该记忆体区域中；
一高介电常数金属栅极，形成于该周边区域中；以及
一多晶硅栅极，形成于该周边区域中；
其中该多晶硅栅极具有一面积，该面积大于该高介电常数金属栅极的一面积。
7.根据权利要求6所述的集成电路，其特征在于，该高介电常数金属栅极具有一顶表面，该顶表面与该多晶硅栅极的一顶表面对准。
8.一种形成集成电路的方法，其特征在于，包括以下步骤：
提供一半导体基板，该半导体基板包括一第一区域及一第二区域；
形成一栅极氧化物层于该第一区域中；
形成一多晶硅层于该第一区域及该第二区域上方，借此在该栅极氧化物层上方形成该多晶硅层；
形成一保护层于该多晶硅层上方；
掩蔽该第一区域；
在掩蔽该第一区域的情况下，从该第二区域选择性地去除该保护层及该多晶硅层；
形成一高介电常数介电层于该第一区域及该第二区域上方；
形成一虚设电极层于该高介电常数介电层上方；
图案化该虚设电极层及该高介电常数介电层以在该第二区域中形成多个虚设栅极并从该第一区域去除该虚设电极层及该高介电常数介电层；
图案化该保护层及该多晶硅层以在该第一区域中界定多个多晶硅栅极；
邻近该些虚设栅极形成多个间隔物；
填充邻近该些间隔物的一区域；
平坦化该第一区域及该第二区域；
从该些虚设栅极去除该虚设电极层以形成多个空隙区域；
在该第一区域及该第二区域上方沉积金属，借此该金属填充该些空隙区域以形成多个高介电常数金属栅极；以及
平坦化该第一区域及该第二区域以去除多余金属。
9.根据权利要求8所述的方法，其特征在于，进一步包括以下步骤：在图案化该虚设电极层及该高介电常数介电层以形成虚设栅极之前，在该虚设电极层上方形成一硬遮罩。
10.根据权利要求8所述的方法，其特征在于，进一步包括以下步骤：在平坦化该第一区域及该第二区域以去除多余金属之后，对该些多晶硅栅极执行一硅化物制程。
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