CN112331561B - Method for improving yield of chemical mechanical polishing - Google Patents
Method for improving yield of chemical mechanical polishing Download PDFInfo
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- CN112331561B CN112331561B CN202011309976.9A CN202011309976A CN112331561B CN 112331561 B CN112331561 B CN 112331561B CN 202011309976 A CN202011309976 A CN 202011309976A CN 112331561 B CN112331561 B CN 112331561B
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- 238000000034 method Methods 0.000 title claims abstract description 58
- 238000005498 polishing Methods 0.000 title claims abstract description 45
- 239000000126 substance Substances 0.000 title claims abstract description 42
- 230000008569 process Effects 0.000 claims abstract description 12
- 230000000694 effects Effects 0.000 claims description 26
- 238000003475 lamination Methods 0.000 claims description 23
- 238000004364 calculation method Methods 0.000 claims description 14
- 238000001514 detection method Methods 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 5
- 238000012935 Averaging Methods 0.000 claims description 3
- 238000002715 modification method Methods 0.000 claims description 3
- 230000007547 defect Effects 0.000 description 17
- 230000006872 improvement Effects 0.000 description 11
- 238000010586 diagram Methods 0.000 description 8
- 238000000227 grinding Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 5
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- 238000012876 topography Methods 0.000 description 3
- 230000009471 action Effects 0.000 description 2
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- 238000004458 analytical method Methods 0.000 description 1
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- 238000006243 chemical reaction Methods 0.000 description 1
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- 238000002474 experimental method Methods 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000011882 ultra-fine particle Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30625—With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
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- H—ELECTRICITY
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
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Abstract
The invention discloses a method for improving the yield of chemical mechanical polishing, which comprises the following steps: firstly, carrying out grid division on a chip layout to form a plurality of layout panes, and extracting characteristic parameters in the layout panes; analyzing the relation between the characteristic parameters in the layout pane and the average surface height in the area of the wafer pane corresponding to the wafer after chemical mechanical polishing, and selecting the most relevant characteristic parameters; thirdly, finding out a hot spot area after chemical mechanical polishing according to the most relevant characteristic parameters on the chip layout; and step four, modifying the layout graph of the hot spot area on the chip layout to eliminate the hot spot. The invention can reduce the process complexity and cost required by improving the yield of chemical mechanical polishing.
Description
Technical Field
The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly, to a method for improving a Chemical Mechanical Polishing (CMP) yield.
Background
Topological fluctuations in the surface topography of the metal layer during the fabrication of integrated circuits (INTEGRATED CIRCUIT, ICs) can affect the depth of focus of lithography and the stress distribution of the interconnect structure. To achieve the flatness necessary for manufacturing the multilayer circuit, a chemical mechanical polishing process is typically used to planarize the surface thereof. Among them, CMP is the best global planarization method in very large scale integrated circuits, which is to form a smooth and flat surface on the surface of a polished medium by chemical etching action of a polishing liquid and polishing action of ultra-fine particles.
Chemical mechanical polishing is affected by various factors in actual operation, including: the material of the grinding pad, the selection of grinding fluid, the rotation speed and pressure of the grinding head, the layout characteristics of the chip and the like. However, in a specific manufacturing process, a fixed optimum grinding condition is generally adopted in consideration of various factors which may cause an uncertain effect. So under the same process, the difference of the surface topography of the chips after CMP mainly depends on the layout characteristics of the chips.
To improve the CMP yield, chip manufacturing companies use CMP models to predict post-CMP chip surface topography. However, CMP modeling is complex, a large amount of experimental data is required, and experiments of multiple batches and multiple chips are often not performed at the same time. The great difference of polishing rate characteristic curves of reaction process characteristics caused by the different service lives of consumable products of CMP polishing equipment leads to the fact that data have errors which are difficult to control, so that the accuracy of a CMP model is severely challenged.
The modeling cost of the CMP process at the present stage is very high, and the accepted commercial CMP process model is few, so how to improve the CMP yield and thus reduce the cost is important.
Disclosure of Invention
The invention aims to provide a method for improving the yield of chemical mechanical polishing, which can reduce the process complexity and cost required by improving the yield of chemical mechanical polishing.
In order to solve the above technical problems, the method for improving the yield of chemical mechanical polishing provided by the invention comprises the following steps:
step one, carrying out grid division on a chip layout to form a plurality of layout panes, and extracting a plurality of characteristic parameters in each layout pane.
Analyzing the relation between the characteristic parameters in the layout pane and the average surface height in the area of the wafer pane corresponding to the wafer after chemical mechanical polishing, and obtaining the most relevant characteristic parameters from a plurality of characteristic parameters.
And thirdly, finding out the hot spot area after chemical mechanical polishing according to the most relevant characteristic parameters on the chip layout.
And step four, modifying the layout graph of the hot spot area on the chip layout to eliminate hot spots.
Further improvement is that the method further comprises:
and fifthly, forming a wafer pattern layer on the wafer according to the modified chip layout, and then carrying out chemical mechanical polishing.
A further improvement is that the wafer pattern layer comprises a metal layer.
In a further improvement, in the first step, the meshing is performed by using a mesh unit with a fixed size.
A further improvement is that the grid cells are 10 x N/20 microns in length and width, N being the process node of the product.
In the second step, the surface height value on the wafer pane is obtained by scanning an Atomic Force Microscope (AFM) machine, and the average surface height in the area of the wafer pane is obtained by averaging the surface height value in the area of the wafer pane.
In a further improvement, in the second step, the pearson correlation coefficient is used to analyze the relationship between the surface heights of the plurality of wafer panes and the characteristic parameters to obtain the most relevant characteristic parameters.
Further improvement is that the characteristic parameters extracted in the first step comprise equivalent line width, equivalent density, equivalent circumference and equivalent spacing.
In the second step, the equivalent density and the surface height of the wafer grid have the strongest negative correlation, and the equivalent density is selected as the most relevant characteristic parameter.
The further improvement is that the third step comprises:
And the chip layout comprises a plurality of layout pattern layers, and the hot spot area is found out according to the lamination effect of the plurality of overlapped layout pattern layers on the chemical mechanical polishing.
The further improvement is that the lamination effect comprises a two-layer lamination effect, and the searching method of the hot spot area corresponding to the two-layer lamination effect comprises the following steps:
And calculating the difference between the equivalent density in the current layer layout pane and the equivalent density in the lower layer layout pane and obtaining a first difference value.
And comparing the first difference value with a first specification value, and if the first difference value exceeds the range of the first specification value, indicating that the current layer layout pane is the hot spot area.
The first specification value is a maximum density difference of equivalent densities in the wafer pane between two of the wafer pattern layers supported by the on-line chemical mechanical polishing.
In a further improvement, the calculation formula of the first difference value is delta 1＝Si-S(i-1).
Or the calculation formula of the first difference value is delta 1＝Si/S(i-1).
S i is the equivalent density in the current layer layout pane, i represents the number of layers of the current layer;
S (i-1) is the equivalent density in the underlying layout pane.
Delta 1 is the first difference value.
In a further improvement, the lamination effect comprises a three-layer lamination effect, and the method for searching the hot spot area corresponding to the three-layer lamination effect comprises the following steps:
and calculating the difference of the equivalent density in the current layer layout pane, the equivalent density in the lower layer layout pane and the equivalent density in the lower layer layout pane, and obtaining a second difference value.
And comparing the second difference value with a second specification value, and if the second difference value exceeds the range of the second specification value, indicating that the current layer layout pane is the hot spot area.
The second specification value is a maximum density difference of equivalent densities in the wafer pane between the three wafer pattern layers supported by the on-line chemical mechanical polishing.
In a further improvement, the calculation formula of the second difference value is delta 2＝Si+S(i-1)-S(i-2).
Or the calculation formula of the second difference value is delta 2＝Si*S(i-1)/S(i-2).
S i is the equivalent density in the current layer layout pane; i represents the number of layers of the current layer.
S (i-1) is the equivalent density in the underlying layout pane.
S (i-2) is the equivalent density in the lower layout pane.
Delta 2 is the second difference value.
In the third step, after the hot spot area is found, the method further comprises the step of finding out the current layer layout pane corresponding to the hot spot area which can be mutually influenced on the current layer layout graphic layer.
In the third step, the step of finding out the current layer layout pane corresponding to the hot spot areas which are mutually affected includes:
and forming a transverse detection area by taking the length sum of r layout panes as the radius and taking the current layer layout pane corresponding to the selected hot spot area as the center.
If there are more than m hot spot areas in the lateral detection area, the hot spot areas in the lateral detection area will interact with each other such that the risk is increased, and r and m are both natural numbers.
In a fourth step, the modification method comprises the following steps:
And reducing the equivalent density in the current layer layout pane or increasing the equivalent density in the lower layer layout pane at the same position as the current layer layout pane.
The invention does not need to carry out CMP modeling and change the CMP process, the invention determines the most relevant characteristic parameters by carrying out grid division and characteristic extraction on the chip layout and combining the CMP process, can find out all hot spot areas after CMP grinding through the most relevant characteristic parameters, and can eliminate hot spots through the modification of layout patterns of the hot spot areas, thereby improving the CMP yield.
Drawings
The invention is described in further detail below with reference to the attached drawings and detailed description:
FIG. 1 is a flow chart of a method for improving the yield of chemical mechanical polishing according to an embodiment of the invention;
FIG. 2 is a layout pattern layer of a chip layout with 3 layers superimposed together in a method of an embodiment of the invention;
FIG. 3 is a schematic diagram of a current layer layout pane corresponding to a hot spot area which is found out in a current layer layout graphic layer in the method of the embodiment of the invention;
FIG. 4A is a schematic diagram of finding out a hot spot area according to the most relevant characteristic parameters when the current layer layout graphic layer is an M4 layer by adopting the method of the embodiment of the invention;
FIG. 4B is a layout diagram corresponding to the dashed circle 102 in FIG. 4A;
FIG. 4C is a wafer pattern on the wafer consistent with the position of FIG. 4B;
FIG. 4D is a graph showing the defect in FIG. 4C after the chemical mechanical polishing of the wafer is completed without performing step four of the present invention;
FIG. 5A is a schematic diagram of finding out a hot spot area according to the most relevant characteristic parameters when the current layer layout graphic layer is M5 layers by adopting the method of the embodiment of the invention;
FIG. 5B is a layout diagram corresponding to the dashed circle 103 in FIG. 4A;
FIG. 5C is a layout diagram corresponding to the dashed circle 104 in FIG. 4A;
FIG. 5D is a wafer pattern on the wafer consistent with the position of FIG. 5B;
FIG. 5E is a wafer pattern on the wafer consistent with the position of FIG. 5C;
Fig. 5F is a graph showing the defect distribution of fig. 5D and 5E after the chemical mechanical polishing of the wafer is completed without performing step four of the present invention.
Detailed Description
FIG. 1 is a flow chart of a method for improving the yield of chemical mechanical polishing according to an embodiment of the invention; as shown in FIG. 2, the method of the embodiment of the invention is characterized in that 3 layers of the chip layout are overlapped; FIG. 3 is a schematic diagram of a current layer layout pane 1 corresponding to a hot spot area that is found out in a current layer layout graphic layer in the method of the embodiment of the invention; the method for improving the yield of chemical mechanical polishing comprises the following steps:
step one, carrying out grid division on a chip layout to form a plurality of layout panes, and extracting a plurality of characteristic parameters in each layout pane.
Typically, the file format of the chip layout is a GDS file.
The chips often require multiple photolithography and formation of multiple wafer patterning layers, including metal layers, when formed on a wafer. The chip layout also includes multiple layout pattern layers. After the layout pane is divided, the positions of the layout panes corresponding to the layout graphic layers are in one-to-one correspondence, as in the case of 3 layers corresponding to the metal layers in fig. 3, the positions of the layout panes 3, 2 and 1 of the layout graphic layers M1, M2 and M3, namely the positions of the transverse areas, are the same, and in the longitudinal direction, the layout panes 3, 2 and 1 are overlapped together.
In the embodiment of the invention, the grid division is performed by adopting grid cells with fixed sizes. Preferably, it is: the length and width of the size of the grid unit are N/2 micrometers, and N is a process node of the product.
The extracted characteristic parameters comprise equivalent line width, equivalent density, equivalent circumference and equivalent spacing.
Analyzing the relation between the characteristic parameters in the layout pane and the average surface height in the area of the wafer pane corresponding to the wafer after chemical mechanical polishing, and obtaining the most relevant characteristic parameters from a plurality of characteristic parameters.
In the embodiment of the invention, the surface height value on the wafer pane is obtained by scanning an AFM machine table, and the average surface height in the area of the wafer pane is obtained by averaging the surface height value in the area of the wafer pane.
The pearson correlation coefficient is used to analyze the relationship between the surface heights of the plurality of wafer panes and the characteristic parameters to obtain the most relevant characteristic parameters.
And obtaining that the equivalent density has the strongest negative correlation with the surface height of the wafer grid through calculation, and selecting the equivalent density as the most relevant characteristic parameter. For example, according to 2600 surface height values of the wafer panes and the characteristic parameters of the corresponding layout panes, the applicant obtains that the equivalent density has the strongest negative correlation with the surface height of the wafer panes by analysis through the pearson correlation coefficient, and the equivalent density is-0.84. The negative correlation is: and when the equivalent density in the layout pane is larger, the surface height of the wafer pane corresponding to the CMP is lower.
And thirdly, finding out the hot spot area after chemical mechanical polishing according to the most relevant characteristic parameters on the chip layout.
In the embodiment of the invention, the chip layout comprises a plurality of layout pattern layers, and the hot spot area is found out according to the lamination effect of the chemical mechanical polishing on the plurality of overlapped layout pattern layers.
The lamination effect includes a lamination effect of two layers, such as lamination effect corresponding to superposition of two layers of layout pattern layers M3 and M2 in fig. 2, and the method for searching the hot spot area corresponding to the two lamination effect includes:
And calculating the difference between the equivalent density in the current layer layout pane 1 and the equivalent density in the lower layer layout pane 2 and obtaining a first difference value.
And comparing the first difference value with a first specification value, and if the first difference value exceeds the range of the first specification value, indicating that the current layer layout pane 1 is the hot spot area.
The first specification value is a maximum density difference of equivalent densities in the wafer pane between two of the wafer pattern layers supported by the on-line chemical mechanical polishing.
Preferably, the calculation formula of the first difference value is δ 1＝Si-S(i-1).
Or the calculation formula of the first difference value is delta 1＝Si/S(i-1).
S i is the equivalent density in the current layer layout pane 1, i represents the number of layers of the current layer;
s (i-1) is the equivalent density in the underlying layout pane 2.
Delta 1 is the first difference value.
Because the equivalent density has the strongest negative correlation with the surface height of the wafer window, when the equivalent density of the current layer layout pane 1 is higher than the equivalent density of the lower layer layout pane 2by a certain value, the risk of CMP penetration corresponding to the current layer layout pane 1 is caused. Taking the calculation formula delta 1＝Si/S(i-1) as an example, the first specification value can take a minimum value, for example, 80%, and when delta 1 is greater than the first specification value, namely 80%, the corresponding current layer layout pane 1 is the hot spot area.
The embodiment of the invention can also be as follows: the lamination effect includes a lamination effect of three layers, such as lamination effect corresponding to superposition of two layers of layout pattern layers M3, M2 and M1 in fig. 2, and the method for searching the hot spot area corresponding to the three layers of lamination effect includes:
And calculating the difference of the equivalent density in the current layer layout pane 1, the equivalent density in the lower layer layout pane 2 and the equivalent density in the lower layer layout pane 3, and obtaining a second difference value.
And comparing the second difference value with a second specification value, and if the second difference value exceeds the range of the second specification value, indicating that the current layer layout pane 1 is the hot spot area.
The second specification value is a maximum density difference of equivalent densities in the wafer pane between the three wafer pattern layers supported by the on-line chemical mechanical polishing.
The calculation formula of the second difference value is delta 2＝Si+S(i-1)-S(i-2).
Or the calculation formula of the second difference value is delta 2＝Si*S(i-1)/S(i-2).
S i is the equivalent density in the current layer layout pane 1; i represents the number of layers of the current layer.
S (i-1) is the equivalent density in the underlying layout pane 2.
S (i-2) is the equivalent density in the lower layout pane 3.
Delta 2 is the second difference value. Similarly, the second specification value can take a minimum value, and when the second difference value is greater than the second difference value, the corresponding current layer layout pane 1 is the hot spot area.
The same can be said for the superposition effect of more layers.
In the embodiment of the invention, after the hot spot area is found, the method further comprises the step of finding out the current layer layout pane 1 corresponding to the hot spot area which can be mutually influenced on the current layer layout graphic layer. As shown in fig. 3, the step of finding the current layer layout pane 1 corresponding to the hot spot areas that will affect each other includes:
and forming a transverse detection area by taking the length sum of r layout panes as a radius with the current layer layout pane 1 corresponding to the selected hot spot area as the center. In fig. 3, reference numeral 101 denotes the current layer layout pattern layer, and a plurality of current layer layout panes 1 are formed by grid division on the current layer layout pattern layer 101. Wherein the current layer layout pane 1, which is denoted by the reference I alone, is centered and the lateral detection area is shown as an area with grey filling.
If there are more than m hot spot areas in the lateral detection area, the hot spot areas in the lateral detection area will interact with each other such that the risk is increased, and r and m are both natural numbers. In fig. 3, marks L, J, K, and M are all hot spot areas around the current layer layout pane 1 corresponding to the mark I, so that the risk of the hot spot areas of the current layer layout pane 1 corresponding to the marks I, L, J, K, and M is increased, and the hot spot areas are all areas with extremely high risk, and special attention is required for subsequent modification.
And step four, modifying the layout graph of the hot spot area on the chip layout to eliminate hot spots. The modification method in the fourth step comprises the following steps:
decreasing the equivalent density in the current layer layout pane 1 or increasing the equivalent density in the lower layer layout pane 2 at the same position as the current layer layout pane 1.
And fifthly, forming a wafer pattern layer on the wafer according to the modified chip layout, and then carrying out chemical mechanical polishing.
The embodiment of the invention does not need CMP modeling, so that the CMP process is not required to be changed, the invention determines the most relevant characteristic parameters by carrying out grid division and characteristic extraction on the chip layout and combining the CMP process, can find out all hot spot areas after CMP grinding through the most relevant characteristic parameters, and can eliminate hot spots through the modification of the layout graph of the hot spot areas, thereby improving the CMP yield.
For a clearer description of the effects of the embodiments of the present invention, the following description will be made with reference to the accompanying drawings:
As shown in fig. 4A, the method according to the embodiment of the present invention is used to find out the hot spot area according to the most relevant feature parameters when the current layer layout graphic layer 101 is the M4 layer; on the current layer layout graphic layer 101, after the third step of the embodiment of the present invention, a plurality of the hot spot areas can be obtained, and in fig. 4A, the hot spot areas to be analyzed are individually circled by the virtual coil 102.
As shown in fig. 4B, is the corresponding layout pattern at the dashed circle 102 in fig. 4A. As shown in fig. 4C, which is a wafer pattern consistent with the position of fig. 4B on the wafer, that is, fig. 4B is a layout pattern of GDS file format, and fig. 4C is a wafer pattern after the CMP is completed without modification of step four of the embodiment of the present invention on the wafer, it can be seen that the pattern structures and positions of the wafer pattern and the layout pattern are consistent, but there is a wear-through defect 201 on the wafer pattern. On this surface, the third step of the embodiment of the present invention can well predict the hot spot area, and finally eliminate the hot spot.
FIG. 4D is a graph showing the defect distribution of FIG. 4C after the chemical mechanical polishing of the wafer is completed without performing step four of the present invention; it can be seen that there are a plurality of wear-through defects 203 on the wafer 202, the wear-through defects 203 in fig. 4D corresponding to the wear-through defects 201 in fig. 4C.
If the method of the present embodiment is adopted, the wear defect 203 in fig. 4D can be eliminated.
FIG. 5A is a schematic diagram of finding out a hot spot area according to the most relevant characteristic parameters when the current layer layout graphic layer is M5 layers by adopting the method of the embodiment of the invention; on the current layer layout graphic layer 101a, after the third step of the embodiment of the present invention, a plurality of the hot spot areas can be obtained, and in fig. 5A, the hot spot areas to be analyzed are circled by virtual coils 103 and 104 alone.
As shown in fig. 5B, the layout pattern corresponding to the dashed circle 103 in fig. 5A; as shown in fig. 5D, a wafer pattern is formed on the wafer at a position consistent with that of fig. 5B. As shown in fig. 5C, is the corresponding layout pattern at the dashed circle 104 in fig. 5A. As shown in fig. 5E, a wafer pattern is formed on the wafer at a position consistent with that of fig. 5C. It can be seen that the wafer pattern and the layout pattern are identical in pattern structure and position, but have a wear-through defect on the wafer pattern, as shown by wear-through defect 204 in fig. 5D and wear-through defect 205 in fig. 5E, respectively. On this surface, the third step of the embodiment of the present invention can well predict the hot spot area, and finally eliminate the hot spot.
As shown in fig. 5F, the distribution of defects in fig. 5D and 5E occurs after the chemical mechanical polishing of the wafer is completed without performing step four of the present embodiment; it can be seen that there are a plurality of wear-through defects 206 on the wafer 202a, the wear-through defects 206 in fig. 5F correspond to the wear-through defects 204 in fig. 5D and the wear-through defects 205 in fig. 5E.
If the method of the present embodiment is employed, the wear-through defect 206 that appears in FIG. 5F can be eventually eliminated.
The present invention has been described in detail by way of specific examples, but these should not be construed as limiting the invention. Many variations and modifications may be made by one skilled in the art without departing from the principles of the invention, which is also considered to be within the scope of the invention.
Claims (15)
1. A method for improving the yield of chemical mechanical polishing is characterized by comprising the following steps:
Firstly, performing grid division on a chip layout to form a plurality of layout panes, and extracting a plurality of characteristic parameters in each layout pane;
Analyzing the relation between the characteristic parameters in the layout pane and the average surface height in the area of the wafer pane corresponding to the wafer after chemical mechanical polishing, and obtaining the most relevant characteristic parameters from a plurality of characteristic parameters;
Thirdly, finding out a hot spot area after chemical mechanical polishing according to the most relevant characteristic parameters on the chip layout;
The chip layout comprises a plurality of layout pattern layers, and the hot spot area is found out according to the lamination effect of the plurality of overlapped layout pattern layers on the chemical mechanical polishing;
Step four, modifying the layout graph of the hot spot area on the chip layout to eliminate hot spots;
In the fourth step, the modification method includes:
And reducing the equivalent density in the current layer of layout pane or increasing the equivalent density in the lower layer of layout pane at the same position as the current layer of layout pane.
2. The method of claim 1, further comprising:
and fifthly, forming a wafer pattern layer on the wafer according to the modified chip layout, and then carrying out chemical mechanical polishing.
3. The method of improving the yield of chemical mechanical polishing as claimed in claim 2, wherein: the wafer pattern layer includes a metal layer.
4. The method of claim 1, wherein the step of increasing the yield of chemical mechanical polishing comprises: in the first step, the grid division is performed by adopting grid units with fixed sizes.
5. The method of claim 4, wherein: the length and width of the size of the grid unit are 10 x [ N/20] micrometers, and N is a process node of the product.
6. The method of claim 1, wherein the step of increasing the yield of chemical mechanical polishing comprises: and in the second step, the surface height value on the wafer pane is obtained through scanning by an AFM machine table, and the average surface height in the area of the wafer pane is obtained by averaging the surface height value in the area of the wafer pane.
7. The method of claim 6, wherein: and in the second step, the pearson correlation coefficient is used for analyzing the relationship between the surface heights of a plurality of wafer panes and the characteristic parameters to obtain the most relevant characteristic parameters.
8. The method of claim 7, wherein: the characteristic parameters extracted in the first step comprise equivalent line width, equivalent density, equivalent circumference and equivalent spacing.
9. The method of claim 8, wherein: in the second step, the equivalent density has the strongest negative correlation with the surface height of the wafer grid, and the equivalent density is selected as the most relevant characteristic parameter.
10. The method of claim 9, wherein: the lamination effect comprises a two-layer lamination effect, and the searching method of the hot spot area corresponding to the two-layer lamination effect comprises the following steps:
calculating the difference between the equivalent density in the current layer layout pane and the equivalent density in the lower layer layout pane and obtaining a first difference value;
Comparing the first difference value with a first specification value, and if the first difference value exceeds the range of the first specification value, indicating that the current layer layout pane is the hot spot area;
the first specification value is a maximum density difference of equivalent densities in the wafer pane between two wafer image layers supported by the chemical mechanical polishing on-line.
11. The method of claim 10, wherein the step of increasing the yield of chemical mechanical polishing comprises: the calculation formula of the first difference value is delta 1＝Si-S(i-1);
Or the calculation formula of the first difference value is delta 1＝Si/S(i-1);
s i is the equivalent density in the current layer layout pane, i represents the number of layers of the current layer;
s (i-1) is the equivalent density in the lower layer layout pane;
Delta 1 is the first difference value.
12. The method of claim 9, wherein: the lamination effect comprises a three-layer lamination effect, and the method for searching the hot spot area corresponding to the three-layer lamination effect comprises the following steps:
Calculating the difference of the equivalent density in the current layer layout pane, the equivalent density in the lower layer layout pane and obtaining a second difference value;
Comparing the second difference value with a second specification value, and if the second difference value exceeds the range of the second specification value, indicating that the current layer layout pane is the hot spot area;
the second specification value is a maximum density difference of equivalent densities in the wafer pane between the three wafer pattern layers supported by the chemical mechanical polishing on-line.
13. The method of claim 12, wherein: the calculation formula of the second difference value is delta 2＝Si+S(i-1)-S(i-2);
Or the calculation formula of the second difference value is delta 2＝Si*S(i-1)/S(i-2);
S i is the equivalent density in the current layer layout pane; i represents the number of layers of the current layer;
s (i-1) is the equivalent density in the lower layer layout pane;
S (i-2) is the equivalent density in the lower layer layout pane;
Delta 2 is the second difference value.
14. The method of any one of claims 9 to 13, wherein: and thirdly, after the hot spot areas are found, the method further comprises the step of finding out the current layer layout panes corresponding to the hot spot areas which are mutually influenced on the current layer layout graphic layer.
15. The method of claim 14, wherein: in the third step, the step of finding out the current layer layout pane corresponding to the hot spot areas which are mutually affected includes:
forming a transverse detection area by taking the length sum of r layout panes as the radius and taking the current layer layout pane corresponding to the selected hot spot area as the center;
If there are more than m hot spot areas in the lateral detection area, the hot spot areas in the lateral detection area will interact with each other such that the risk is increased, and r and m are both natural numbers.
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