JP2012221104A - Uneven distribution rate calculation method, method for manufacturing semiconductor device and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an uneven distribution rate calculation method capable of determining whether or not there exists such a type or layer that Cu residue is likely to be generated from layout data.SOLUTION: A CPU is configured to execute: a step S13 of calculating pattern density for each verification area of a predetermined size in a verification layer; a step S14 of discriminating the calculated pattern density into a plurality of density ranges, and creating a plurality of density maps MAP0 to MAP7 showing the distribution of pattern density belonging to each density range; a step S15 of adding predetermined amounts of plus shift to each of those density maps MAP0 to MAP7; a step S16 of overlapping the density maps MAP0 to MAP7 combined such that the density difference of the pattern density becomes a first reference value or more, and extracting an area overlapped in the both density maps; a step S17 of calculating the total area of the extracted areas; and a step S18 of comparing the calculated total area with a second reference value.

Description

  The present invention relates to an uneven distribution rate calculation method, a semiconductor device manufacturing method, and a program.

  Conventionally, an aluminum (Al) wiring layer has been widely used as a wiring layer of a semiconductor device. However, in order to meet the recent demand for higher integration and miniaturization of semiconductor devices, the resistance is lower than that of aluminum and resistance to electromigration. An excellent copper (Cu) wiring layer has been used. However, Cu wiring is not easy to pattern by dry etching like Al wiring. For this reason, a so-called damascene method in which a Cu layer is embedded in a wiring groove (a groove having a wiring pattern shape) formed in an insulating film is frequently used for forming a Cu wiring.

Here, a method for forming a Cu wiring by a typical damascene method will be described with reference to FIG.
As shown in FIG. 14A, a flat insulating film 60 is formed on a substrate (not shown), and a wiring groove 60X is formed in the insulating film 60. One wiring groove 60X having a wide opening is formed in the first region 70 on the right side in the drawing, and a plurality of elongated wiring grooves 60X having narrow openings are formed in the second region 71 on the left side in the drawing. Has been.

  Next, as shown in FIG. 14B, a barrier metal 61 is formed on the surface of the insulating film 60 and the inner surface of the wiring groove 60X. As a material of the barrier metal 61, for example, tantalum nitride (TaN), titanium nitride (TiN), tungsten (W), or the like can be used. The barrier metal 61 is for preventing Cu filled in the wiring trench 60 </ b> X from diffusing into the insulating film 60 in a subsequent process.

  Subsequently, as shown in FIG. 14C, a seed layer 62 is formed on the barrier metal 61. For example, Cu can be used as the material of the seed layer 62. The barrier metal 61 and the seed layer 62 can be formed by sputtering or CVD.

  Next, as shown in FIG. 14D, by performing electroplating using the seed layer 62 as an electrode, a Cu layer 63 filling the wiring trench 60X and extending to the surface of the insulating film 60 is deposited. Thereafter, the excess Cu layer 63 on the surface of the insulating film 60 is removed by chemical mechanical polishing (CMP), leaving a Cu layer 63 filling the wiring trench 60X as shown in FIG. Is formed as Cu embedded wiring 64. In the CMP process, the seed layer 62 and the barrier metal 61 on the surface of the insulating film 60 are also removed so that the surface of the insulating film 60 is exposed.

  In the above-described method of forming the Cu embedded wiring 64 by the damascene method, when the wiring groove 60X is filled with the Cu layer 63 by electrolytic plating, the thickness of the Cu layer 63 varies depending on the wiring density and the wiring width. Such a problem occurs.

  That is, as shown in FIG. 14D, in the region 70 where the width of the wiring groove 60X is wide (that is, the wiring width is wide), the undulations corresponding to the wiring groove 60X are reflected in the Cu layer 63, and the Cu layer Since 63 is deposited thinner than the region 72 where no wiring exists, a recess 63A is formed on the surface of the Cu layer 63. On the other hand, in the region 71 in which a plurality of narrow wiring grooves 60X are formed, an overplate in which the Cu layer 63 is deposited thicker than the region 72 in which no wiring exists is generated, and a convex portion 63B is formed on the surface of the Cu layer 63. Is done. The occurrence of such an overplate is due to the adoption of a plating method called a bottom-up method or an overfilling method. That is, in the bottom-up method, Cu is preferentially deposited from the bottom surface of the groove or hole. However, if Cu precipitation is locally promoted in this way, the precipitation of the region is promoted even after the wiring groove is filled. Therefore, a Cu layer abnormally raised on the pattern (on the wiring groove) is formed.

  After the Cu layer 63 as described above is formed, as shown in FIG. 14E, the Cu layer 63 is polished by CMP, and the Cu layer 63 is removed until the surface of the insulating film 60 in the region 72 is exposed. Is done. However, if the height difference between the concave portion 63A and the convex portion 63B of the Cu layer 63 formed in each of the regions 70 and 71 is large, it cannot be completely planarized by CMP. As a result, on the upper surface of the Cu embedded wiring 64 in the region 71 where the convex portion 63B is formed, a residual Cu layer 64a that covers the region 71 widely (hereinafter, such Cu uncut residue is also referred to as “Cu residue”). May be left behind. Such a residual Cu layer 64 a causes a short circuit failure between the Cu embedded wirings 64 formed in the region 71.

  Note that by adding an appropriate additive to the electrolytic plating solution, it is possible to suppress the occurrence of overplate and form the Cu layer 63 formed in the regions 71 and 72 substantially flat. However, in this case as well, a step is generated between the Cu layer 63 formed in the regions 71 and 72 and the concave portion 63A. If this step is large, Cu residue is generated in the regions 71 and 72 having a low pattern density. Will do.

  Thus, the Cu residue is generated due to the density of the pattern density and the pattern width. Therefore, as a technique for suppressing the occurrence of such Cu residue, a technique has been proposed in which a dummy pattern is added to a region having a low pattern density so that the effective pattern density approaches uniformly (for example, Patent Document 1). reference).

JP 2006-108541 A

  However, it is impossible to determine whether or not the type (or layer) is likely to generate Cu residue only by verifying the density of the pattern density. For this reason, in the conventional method, when there is a region with a low pattern density, it is necessary to always add a dummy pattern, that is, it is necessary to always add a useless pattern as a circuit. In addition, a method of suppressing the occurrence of Cu residue by adjusting the polishing conditions in the CMP process is also conceivable, but in this case, the layer in which the Cu residue is generated is specified only after the production process in the production line is performed. The For this reason, in this method, when the occurrence of Cu residue cannot be suppressed only by adjusting the polishing conditions, there is a problem that a processing load is applied, for example, it is necessary to correct layout data and re-create a reticle (photomask). There is. For this reason, conventionally, there has been a demand for the creation of a new technology that can determine whether or not a product or layer is likely to generate Cu residue from layout data.

  According to an aspect of the present invention, there is provided an uneven distribution rate calculation method for calculating an uneven distribution rate of a pattern density based on layout data of a pattern formed on a semiconductor device, wherein the step executed by the computer includes a verification layer Calculating the pattern density for each area of a predetermined size, extracting an error area where the density difference of the pattern density between adjacent areas is at least a first reference value, and the total area of the error area Calculating, and comparing the total area with a second reference value.

  According to one aspect of the present invention, it is possible to determine whether or not a product or layer is likely to generate Cu residue from layout data.

The schematic block diagram of a wiring design apparatus. 6 is a flowchart showing a method for manufacturing a semiconductor device. The flowchart which shows the calculation method of the uneven distribution rate of pattern density. (A), (b) is explanatory drawing of the addition process of a minus shift. The top view for demonstrating blocking of a verification layer. Explanatory drawing of a calculation process of pattern density. Explanatory drawing of a calculation process of pattern density. (A)-(h) is explanatory drawing which shows a density map. (A), (b) is explanatory drawing of the addition process of a plus shift. (A)-(d) is explanatory drawing of the addition process of a plus shift. Explanatory drawing of a density difference check process. (A), (b) is explanatory drawing of a density difference check process. (A)-(c) is explanatory drawing of a CMP process. (A)-(e) Sectional drawing which shows Cu wiring formation process by the damascene method. The top view which shows the generation | occurrence | production location of Cu residue.

Hereinafter, an embodiment will be described with reference to FIGS.
As shown in FIG. 1, a design device (computer) 10 for generating layout data of a pattern formed on a semiconductor device is, for example, a general design support device (Computer Aided Design: CAD). The design device 10 includes a central processing unit (CPU) 11, a memory 12, a storage device 13, a display device 14, an input device 15, and a drive device 16. These devices 11, 13, 14, 15 and 16 and the memory 12 are connected to each other via a bus 17.

  The CPU 11 executes a program using the memory 12 and realizes necessary processes such as layout design of the semiconductor device and calculation of the uneven distribution rate of the pattern density. The program is for causing the CPU 11 to function as various means as a design device that generates layout data of a semiconductor device. The program is for causing the CPU 11 to function as various means as a calculation device for calculating the uneven distribution rate of the pattern density. The memory 12 stores programs and data necessary for providing various processes. The memory 12 usually includes a cache memory, a system memory, a display memory, and the like.

  The display device 14 is used for displaying a layout display, a parameter input screen, and the like. As the display device 14, for example, a CRT, LCD, PDP or the like is used. The input device 15 is used for inputting requests, instructions, patterns, and parameters from the user. As the input device 15, for example, a keyboard and a mouse device are used.

  The computer 10 causes the display device 14 to display a pattern (figure) formed on the semiconductor device based on the layout data. Then, the computer 10 adds and deletes the pattern on the display device 14 according to the signal from the input device 15 operated by the user, and adds and deletes the pattern data with respect to the layout data.

  The storage device 13 usually includes a magnetic disk device, an optical disk device, a magneto-optical disk device, and the like. The storage device 13 stores program data and files for generating layout data of a semiconductor device (semiconductor integrated circuit device). In response to an instruction from the input device 15, the CPU 11 transfers a program and data to the memory 12 and executes it.

  Program data executed by the CPU 11 is provided on the recording medium 18. The drive device 16 drives the recording medium 18 and accesses the stored contents. The CPU 11 reads program data from the recording medium 18 via the drive device 16 and installs it in the storage device 13.

  The recording medium 18 is an arbitrary computer-readable recording medium such as a magnetic tape (MT), a memory card, a flexible disk, an optical disk (CD-ROM, DVD-ROM, etc.), a magneto-optical disk (MO, MD, etc.). Can be used. The program and data described above can be stored in the recording medium 18 and loaded into the memory 12 for use as necessary.

  The recording medium 18 includes a medium or a disk device that records program data uploaded or downloaded through a communication medium. Furthermore, not only a recording medium that records a program that can be directly executed by a computer, but also a recording medium that records a program that can be executed once installed on another recording medium (such as a hard disk), or an encrypted program In addition, a recording medium on which a compressed program is recorded is also included.

  Here, the part and layer (layer) where Cu residue is likely to occur are considered. As described above, Cu residue is likely to be generated in a region where a wiring density (pattern density) is low or a wiring (pattern) having a narrow width is densely formed. Specifically, as shown in FIG. 15, a plurality of chips 20 are formed in a matrix on a semiconductor substrate (wafer) W, and an area R <b> 11 in which an internal circuit of each chip 20 is formed or each chip 20. Cu residue is likely to occur in the region R12 where the scribe line is formed. Further, when viewed in units of layers, when there is a large degree of unevenness in pattern density, that is, when there is a wide range of areas where the pattern density difference between neighboring areas is large, Cu residue is generated in the areas R11 and R12. It has been clarified by the inventors' diligent research that it is easy. Therefore, by quantifying the uneven distribution rate (degree of uneven distribution) of the pattern density, it is determined from the uneven distribution rate whether or not the product / layer is likely to generate Cu residue.

  Next, a method for generating layout data in consideration of the uneven distribution rate of pattern density and a method for manufacturing a semiconductor device using the uneven distribution rate and layout data of the pattern density will be described with reference to FIG.

  First, the CPU 11 creates a pattern shape of the entire chip 20 and generates layout data 21 (step S1). The layout data 21 is stored in the storage device 13 shown in FIG. The layout data 21 may be created by another layout design device or the like.

  Next, the CPU 11 calculates the uneven distribution rate of the pattern density of the entire layer to be verified based on the layout data 21 read from the storage device 13 (step S2).

  Subsequently, the CPU 11 compares the calculated pattern density uneven distribution rate with a reference value (step S3), and determines whether the verification layer is a layer in which Cu residue is likely to occur based on the comparison result. . Then, the CPU 11 determines whether or not the pattern needs to be corrected based on the comparison result between the uneven distribution rate and the reference value (step S4). If it is determined that the pattern needs to be corrected, the process returns to step S1, and the CPU 11 performs the pattern editing process to update the layout data 21. In this case, the CPU 11 updates the layout data 21 by adding a dummy pattern or the like to an area where the pattern density is low, for example.

  On the other hand, if it is determined in step S4 that no pattern correction is necessary, the layout is confirmed, and the CPU 11 determines the CMP recipe, that is, the CMP process (chemical process) according to the comparison result between the uneven distribution rate and the reference value. Polishing conditions in the mechanical polishing step) are set (step S5). That is, the CPU 11 changes the CMP recipe depending on whether or not the target layer to be subjected to the CMP process is a layer where Cu residue is likely to be generated, and sets an optimal CMP recipe for the target layer. Note that, for example, if it is not possible to avoid the occurrence of Cu residue even after adjusting the CMP recipe, it is determined in step S4 that the pattern needs to be corrected.

  Next, the CPU 11 generates a reticle (photomask) based on the layout data 21 (step S6). Then, using the reticle, a semiconductor device manufacturing process is performed on the manufacturing line (step S7). This manufacturing process includes a CMP process performed based on the CMP recipe set in step S5.

Next, a method for calculating the uneven distribution rate of the pattern density will be described in detail with reference to FIGS.
As shown in FIG. 3, first, the CPU 11 reads the layout data 21 from the storage device 13 (see FIG. 1), and performs the verification layer (for example, an arbitrary wiring layer) pattern read from the layout data 21. A minus shift is added by a predetermined amount (for example, 0.5 μm) to narrow all the patterns in the verification layer (step S11). By this processing, a pattern with a narrow wiring width (for example, a pattern such as the Cu embedded wiring 64 formed in the region 71 of FIG. 14E) disappears. Then, as shown in FIGS. 4 (a) and 4 (b), the pattern density is greatly reduced in a dense region of a pattern having a narrow wiring width (for example, see regions R1 and R2 in FIG. 4). In a region where a pattern with a wide wiring width exists (see, for example, the region R3 in FIG. 4), the variation in pattern density is small, and the pattern density hardly changes. In FIG. 4, the darkness of the dots in each of the regions R1 to R3 indicates the height of the pattern density in that region. By such a minus shift process, as shown in FIG. 4, the density of the pattern density between the regions R1, R2 and the region R3, specifically, the regions R1, R2 where the Cu residue can be generated and the pattern density are reduced. The boundary (pattern density difference) with the high region R3 is emphasized. That is, the minus shift amount in this process is set in advance by simulation or the like, and specifically, is set to an amount that can emphasize the boundary between a region where Cu residue can be generated and its neighboring region. The layout data after the minus shift process is stored in the storage device 13 (see FIG. 1) separately from the layout data 21.

  Next, as shown in FIG. 5, the CPU 11 blocks the verification layer into verification blocks B1 having a predetermined size (step S12 in FIG. 3). Here, the verification block B1 is set to have a size including 2 × 2 chips 20. By forming a block with such a size, it is possible to verify the pattern density of the region between the chips 20 where Cu residue can be generated, and calculate the uneven distribution rate of the pattern density in consideration of the pattern density of the region. be able to.

  Subsequently, the CPU 11 calculates a pattern density for each verification block B1 in the verification layer based on the layout data after the minus shift process (step S13). Specifically, each verification block B1 is divided by a 2 mm square verification area A1 shown in FIG. 6, and the pattern density (pattern occupancy) in the verification area A1 is calculated. Here, the pattern density (pattern occupancy) is a ratio of the total value of the areas of the patterns in the verification area A1 to the area of the verification area A1. Next, the CPU 11 moves the verification area A1 in the X-axis direction or the Y-axis direction by the verification step value V1 (for example, 0.5 mm), and calculates the pattern density in the verification area A1 at the movement destination. Such movement of the verification area A1 and calculation of the pattern density are repeatedly executed in the verification block B1. Then, the CPU 11 creates a density table 22 as shown in FIG. 7 based on the pattern density calculated for each movement of the verification area A1. In the density table 22 of FIG. 7, an example of the numerical value of the pattern density calculated for each movement of the verification area A1 is in each step section D1 whose one side is the verification step value V1 (here, 0.5 mm). It is shown. The density table 22 is stored in the storage device 13 shown in FIG.

  Next, the CPU 11 classifies the pattern density in the density table 22 read from the storage device 13 into predetermined density ranges, and creates a plurality of density maps MAP0 to MAP7 as shown in FIG. 8 (FIG. 3). Step S14). Specifically, the CPU 11 classifies the pattern density in the density table 22 into eight density ranges, and creates eight density maps MAP0 to MAP7 corresponding to the respective density ranges.

(Density map MAP0)
As shown in FIGS. 7 and 8A, the density map MAP0 extracts a step section D1 whose pattern density is a density range of 0% or more and less than 10%, and the extracted step section D1 (FIG. 8A). )) Is mapped onto the map MAP0. As a result, a map pattern MP0 corresponding to the distribution (positional information) of the step section D1 in which the pattern density is a density range of 0% or more and less than 10% is formed in the density map MAP0.

(Density map MAP1)
As shown in FIGS. 7 and 8B, the density map MAP1 extracts a step section D1 whose pattern density is a density range of 10% or more and less than 20%, and extracts the extracted step section D1 (FIG. 8B). )) Is mapped onto the map MAP1. As a result, a map pattern MP1 corresponding to the distribution of the step section D1 having a pattern density of 10% or more and less than 20% is formed in the density map MAP1.

(Density map MAP2)
As shown in FIG. 7 and FIG. 8C, the density map MAP2 extracts a step section D1 whose pattern density is a density range of 20% or more and less than 30%, and extracts the extracted step section D1 (FIG. 8C). )) Is mapped on the map MAP2. As a result, a map pattern MP2 corresponding to the distribution of the step section D1 whose pattern density is a density range of 20% or more and less than 30% is formed in the density map MAP2.

(Density map MAP3)
As shown in FIGS. 7 and 8D, the density map MAP3 extracts a step section D1 whose pattern density is a density range of 30% to less than 40%, and extracts the extracted step section D1 (FIG. 8D). )) Is generated on the map MAP3. As a result, a map pattern MP3 corresponding to the distribution of the step section D1 whose pattern density is in the density range of 30% or more and less than 40% is formed in the density map MAP3.

(Density map MAP4)
As shown in FIGS. 7 and 8E, the density map MAP4 extracts the step section D1 whose pattern density is a density range of 40% or more and less than 50%, and extracts the extracted step section D1 (FIG. 8 (e)). ) Is mapped on the map MAP4. As a result, a map pattern MP4 corresponding to the distribution of the step section D1 whose pattern density is in the density range of 40% or more and less than 50% is formed in the density map MAP4.

(Density map MAP5)
As shown in FIGS. 7 and 8 (f), the density map MAP5 extracts a step section D1 in which the pattern density is a density range of 50% or more and less than 60%, and the extracted step section D1 (FIG. 8 (f) )) Is mapped onto the map MAP5. As a result, a map pattern MP5 corresponding to the distribution of the step section D1 in which the pattern density is a density range of 50% or more and less than 60% is formed in the density map MAP5.

(Density map MAP6)
As shown in FIGS. 7 and 8G, the density map MAP6 extracts a step section D1 whose pattern density is a density range of 60% or more and less than 70%, and extracts the extracted step section D1 (FIG. 8 (g) )) Is mapped onto the map MAP6. As a result, a map pattern MP6 corresponding to the distribution of the step section D1 whose pattern density is a density range of 60% or more and less than 70% is formed in the density map MAP6.

(Density map MAP7)
As shown in FIGS. 7 and 8 (h), the density map MAP7 extracts a step section D1 whose pattern density is a density range of 70% or more and less than 80%, and the extracted step section D1 (FIG. 8 (h) )) Is mapped on the map MAP7. Thereby, the density map MAP7 forms a map pattern MP7 corresponding to the distribution of the step section D1 whose pattern density is a density range of 70% or more and less than 80%.

The density maps MAP0 to MAP7 created in this way are stored, for example, in the storage device 13 shown in FIG.
Next, as shown in FIG. 3, the CPU 11 adds a plus shift by a predetermined amount (here, 1.5 μm) to the eight density maps MAP0 to MAP7 (specifically, the map patterns MP0 to MP7). The map patterns MP0 to MP7 are fattened (step S15). Specifically, as shown in FIG. 9, the unit map pattern MU corresponding to one step section D1 (see FIG. 9A), that is, the four side surfaces of the 0.5 mm square unit map pattern MU is 1.5 mm. Thicken one by one (see hatched area in FIG. 9B). As a result, the unit map pattern MU spreads over the area of 2 mm around the unit map pattern MU, and verification of the uneven distribution rate of the pattern density described below is performed in the area of the circumference 2 mm. In other words, the plus shift amount (1.5 mm) is an amount set to expand the unit map pattern MU to a peripheral region where the value of the pattern density of the unit map pattern MU affects. This positive shift amount is set in advance by simulation or the like, and specifically, adjusted so that a layer (product type) in which Cu residue is generated can be highlighted. Here, in step S13, since the pattern density calculated in the verification area A1 of 2 mm square is the pattern density of the step section D1 (unit map pattern MU) of 0.5 mm square, the value of this pattern density is The plus shift amount is set to 1.5 mm in order to expand the affected area to a 2 mm area around the unit map pattern MU.

  FIG. 10B shows the map pattern MP0a after adding a 1.5 mm plus shift to the map pattern MP0 (see FIG. 10A) of the density map MAP0 created in step S14. Further, FIG. 10D shows a map pattern MP3a after adding a 1.5 mm plus shift to the map pattern MP3 (see FIG. 10C) of the density map MAP3 created in step S14. In this step S15, although not shown, plus shift is also added to the map patterns MP2, MP4 to MP7 of the other density maps MAP2, MAP4 to MAP7. After such a plus shift is added, the density maps MAP0 to MAP7 stored in the storage device 13 are updated.

  Next, as shown in FIG. 3, the CPU 11 has a density difference in pattern density in the neighboring area equal to or greater than the first reference value (here, 30%) based on the density maps MAP0 to MAP7 after the plus shift. An area is extracted (step S16). Specifically, as shown in FIG. 11, among the density maps MAP0 to MAP7, density maps having a density difference of 30% or more are overlapped (see black circles), and an area where the map patterns of both density maps overlap is extracted. To do. More specifically, for example, density maps MAP0 and MAP3 after the plus shift shown in FIG. 12A are overlapped, and the map pattern MP0a and the map pattern MP3a after the plus shift overlap as shown in FIG. 12B. An area (area within the bold frame) is extracted as an error area EA. Similarly, the following density maps shown by the black circles in FIG. 11 are combined, and the overlapping area of the map pattern after the plus shift formed in both density maps is extracted as an error area EA.

Density map MAP0 and density map MAP4
・ Density map MAP0 and density map MAP5
Density map MAP0 and density map MAP6
Density map MAP0 and density map MAP7
Density map MAP1 and density map MAP4
Density map MAP1 and density map MAP5
Density map MAP1 and density map MAP6
Density map MAP1 and density map MAP7
Density map MAP2 and density map MAP5
Density map MAP2 and density map MAP6
Density map MAP2 and density map MAP7
Density map MAP3 and density map MAP6
Density map MAP3 and density map MAP7
Density map MAP4 and density map MAP7
As a result, a region having a large density difference in pattern density between neighboring regions, which serves as an index for evaluating the likelihood of occurrence of Cu residue, can be extracted as the error region EA. The first reference value is set in advance by simulation or the like, and specifically adjusted so as to highlight a layer (product type) in which Cu residue is generated.

Next, as shown in FIG. 3, the CPU 11 calculates the area of each error area EA extracted by each combination described above, and sums the areas of all the error areas EA to obtain the total area of the error area EA. Calculate (step S17). The error area EA extracted by the combination of the density maps MAP0 and MAP3 shown in FIG. 12 has 55 unit map patterns MU of 0.5 mm square, so that the area of the error area EA is 13.2. 75 mm ² (= 0.5 × 0.5 × 55).

Subsequently, as illustrated in FIG. 3, the CPU 11 compares the calculated total area of the error area EA with a second reference value (for example, 320 mm ² ) (step S18). In this step S18, when the total area of the error area EA is equal to or larger than the second reference value, the CPU 11 determines that the uneven distribution rate of the pattern density of the verification layer is “large” (step S19). That is, in this case, it can be determined that there is a region where the pattern density difference between the neighboring regions is large in a wide range and Cu is likely to be generated. The determination result indicating the uneven distribution rate of the pattern density at this time is used for determining whether or not the pattern needs to be corrected in step S4 described above and for setting the CMP recipe in step S5. On the other hand, when the total area of the error area EA is less than the second reference value, the CPU 11 determines that the uneven distribution rate of the pattern density of the verification layer is “small” (step S20). That is, in this case, it can be determined that the layer has a small pattern density difference between neighboring regions and has a low probability of occurrence of Cu residue. The second reference value is set in advance by simulation or the like, and is specifically set to a value that can determine whether or not the layer is likely to generate Cu residue.

  Through the processing described above, it is possible to determine the size of the uneven distribution rate of the pattern density of the verification layer based on the layout data 21, and from the layout data 21 whether the verification layer is a layer in which Cu residue is likely to occur. Can be determined. In addition, since the position of the low pattern density region can be detected from the density table 22 created in step S13, if the verification layer is a layer where Cu residue is likely to occur, the location where Cu residue is likely to occur is specified. be able to. Furthermore, since the region where the patterns with narrow wiring widths are densely replaced by the region having a low pattern density by the minus shift process in step S11, the region having a low pattern density is detected as a portion where Cu residue is likely to occur. As a result, a region where patterns with narrow wiring widths are dense can be specified as a portion where Cu residue is likely to occur.

Next, an example of a CMP recipe setting method in step S5 shown in FIG. 2 will be described.
First, an outline of the CMP process performed in step S7 shown in FIG. 2 and a polishing apparatus used in the CMP process will be described.

  As shown in FIG. 13A, in the CMP process, a predetermined polishing process is performed in order on the three polishing apparatuses 30, 40, and 50 on the wafer to be processed. 14 (d) and 14 (e) will be described in detail. In the first polishing apparatus 30, unnecessary portions of the Cu layer 63 deposited so as to cover the wiring trench 60 </ b> X formed in the insulating film 60 are removed. A first polishing step for roughing is performed. In the second polishing apparatus 40, unnecessary portions of the Cu layer 63 after the first polishing step are further polished, end point detection (EPD) of Cu polishing is performed, and then over polishing (excess polishing) as a countermeasure against Cu residue. A second polishing step is performed. In the third polishing apparatus 50, barrier metal polishing for polishing the barrier metal 61 formed on the surface of the insulating film 60 is performed. By such a CMP process, a Cu embedded wiring 64 is formed in the wiring groove 60X formed in the insulating film 60.

  As shown in FIG. 13B, the first polishing apparatus 30 fixes the wafer W so that the polishing pad 31 is attached to the surface and the platen 32 is rotatable, and the surface of the wafer W is in contact with the polishing pad 31. It has a polishing head 33 and a dressing part 34 that removes shavings generated during polishing from the polishing pad 31. A polishing liquid (slurry) 36 is supplied from the nozzle 35 to the center of the platen 32. Further, the polishing head 33 and the dressing portion 34 are rotatable and are movable in the radial direction of the platen 32.

  In the first polishing apparatus 30, a polishing process is performed for the purpose of flattening the unevenness of Cu on the surface of the wafer W. For this reason, the polishing pad 31 of the first polishing apparatus 30 is made of a material having a high leveling ability (for example, a urethane resin layer), and the rigidity of the surface of the polishing pad 31 is increased.

  The first polishing step in the first polishing apparatus 30 includes, for example, the rotation speed of the platen 32 is 64 rpm, the rotation speed of the polishing head 33 is 58 rpm, the supply amount of the polishing liquid 36 is 300 ml / min, and the wafer W is polished to the polishing pad 31. The pressure is pressed under a polishing condition of 3.5 psi.

  As shown in FIG. 13C, the second polishing apparatus 40 fixes the wafer W so that the polishing pad 41 is attached to the surface and the platen 42 is rotatable, and the surface of the wafer W is in contact with the polishing pad 41. It has a polishing head 43 and a dressing portion 44 for removing shavings generated during polishing from the polishing pad 41. A polishing liquid (slurry) 46 is supplied from the nozzle 45 to the center of the platen 42. Further, the polishing head 43 and the dressing portion 44 are rotatable and movable in the radial direction of the platen 42.

  In the second polishing apparatus 40, a polishing process is performed for the purpose of completely removing unnecessary Cu (Cu clear). For this reason, the polishing pad 41 of the second polishing apparatus 40 has a first resin layer 41a having a high step following ability to follow the unevenness on the surface of the wafer W, and a second resin layer 41b in contact with the wafer W. is doing. The material of the first resin layer 41a is preferably a material having a high cushioning property. For example, an elastic resin can be used. Moreover, as a material of the 2nd resin layer 41b, a urethane resin layer etc. can be used, for example.

  In the second polishing step in the second polishing apparatus 40, for example, the rotation speed of the platen 42 is 64 rpm, the rotation speed of the polishing head 43 is 58 rpm, the supply amount of the polishing liquid 46 is 300 ml / min, and the wafer W is polished to the polishing pad 41. The pressure is pressed under a polishing condition of 3.5 psi.

  In the polishing process in the third polishing apparatus 50, the barrier metal exposed by the polishing process by the second polishing apparatus 40 is removed, and a Cu embedded wiring by a damascene method is formed. After that, the polishing residue is removed with, for example, a cleaning liquid containing a surfactant, and the CMP process is completed by re-cleaning with pure water.

Next, a CMP recipe setting method based on the uneven distribution rate of the pattern density will be described.
When the total area of the error area EA is equal to or larger than the second reference value, that is, when it is determined that the uneven distribution rate of the pattern density is large, the polishing amount in the first polishing step by the first polishing apparatus 30 is It sets so that it may increase rather than the grinding | polishing amount when it determines with the uneven distribution rate being small. For example, when the polishing amount in the first polishing step when the uneven distribution rate is small is 1000 μm, when it is determined that the uneven distribution rate is large, the polishing amount is set to 1100 μm which is 1.1 times the polishing amount. . This is because, when it is determined that the uneven distribution rate is large, that is, when it is determined that Cu residue is likely to be generated, the difference in level of the Cu unevenness is considered to be large. The amount of polishing in the first polishing step by the target first polishing apparatus 30 is set to increase. The amount of polishing can be adjusted by, for example, the polishing time.

  When it is determined that the uneven distribution rate of the pattern density is large, the overpolishing amount in the second polishing step by the second polishing apparatus 40 is larger than the overpolishing amount when the uneven distribution rate is determined to be small. Also set to increase. Specifically, first, when it is determined that the uneven distribution rate is small, after the end point of Cu polishing is detected in the second polishing step by the second polishing apparatus 40, overpolishing with a polishing amount of 400 nm is performed. Is done. On the other hand, when it is determined that the uneven distribution rate is large, in the second polishing step by the second polishing apparatus 40, after the end point of Cu polishing is detected, overpolishing with a polishing amount of 400 nm is performed. Then, washing with water is performed to remove additives that hinder polishing, and overpolishing with a polishing amount of 400 nm is performed again. That is, when it is determined that the uneven distribution rate is high, over-polishing that is twice as much as when the uneven distribution rate is small is performed. Unnecessary Cu is removed by such over-polishing, and the generation of Cu residue is suitably suppressed.

  As described above, when it is determined from the uneven distribution rate of the pattern density that the Cu residue is likely to be generated, the amount of polishing in the first polishing apparatus 30 (first polishing step) is increased, and the first The CMP recipe is set so as to increase the amount of overpolishing in the second polishing apparatus 40 (second polishing step). Then, in step S7 shown in FIG. 2, a CMP process is performed based on this CMP recipe. As a result, the CMP process in which the CMP strength is greatly adjusted is performed on the layer where Cu residue is likely to be generated, so that it is possible to suitably suppress the occurrence of Cu residue in the layer.

The map patterns MP0 to MP7 are examples of density maps, the wiring groove 60X is an example of a recess, and the Cu layer 63 is an example of a conductive layer.
According to this embodiment described above, the following effects can be obtained.

  (1) An error area EA in which the pattern density difference between neighboring areas is equal to or greater than the first reference value (30%) is extracted, and the total area of the error area EA is calculated as the uneven distribution rate of the pattern density. Further, the magnitude of the uneven distribution rate of the pattern density is determined by comparing the total area of the error area EA with the second reference value. Thereby, it can be determined from the magnitude of the uneven distribution rate of the pattern density determined in this way whether or not the verification layer is a layer where Cu residue is likely to occur. That is, a verification layer in which Cu residue is likely to be generated can be specified from the layout data, and as a result, a variety in which Cu residue is likely to be generated can be specified. Therefore, when it is determined that the layer is likely to generate Cu residue, the layout data can be corrected before the reticle is created, or the optimum CMP conditions can be set before the CMP process is performed. . Further, when it is determined that the layer is hard to generate Cu residue, the layout can be determined without adding a dummy pattern or the like unnecessarily.

  (2) The CMP recipe is set according to the comparison result between the total area of the error area EA and the second reference value. That is, the CMP recipe is changed depending on whether or not the target layer subjected to the CMP process is a layer where Cu residue is likely to be generated, and an optimum CMP recipe is set for the target layer. By performing the CMP process based on the CMP recipe set in this way, it is possible to suitably suppress the occurrence of Cu residue.

  (3) A density map of a combination in which the pattern density difference is greater than or equal to the first reference value, specifically, a density map after applying a predetermined amount of plus shift is superimposed, so that map patterns MP0 to MP7 after plus shift are obtained. The overlapping area is extracted as the error area EA. Thereby, not only the pattern density difference between the adjacent areas of the step section D1 (unit map pattern MU) but also the pattern density in consideration of the pattern density difference between the neighboring areas (here, the surrounding area of 2 mm) of the step section D1. Can be calculated.

  (4) A predetermined amount of minus shift is added to all patterns in the verification layer read from the layout data 21. As a result, the pattern with a narrow wiring width disappears, so that the pattern density of a region (for example, the region 71 in FIG. 14) where such patterns with a narrow wiring width are densely reduced. By the way, as described above, such a region is a region where overplate is likely to occur and unevenness causing the generation of Cu residue may occur, but the pattern density is so low because the patterns are densely packed. Absent. For this reason, when a minus shift is not applied, for example, there is a large density difference between a dense region of a pattern having a narrow wiring width and a region having a high pattern density in which a pattern having a wide wiring width is formed. Does not occur. Therefore, in this case, in calculating the uneven distribution rate of the pattern density, a region in which patterns having a narrow wiring width, which can generate Cu residue, is not considered so much.

  On the other hand, in the present embodiment, the dense area of the narrow wiring pattern is replaced with an area having a low pattern density by the minus shift process. For this reason, a large density difference is generated between the region thus replaced and a region having a high pattern density, and an error region EA is generated. In other words, in this case, the uneven distribution rate of the pattern density can be calculated in consideration of a region where patterns with narrow wiring width where a Cu residue can be generated are concentrated. Therefore, based on the uneven distribution rate of the pattern density, it can be accurately determined whether or not the verification layer is a layer in which Cu residue is likely to occur.

(Other embodiments)
In addition, the said embodiment can also be implemented in the following aspects which changed this suitably.
In the above embodiment, the second reference value is a single value, but the second reference value may be set to a plurality of values. In this case, a CMP recipe may be set for each section of the second reference value to which the total area of the error area EA belongs. According to this, a CMP recipe can be set finely according to the size of the uneven distribution rate of the pattern density, and a CMP recipe more suitable for the uneven distribution rate of the pattern density can be set.

-You may abbreviate | omit the process of step S11 (refer FIG. 3) in the said embodiment.
In the above embodiment, the block B1 has a size including 2 × 2 chips 20. However, the size is particularly limited as long as the pattern density of the area between the chips 20 can be calculated. Not.

  Further, for example, the entire verification layer may be set as one verification region. In this case, the verification layer blocking process in step S12 (see FIG. 3) may be omitted.

In the above embodiment, the size of the verification area A1 and the value of the verification step value V1 are arbitrarily set values and are not particularly limited.
In the above embodiment, the density map of the combination in which the pattern density difference is equal to or greater than the first reference value, specifically, the density map after adding a predetermined amount of plus shift is superimposed, and the map pattern after plus shift is The overlapping area is extracted as the error area EA. Not limited to this, for example, a density map of a combination in which the pattern density difference is equal to or greater than the first reference value, specifically, a density map to which no plus shift is added is superimposed, and an area where both map patterns are adjacent is an error area. You may make it extract as EA. In this case, the process of step S15 may be omitted. As described above, the method is not particularly limited as long as it is possible to extract a region in which at least the pattern density difference between adjacent regions is equal to or greater than the first reference value.

  In the above embodiment, the CPU 11 of the design device 10 that generates the layout data 21 calculates the pattern density uneven distribution rate, but a computer different from the design device 10 calculates the pattern density uneven distribution rate. May be. In this case, the other computer may have the same configuration as that shown in FIG.

DESCRIPTION OF SYMBOLS 10 Design apparatus 11 Central processing unit 13 Memory | storage device 20 Chip 21 Layout data MAP0-MAP7 Density map MP0-MP7 Map pattern 60 Insulating film 60X Wiring groove 63 Cu layer 64 Cu embedded wiring

Claims (7)

An uneven distribution ratio calculation method for calculating an uneven distribution ratio of a pattern density based on layout data of a pattern formed on a semiconductor device by a computer,
The steps executed by the computer include
Calculating the pattern density for each area of a predetermined size in the verification layer;
Extracting an error region where the density difference of the pattern density between at least adjacent regions is equal to or greater than a first reference value;
Calculating the total area of the error region;
Comparing the total area with a second reference value;
The uneven distribution rate calculation method characterized by having. Extracting the error region comprises:
Separating the pattern density calculated for each area into a plurality of density ranges, and generating a plurality of density maps indicating a distribution of pattern densities belonging to each density range;
Adding a predetermined amount of positive shift to each density map;
A step of superimposing the density maps after the plus shift in a combination in which the density difference of the pattern density is equal to or greater than the first reference value, and extracting an overlapping area in both density maps as the error area;
The uneven distribution rate calculation method according to claim 1, wherein: The step of calculating the pattern density includes:
Blocking the verification layer into blocks containing at least 2 × 2 chips;
Moving the area of the predetermined size in the block for each predetermined step, and calculating the pattern density in the area for each movement;
The uneven distribution rate calculation method according to claim 1, wherein: Before calculating the pattern density,
The uneven distribution rate calculation method according to claim 1, further comprising a step of adding a predetermined amount of minus shift to all patterns in the verification layer. Based on the comparison result in the uneven distribution rate calculation method according to any one of claims 1 to 4, a step of setting polishing conditions in a chemical mechanical polishing step;
Performing the chemical mechanical polishing step under the set polishing conditions;
A method for manufacturing a semiconductor device, comprising: The chemical mechanical polishing step includes a first polishing step for rough cutting an unnecessary portion of the conductive layer deposited so as to cover a recess provided in the insulating film, and an unnecessary portion of the conductive layer after the first polishing step. A second polishing step of performing excess polishing after polishing and detecting the end point,
In the step of setting the polishing conditions, when it is determined that the uneven distribution rate is large according to the comparison result, the polishing amount in the first polishing step is increased and the polishing step in the second polishing step is performed. 6. The method of manufacturing a semiconductor device according to claim 5, wherein the polishing conditions are set so as to increase a polishing amount of excessive polishing. A program executed by a computer that calculates an uneven distribution rate of pattern density based on layout data of a pattern formed in a semiconductor device,
Calculating a pattern density for each area of a predetermined size in the verification layer;
Extracting an error region where the density difference of the pattern density between at least adjacent regions is equal to or greater than a first reference value;
Calculating the total area of the error region;
Comparing the total area with a second reference value;
The program characterized by having.

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