JP2008047574A - Manufacturing method and system of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing technique of semiconductor devices capable of setting a residual level difference in CMP polishing to not more than a prescribed value, improving the manufacturing throughput of a film deposition process and a CMP process, and suppressing costs. <P>SOLUTION: The CMP process and the film deposition process when manufacturing a semiconductor predicts the amount of polishing, where the residual level difference generated after CMP polishing becomes not more than a prescribed value, by an information processing unit, and deposits the same thickness film as or a thicker film than the amount of polishing in advance before polishing by a CMP apparatus. Thus the thickness is minimized in the film deposited by the film deposition process, the amount of polishing is minimized at a stage for performing the CMP polishing of the deposited film, and throughput and suppressing costs are improved in manufacture. The occurrence of fault due to the occurrence of excessive polishing can also be inhibited in advance. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a manufacturing technique of a semiconductor device, and more particularly to a technique effective when applied to a CMP (Chemical Mechanical Polishing) process and a film deposition process in semiconductor manufacturing.

  For example, regarding the CMP process and the film deposition process in semiconductor manufacturing, the techniques listed below can be cited.

  (1) Patent Document 1 (Japanese Patent Laid-Open No. 8-69999) describes a method for defining the thickness of a deposited film.

(2) Patent Document 2 (Japanese Patent Laid-Open No. 2004-191266) describes a method of performing stable film thickness management by combining a film forming apparatus and a measuring apparatus, and feeding the result to a CMP process. Has been.
JP-A-8-69999 JP 2004-191266 A

  By the way, in the above-described technique, (1) the technique of Patent Document 1 merely defines the thickness of a film to be deposited. In addition, (2) The technique of Patent Document 2 is mainly intended to control the film deposition apparatus. Therefore, neither of the techniques of Patent Documents 1 and 2 predicts a residual step, and does not change the thickness of the deposited film according to the residual step.

  An object of the present invention is to predict the residual step and deposit a film having an optimal thickness based on the prediction, thereby improving the film deposition process and the manufacturing throughput of the CMP process while keeping the residual step in the CMP polishing below a specified value. An object of the present invention is to provide a manufacturing technique of a semiconductor device that can realize cost reduction.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  In order to achieve the above object, the present invention predicts, with an information processing device, a polishing amount at which a residual step generated after CMP polishing is within a specified value in a CMP process and a film deposition process in semiconductor manufacturing, and the polishing amount and Provided is a method for manufacturing a semiconductor device, wherein the same or thicker film is deposited in advance before polishing with a CMP apparatus. Thereby, the thickness of the film deposited in the film deposition process can be suppressed to a minimum, and the deposited amount can be minimized even in the CMP polishing of the deposited film. In addition, it is possible to prevent the occurrence of defects due to the occurrence of excessive polishing. That is, excessive polishing can be suppressed and occurrence of defects can be suppressed. Further, it is not necessary to deposit an excessively thick film by the film deposition apparatus, and the manufacturing turnaround time can be improved.

  Preferably, in the above, a method for manufacturing a semiconductor device is provided, wherein the thickness of the deposited film is 1 to 2 times the polishing amount at which the residual step is within a specified value. Thereby, excessive polishing can be suppressed and occurrence of defects can be suppressed. Further, it is not necessary to deposit an excessively thick film by the film deposition apparatus, and the manufacturing throughput can be improved.

  Preferably, in the above, a method for manufacturing a semiconductor device is provided in which the amount of residual step is obtained by simulation of a CMP process. As a result, it is possible to predict the amount of film deposition more precisely, and it is possible to prevent excessive polishing and prevent excessively thick film deposition.

  Preferably, in the above, the polishing characteristics of the CMP apparatus, particularly the pressure distribution applied to the polishing pad, the hardness of the polishing pad, the polishing speed, etc. are monitored on the production line by the process monitor apparatus, and the change in the residual step caused by the polishing characteristics of the CMP apparatus is observed. Provided is a method for manufacturing a semiconductor device, characterized in that a film having the same or thicker film thickness as the remaining step is deposited by controlling the film deposition apparatus in a process before polishing, that is, a film deposition process, predicted by an information processing apparatus. The As a result, the film deposition amount can be changed in accordance with process variations, and further improvement in turnaround time and suppression of a decrease in product yield due to process variations can be achieved.

  Preferably, the film described above is a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon oxide film containing carbon atoms, a metal containing tantalum, a metal containing copper, a metal containing tungsten, or a silicon oxide containing an organic substance. There is provided a method for manufacturing a semiconductor device comprising a film, phosphoborosilicate glass, phosphosilicate glass, or a combination thereof. As a result, the effects described above can be obtained for the film on the semiconductor device manufactured by various processes.

  Preferably, a process monitor device for monitoring the pressure of the polishing pad, the residual step or film thickness, and the polishing speed for receiving the control in the above, and receiving information from the process monitor device, processing this information, and after polishing There is provided a semiconductor device manufacturing system having an information processing device for calculating a residual level difference. As a result, it is possible to manufacture a semiconductor with high throughput and capable of suppressing a decrease in the yield rate of products due to process variations.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  According to the present invention, it is possible to realize an improvement in manufacturing throughput and cost reduction in a film deposition process and a CMP process while a residual level difference in CMP polishing is set to a predetermined value or less.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

  1 to 4, a method for manufacturing a semiconductor device will be described with reference to FIGS. 1 to 4, and a semiconductor device manufacturing system will be described with reference to FIGS.

(Method for manufacturing semiconductor device)
FIG. 1 is an explanatory diagram illustrating a cross-sectional shape of a semiconductor device. In FIG. 1, there are a region where the wiring 15 is disposed and a region where the wiring 15 is not disposed on the substrate. An oxide film for insulating the wirings is formed on the wirings 15. After the oxide film is formed, the oxide film on the wiring 15 is formed with a film thickness of Z1, and the cross-sectional shape of the oxide film surface is as shown by the line 11.

  At this time, the step formed between the upper portion of the wiring 15 and the portion without the wiring has a height of s1. Usually, the value of s1 is almost equal to the height of the wiring 15 and has a value of about 300 nm to 600 nm. If the upper lithography process is carried out while leaving such a large step left, if the step becomes larger than the depth of focus of the exposure apparatus, it becomes a cause of defects such as defective exposure and disconnection.

  Therefore, the step is reduced by the CMP process. In the CMP process, the oxide film is polished, whereby the step is reduced, the cross section of the surface of the oxide film is shaped as indicated by the line 12, and the maximum residual step is e1. Here, the maximum residual level difference described above is defined as the maximum residual level difference in a semiconductor device such as a semiconductor device chip (usually several mm square). In order to completely eliminate the step, theoretically infinite time is required. Therefore, the residual step e1 always occurs in an actual process.

  Therefore, when determining the polishing amount d1 of the CMP process, it is usual to use d1 having a sufficient size so that the maximum residual step e1 <the specified value (hereinafter referred to as e2). For this purpose, it is necessary to carry out test polishing, and it takes a lot of time to obtain the optimum d1, Z1 for all product types.

  Therefore, d1 and Z1 are usually determined using a test chip having a typical pattern arrangement. However, since the actual product has a pattern arrangement different from that of the test chip, in order to secure a sufficiently large d1 in any product type, even if it is over-spec, it is more than necessary. It is necessary to deposit the film d1.

  As described above, conventionally, Z1 and d1 having a sufficient size have been provided regardless of the product type using a test chip. It is considered that the overhead of the manufacturing time can be eliminated by changing such a conventional method so as to give optimum Z1 and d1 for each product type without using a test chip.

  Therefore, in the embodiment of the present invention, the polishing amount d2 that satisfies the maximum residual step e1 <the specified value e2 is determined using the CMP simulation method as shown in FIG. FIG. 2 is a graph showing a result of obtaining the maximum residual step (e1) with respect to the polishing amount (D) by simulation.

  Much research has been conducted on the CMP simulation technique so far. Smith, Simon J. et al. Fang, Duane S. Boning, Greg B.E. Shinn, and Jerry A. et al. Stefani, “A CMP Model Combining Density and Time Dependencies,” 1999 Chemical Mechanical Polish for ULSI Multilevel Interconnection Conference (CMP-MICbS). 1999. Etc. have been announced.

  In the CMP simulation method, the film thickness distribution in the chip can be calculated with respect to the polishing time t and the polishing amount D. The simulation is executed while changing the polishing time t, and the polishing time when the residual step in the chip becomes equal to or less than the standard value (e2) is t2, and the polishing amount is d2. This process will be described below with reference to FIG. FIG. 3 is a flowchart showing a CMP simulation process.

  First, design data of a semiconductor device is prepared. The design data includes the shapes of all patterns (STI (Shallow Trench Isolation) patterns, Cu wiring groove patterns, contact hole patterns, etc. in addition to normal Al wiring) that exist in semiconductor devices (usually several mm square) It is. Among these, only the pattern of the layer to be polished is selected and divided into meshes (S101).

  FIG. 4 is an explanatory diagram showing an example of this mesh division. The optimum mesh size varies depending on the target CMP process, but about 20 to 100 μm is appropriate for polishing an interlayer oxide film.

Next, pattern processing is performed on the obtained mesh division data (S102). The contents of this processing also differ depending on the target CMP process, but in the case of a conformal film such as an O ₃ -TEOS (Tetraheythyrhosilicate) film, a process for increasing the pattern size is added. The order of mesh division and pattern processing may be switched.

  Next, the pattern density is calculated for each mesh using the processed pattern (S103). The pattern density described above is a value obtained by (area occupied by processed pattern existing in the target mesh) / (area of the target mesh). The pattern density calculation is performed for all meshes existing on the semiconductor device.

  Next, the polishing rate is obtained using the value of the pattern density (S103). Many methods have been proposed so far for obtaining the polishing rate, and typical ones are also described in the above-mentioned documents. In order to obtain the polishing rate, parameters related to the polishing pressure, the polishing rate when a film having no pattern is polished (hereinafter referred to as the blank rate), the Young's modulus of the pad, and the like are required. The parameters described above need to be well tuned to reproduce the actual CMP polishing process.

  Next, the film thickness distribution in the semiconductor device at the polishing time t is determined using the polishing rate determined above (S104). This process corresponds to calculating the film thickness of all meshes dividing the semiconductor device. Since the distribution of the film thickness in the semiconductor device can be understood, naturally, by comparing the height of the mesh showing the highest film thickness and the mesh showing the lowest film thickness, The maximum residual step e1 can be obtained.

  Next, it is examined whether or not the maximum residual step e1 obtained above is within the standard value e2 (S105). At this time, if e1 <e2 is not satisfied, the polishing time is increased by Δt (S106), and the above-described calculation of the film thickness distribution is executed again. On the other hand, when e1 <e2 is satisfied, the polishing time at this time is obtained as the optimum polishing time t2. When t2 is obtained, the polishing amount is obtained at the same time, and the optimum polishing amount at this time is defined as d2.

  Although the optimum polishing amount d2 obtained as described above may be used as the optimum deposition amount Z2 as it is, there is a possibility that excessive polishing occurs due to lack of a margin. Therefore, in order to obtain a margin, it is preferable to set Z2 by multiplying d2 by a coefficient between 1 and 2. According to the study by the present inventors, an appropriate value of the coefficient is about 1.2.

  Film deposition is performed using the optimum deposition amount Z2 obtained as described above, and if the polishing amount is d2 in the polishing stage, a high throughput can be obtained and the standard value of polishing flatness can be satisfied. It becomes possible. In the present embodiment, since Z2 and d2 are different for each product type, calculation of Z2 and d2 is required for each product type.

(Semiconductor device manufacturing system)
FIG. 5 is an explanatory view showing a semiconductor device manufacturing system. 5 includes a film deposition apparatus 21, a CMP pretreatment apparatus 22, a CMP apparatus 23, a process monitor apparatus 231, an information processing apparatus 25, a data server 26, a film deposition control apparatus 211, and a CMP control apparatus 212. It is configured.

  In this configuration, in particular, the information processing apparatus 25 is composed of a computer, calculates a residual level difference that occurs after CMP polishing, and predicts an amount of polishing that the residual level level is within a specified value, and a residual level that occurs due to the polishing characteristics of the CMP apparatus. It has a function of predicting a change in level difference. Further, the process monitor device 231 has a function of monitoring the pressure distribution applied to the polishing pad, the hardness of the polishing pad, the polishing speed, the residual step or the film thickness in the production line.

  The operation of the semiconductor device manufacturing system shown in FIG. 5 will be described below. The values of the optimum deposition amount Z2 and the polishing amount d2 are preferably obtained in advance for each product type scheduled to be processed and registered in the data server 26 in a table format as shown in FIG. However, when the time until product introduction is extremely short, etc., Z2 and d2 may be obtained by the information processing device 25 using design data stored in the data server 26. The obtained Z2 and d2 are registered in the table of the data server 26.

  The semiconductor device to be processed is subjected to a film deposition process by the film deposition apparatus 21 according to the value of Z2 transferred from the data server 26 to the film deposition control apparatus 211. Next, a CMP pretreatment process is performed by the CMP pretreatment apparatus 22. Next, the value d2 of the data server 26 is transferred to the CMP control device 212, and the polishing amount in the CMP device 23 is accurately controlled to d2. The process monitor device 231 connected to the CMP device 23 has various monitoring functions. For example, the pressure distribution applied to the polishing pad, the hardness of the polishing pad, and the polishing rate can be measured in real time during polishing. The measurement result is transferred to the information processing apparatus 25 and used as a parameter for CMP simulation.

  Normally, in CMP, the characteristics of the polishing pad change as the number of polishing sheets increases, so the parameters change little by little each time one is polished. The information processing apparatus 25 performs the simulation again using the parameters changed as described above, and obtains new Z2 and d2. The film deposition control device 211 instructs the film deposition device 21 to perform film deposition by the new value of Z2 according to the obtained value of Z2. The semiconductor device deposited with the new value of Z2 is polished by the CMP apparatus 23 via the CMP pretreatment apparatus 22. At this time, polishing is performed in accordance with an instruction from the CMP control device 212 by the amount of d2 newly obtained as described above.

  If the above cycle is executed for all semiconductor devices, it is possible to maintain the optimum film thickness and polishing amount while following minute variations in the polishing process. It is possible to suppress the occurrence of a residual step exceeding the value.

(Modification of semiconductor device manufacturing system)
In the semiconductor device manufacturing system, when monitoring and feedback of Z2 and d2 are performed on all semiconductor devices, an amount of simulation exceeding the performance of the information processing device 25 may be required. In many cases, the variation of the CMP process is not so large that monitoring is required for all semiconductor devices.

  For this reason, in a modification of the semiconductor device manufacturing system, Z2 and d2 are reviewed only once for not all semiconductor devices but N (N is a positive integer) semiconductor devices to be processed. Is to do. The above N varies depending on the process, but according to the study by the present inventors, up to about 5 is considered to be within the allowable range.

  The same effect as that of the semiconductor device manufacturing system can be obtained by a modification of the semiconductor device manufacturing system.

(Film subject to CMP process)
Although the film to be subjected to the CMP process described above has been described as an oxide film, in this embodiment mode, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon oxide film containing carbon atoms, and tantalum are used. Even if it is a metal containing copper, a metal containing copper, a metal containing tungsten, a silicon oxide film containing an organic substance, phosphoborosilicate glass, phosphosilicate glass, or a combination thereof, the same effect can be applied. Obtainable.

(Effect of this embodiment)
In the present embodiment described above, the effects of the semiconductor device manufacturing method and the manufacturing system are summarized as follows.

  (1) Predicting a polishing amount in which a residual level difference generated after CMP polishing is within a specified value, and pre-depositing a film equal to or thicker than the polishing amount with a CMP apparatus, it is possible to suppress excessive polishing, The occurrence of defects can be suppressed. Further, it is not necessary to deposit an excessively thick film by the film deposition apparatus, and the manufacturing turnaround time can be improved.

  (2) By setting the thickness of the deposited film to a thickness of 1 to 2 times the polishing amount at which the residual level difference is within the specified value, excessive polishing can be suppressed and occurrence of defects can be suppressed. Further, it is not necessary to deposit an excessively thick film by the film deposition apparatus, and the manufacturing throughput can be improved.

  (3) By determining the amount of residual step by simulation of the CMP process, it is possible to predict the film deposition amount more precisely, and it is possible to prevent excessive polishing and suppress excessively thick film deposition.

  (4) The pressure distribution applied to the polishing pad, the hardness of the polishing pad, the polishing rate, etc. are monitored by a process monitor device on the production line, and the change in the residual step caused by the polishing characteristics of the CMP device is predicted, and the film deposition in the film deposition process By depositing a film with the same or thicker film thickness as the residual step by controlling the equipment, it is possible to change the film deposition amount according to process fluctuations, and further improve turnaround time and process fluctuations It is possible to prevent the product yield rate from decreasing.

  (5) The target film is a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon oxide film containing carbon atoms, a metal containing tantalum, a metal containing copper, a metal containing tungsten, or a silicon oxide containing an organic substance. By comprising a film, phosphoborosilicate glass, phosphosilicate glass, or a combination thereof, the effects as described above can be obtained for films on semiconductor devices manufactured by various processes.

  (6) Process monitor device for monitoring the pressure of the polishing pad, residual step or film thickness, and polishing speed, and information processing for receiving information from the process monitor device and processing this information to calculate the residual step after polishing By having the apparatus, it is possible to manufacture a semiconductor that has a high throughput and can suppress a decrease in the yield rate of product due to process variations.

  (7) By the above (1) to (6), it is possible to realize an improvement in manufacturing throughput and cost reduction of the film deposition process and the CMP process while keeping the residual step in the CMP polishing below a specified value.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention relates to a semiconductor device manufacturing technique, and is particularly applicable to a CMP process and a film deposition process in semiconductor manufacturing.

In embodiment concerning this invention, it is explanatory drawing which shows the cross-sectional shape of a semiconductor device in the manufacturing method of a semiconductor device. In embodiment which concerns on this invention, in the manufacturing method of a semiconductor device, it is a graph which shows the result of having calculated | required the magnitude | size of the largest residual level | step difference with respect to polishing amount by simulation. In the embodiment according to the present invention, it is a flowchart showing the process of CMP simulation in the method of manufacturing a semiconductor device. In embodiment which concerns on this invention, it is explanatory drawing which shows the example of a mesh division | segmentation in the manufacturing method of a semiconductor device. In embodiment which concerns on this invention, it is explanatory drawing which shows the manufacturing system of a semiconductor device. In embodiment which concerns on this invention, it is explanatory drawing which shows the content of the database in the manufacturing system of a semiconductor device.

Explanation of symbols

11 ... line (cross-sectional shape), 12 ... line (cross-sectional shape), 15: wiring,
DESCRIPTION OF SYMBOLS 21 ... Film deposition apparatus, 22 ... CMP pre-processing apparatus, 23 ... CMP apparatus, 25 ... Information processing apparatus, 26 ... Data server, 211 ... Film deposition control apparatus, 212 ... CMP control apparatus, 231 ... Process monitor apparatus.

Claims (6)

A method of manufacturing a semiconductor device including a CMP process and a film deposition process in semiconductor manufacturing,
The amount of polishing in which the residual step generated after CMP polishing is within a specified value is predicted by an information processing device,
A method of manufacturing a semiconductor device, comprising depositing a film having a thickness equal to or thicker than the predicted polishing amount in advance before polishing with a CMP apparatus. In the manufacturing method of the semiconductor device according to claim 1,
The method of manufacturing a semiconductor device according to claim 1, wherein the thickness of the deposited film is 1 to 2 times the polishing amount at which the residual step is within a specified value. In the manufacturing method of the semiconductor device of Claim 1 or 2,
The method of manufacturing a semiconductor device, wherein the amount of the residual step is obtained by simulation of the CMP process. In the manufacturing method of the semiconductor device of any one of Claims 1-3,
The pressure distribution applied to the polishing pad, the hardness of the polishing pad, and the polishing rate, which are polishing characteristics of the CMP apparatus, are monitored by a process monitor device in the production line,
The information processing device predicts a change in residual level difference caused by the polishing characteristics of the CMP device,
A method of manufacturing a semiconductor device, comprising: controlling a film deposition apparatus in the film deposition process, which is a process before polishing by the CMP apparatus, to deposit a film having a thickness equal to or thicker than the residual step. In the manufacturing method of the semiconductor device given in any 1 paragraph of Claims 1-4,
The film includes a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon oxide film containing carbon atoms, a metal containing tantalum, a metal containing copper, a metal containing tungsten, a silicon oxide film containing an organic substance, and phosphoborosilicate glass. A method for manufacturing a semiconductor device, comprising: phosphosilicate glass, or a combination thereof. A semiconductor device manufacturing system for realizing a semiconductor device manufacturing method including a CMP process and a film deposition process in semiconductor manufacturing,
A process monitor for monitoring the pressure of the polishing pad, the residual step or film thickness, and the polishing rate;
An information processing apparatus that receives information from the process monitor device and processes the information to calculate a residual step after polishing.

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