JP2007201256A - Shape predicting method and system of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a shape predicting technique of a semiconductor device wherein the simulation of its laminated films can be performed quickly and highly accurately, and its manufacturing faultiness can be prevented previously by controlling accurately the polishing time and polishing quantity of its laminated films. <P>SOLUTION: In the shape predicting method of a semiconductor device, the altitude of the surface of the device is predicted after the CMP process of its films formed by laminating a plurality of different materials (for example, an oxide film 52 and a nitride film 53). In this case, the surface of the device is divided into regions in the direction of its CMP plane. The corresponding altitude of each divided region to its polishing time is predicted based on one or more calculating formulas. In the case of the material of an underlaying layer being exposed to the external in response to the progress of polishing in either one of the respective regions, when calculating the altitude of the exposed region, the parameters included in the altitude calculating formulas are so altered as to be limited to the ones of the exposed region and as to perform thereby the altitude calculation. Consequently, the increase of calculating speed and the increase of the accuracy of calculated result can be realized with respect to the simulation of the CMP of laminated films. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device shape prediction technique, and is particularly effective when applied to a method for predicting the altitude of a device surface after a CMP (Chemical Mechanical Polishing) process of a film formed by laminating a plurality of different materials. Regarding technology.

  For example, technologies as disclosed in Patent Documents 1 to 4 can be cited as semiconductor device shape prediction technologies.

  (1) In Patent Document 1 and Patent Document 2, an insulating film is formed around a silicon nitride film as a stopper on the surface of a metal wiring layer, and polishing of the insulating film is completed based on a change in pH when CMP is performed. A method is described.

  (2) Patent Document 3 describes a method of changing simulation parameters so as to achieve both throughput improvement and flatness maintenance in the CMP method.

(3) Patent Document 4 describes a polishing method in which the value of a parameter included in a basic expression is changed so as to reproduce the characteristics of a CMP apparatus each time a product type to be processed is switched.
JP-A-8-162431 Japanese translation of PCT publication No. 2003-521817 JP 2003-257915 A JP 2003-347258 A

  However, none of Patent Documents 1 to 4 described above is intended to realize simulation of a laminated film with high speed and high accuracy. For example, (1) Patent Literature 1 and Patent Literature 2 are aimed at end point detection, and (2) Patent Literature 3 is a simulation parameter changing method aimed at improving throughput. Further, (3) Patent Document 4 is a method of changing a simulation parameter every time a product type changes instead of a laminated film. As described above, in any of Patent Documents 1 to 4 of the above (1) to (3), it is impossible to realize the simulation of the laminated film at high speed and high accuracy.

  Therefore, the object of the present invention is to solve the above-mentioned problems, to execute a simulation of a laminated film quickly and with high accuracy, and to prevent device manufacturing defects by accurately controlling the polishing time and the polishing amount. It is an object of the present invention to provide a semiconductor device shape prediction technique that can be performed.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  The present invention relates to a semiconductor device shape prediction method using a computer for predicting the shape of a semiconductor device, and predicting an altitude of a device surface after a CMP process of a film formed by laminating a plurality of different materials. In this case, the device surface is divided into regions in the plane direction, and the altitude corresponding to the polishing time in each divided region is predicted based on one or more calculation formulas, and the lower layer is formed in any region by the progress of polishing. When the material is exposed, when calculating the altitude of the exposed area, the altitude calculation is performed by changing the parameter included in the calculation formula only in this area. As a result, it is possible to increase the calculation speed of the multilayer film CMP simulation and to increase the accuracy of the calculation result.

  Preferably, when any kind of stress response function is included in the calculation formula and the underlying material is exposed, the parameter of the stress response function included is changed. As a result, it is possible to increase the calculation speed of the multilayer film CMP simulation and to increase the accuracy of the calculation result.

  Preferably, any one of an empirical formula obtained from actual measurement, a Gaussian function, and a step function is used as the stress response function. As a result, it is possible to achieve both high speed and high accuracy by using an appropriate stress response function with a balance between calculation speed and accuracy.

  Preferably, the parameter included in the stress response function is changed when a lower layer material is exposed. As a result, it is possible to increase the calculation speed of the multilayer film CMP simulation and to increase the accuracy of the calculation result.

  Preferably, the stress response function includes a parameter having a length dimension as a parameter representing a distance at which a strain due to stress reaches, and the parameter is changed when the underlying material is exposed. And As a result, it is possible to increase the calculation speed of the multilayer film CMP simulation and to increase the accuracy of the calculation result.

  Preferably, the target device is laminated with materials from the first layer to the Nth layer counted from the upper surface of the device, and polishing until the first layer is polished and removed from all the divided regions on the device surface. The time T1 is obtained. Thereby, the polishing end point management by the process engineer can be more easily performed.

  More preferably, the polishing time T1 from when the M (1 ≦ M <N) layer starts polishing until it is polished and removed from all the divided regions on the device surface, and the M + 1 layer after starting polishing. The polishing time T2 until the eye is polished and removed from all the divided areas on the device surface is determined simultaneously. Thereby, the polishing end point management by the process engineer can be more easily performed.

  More preferably, using the polishing time T1 and the polishing time T2, the time T3 is calculated by the equation T3 = (T1 + T2) / K (K is a real number of 1 or more), and the time is used for polishing time management. It is characterized by using T3. Thereby, the polishing end point management by the process engineer can be more easily performed.

  More preferably, the polishing amount of one specified divided region of all the divided regions at the polishing times T1, T2 and T3 is set to H1, H2, and H3, and the polishing amount H3 is used for managing the polishing amount. It is characterized by using. Thereby, the polishing end point management by the process engineer can be more easily performed.

  More preferably, the device is a metal containing tantalum, a metal containing copper, a metal containing tungsten, a silicon oxide film, a silicon oxide film containing an organic substance, a silicon nitride film, or silicon nitride added with an element of oxygen. A laminated structure is formed by the film. As a result, CMP simulation of a laminated film made of various materials can be performed at high speed and with high accuracy.

  Further, the present invention is a semiconductor device shape prediction system using a computer for predicting the shape of a semiconductor device, wherein means for inputting parameters of the stress response function and the altitude of each region at each time are calculated. And a means for outputting and storing the altitude of each region and a means for outputting and storing the T1, T2, T3, H1, H2, and H3. Thus, a series of simulations and simulation results can be easily accumulated.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  According to the present invention, simulation of a laminated film can be executed quickly and with high accuracy, and device manufacturing defects can be prevented in advance by accurately controlling the polishing time and the polishing amount.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

(Embodiment 1)
A first embodiment of a semiconductor device shape prediction method according to the present invention will be described below with reference to FIGS. 1 is a cross-sectional view (1) of a device pattern, FIG. 2 is a top view (1) of the device pattern, FIG. 3 is a top view (2) of the device pattern, and FIG. 4 is a characteristic diagram (1) and FIG. 5 is a sectional view (2) of the device pattern, FIG. 6 is a sectional view (3) of the device pattern, and FIG. 7 is a top view (3) of the device pattern.

  First, the stress response function used in the CMP simulation will be described with reference to FIGS.

  First, the polishing process in the CMP process will be described with reference to FIG. In the CMP process, the polishing pad 13 is pressed against the convex pattern 15 of the device and rotated, and the convex portion existing on the device surface is polished and flattened. In the case of the oxide film CMP process, the convex pattern 15 is formed by the oxide film 12 deposited on the pattern 11. At this time, the polishing pad 13 is deformed under the influence of the convex pattern 15 existing on the device surface. The polishing pad 13 is in contact with the convex pattern 15, but due to the deformation of the polishing pad 13, the stress is not concentrated only on the target convex pattern 15 and is bent away from the convex pattern 15.

In order to execute a simulation in consideration of this influence, usually, the local pattern density ρ is averaged by a function called a stress response function F to obtain an averaged pattern density ρ ′. Here, the local pattern density is a ratio of the convex patterns 15 existing per unit area. Usually, the unit area is an area occupied by a region of several tens of μm × several tens of μm, and is 25 μm × 25 μm (= 625 μm ² ) in the present embodiment. In order to obtain the local pattern density ρ, a chip (usually a rectangle or square with a side of several mm in size, several mm: about 1 to 15 mm) is divided into, for example, 25 μm × 25 μm regions as described above. The ratio of the convex pattern in each divided area is obtained.

  FIG. 2 and FIG. 3 show conceptual diagrams of averaged local pattern density ρ and local pattern density ρ ′. In FIG. 2, the black pattern 21 indicates that the local pattern density ρ of the convex pattern occupies 80%. When the averaging process of FIG. 2 is performed, it can be seen that the contour of the pattern 21 is blurred and a distribution of a high density part (gray dark part) and a low density part (gray light part) occurs as shown in FIG. In this way, the distribution within the chip of the average pattern density ρ ′ can be obtained.

  With respect to an expression representing how the polishing proceeds with respect to the polishing time using the average pattern density ρ ′, many papers (for example, Taber H. Smith, Simon J. Fang, Duane S. Boning, Greg B. Shinn, and Jerry A. Stefani, “A CMP Model Combining Density and Time Dependency,” 1999 Chemical Mechanical PolLSI. ) Has been announced and will not be detailed here.

  As described above, in the normal CMP simulation method, the result obtained by averaging the pattern density of the chip using the stress response function F is used for calculating the polishing rate using a specific formula. The stress response function F is a function with respect to the distance r from the point of interest, and has a relationship between the distance and the function value as shown in FIG. 4, for example. The characteristics of the stress response function are defined by parameters related to distance. Here, if the stress response function is expressed by a Gaussian function, the expression of F is as follows.

F (r) = Aexp (−2r ² / B ² )
Here, A is a constant (usually 1.0), B is a parameter [mm], and r is a distance [mm]. The characteristic of F with respect to the distance r is determined by a parameter B having a distance dimension. The larger the value of B, the more slowly the function decays with increasing r. For example, when the case of B = 2 mm and the case of B = 0.2 mm are compared as shown in FIG. 4, the case of B = 2 mm attenuates more gently. As a result, the distribution of the averaged density ρ ′ in FIG. 3 is wider when B = 2 mm than when B = 0.2 mm.

  In the above description, the object to be polished is described as a single layer consisting of only an oxide film. However, in the case of a CMP process for polishing STI (Shallow Trench Isolation), the Si substrate 51 is formed as shown in FIG. A plurality of layers (the oxide film 52 and the nitride film 53) are polished. In FIG. 5, the oxide film 52 is exposed before the polishing, and only the oxide film 52 is polished by contacting the polishing pad with the oxide film 52. However, as the polishing progresses gradually, the nitride film 53 is exposed, and depending on the location, the polishing of the nitride film 53 proceeds.

  In the simulation, area division is performed as shown in FIG. In FIG. 6, 61 and 62 are mesh boundary lines. The meshes divided by the mesh boundary lines 61 and 62 are 611 and 621. The oxide film 52 remains in the mesh 611, and the nitride film 53 is exposed in the mesh 621. When a portion where the nitride film 53 is exposed and a portion where the oxide film 52 remains coexist in one mesh, it is determined that the mesh has the nitride film 53 remaining according to the ratio. It is determined whether the mesh is determined to have the oxide film 52 remaining.

  The determination criteria may be freely changed according to the analysis conditions, but in this embodiment, when the region where the oxide film 52 remains is 50% or more, the mesh is determined as a mesh where the oxide film 52 remains. When the region where the oxide film 52 remains is less than 50%, the mesh is determined as a mesh with the nitride film 53 exposed. If the determination is performed based on this criterion, the mesh on which the nitride film 53 is exposed increases as the polishing time increases. This is shown in FIG.

  FIG. 7A shows a semiconductor chip (before polishing) having a size of x [mm] × y [mm] divided into meshes. Since it is before polishing, in FIG. 7 (1), it is composed only of the mesh 71 (white mesh) in which the oxide film remains. As the polishing proceeds, the mesh 72 with the nitride film exposed gradually spreads as shown in FIGS. 7 (2) and 7 (3). When simulating such a situation, in this embodiment, the value of B in FIG. 4 is set to 2 mm for the mesh 71 where the oxide film remains, and the value of B is set to 0.2 mm for the mesh 72 where the nitride film is exposed. And A larger value of B corresponds to a state in which a soft object is shaved. Usually, the oxide film is handled as described above because it is softer than the nitride film.

  As a result of the STI CMP simulation performed as described above, the error from the actual measurement is within ± 15 nm, and the calculation time using a commercially available personal computer is 1 minute when a 10 mm square system LSI is targeted. Was within.

  As described above, according to the present embodiment, a polishing simulation of a plurality of different layers (two layers in this embodiment) is performed by changing the parameters of the stress response function for each mesh. As a result, it is possible to execute a polishing simulation of a plurality of layers at high speed, high accuracy and simply. That is, the calculation speed of the multilayer film CMP simulation can be increased and the calculation result can be increased in accuracy.

(Embodiment 2)
A second embodiment of the semiconductor device shape prediction method according to the present invention will be described below with reference to FIG. FIG. 8 shows a characteristic diagram (2) of the stress response function.

  In the first embodiment, the Gaussian function shown in FIG. 4 is used. However, a step function as shown in FIG. 8 may be used depending on the simulation target. The same effect can be obtained even by using an empirical formula obtained from actual measurement. That is, it is possible to achieve both high speed and high accuracy by using an appropriate stress response function in consideration of the calculation speed and accuracy.

(Embodiment 3)
A third embodiment of the semiconductor device shape prediction method according to the present invention will be described below.

  In the first embodiment, the target layers are the oxide film and the nitride film, but the same simulation is possible even when there are two or more layers. For example, the same effect can be obtained even when the first layer is made of copper, the second layer is made of tantalum nitride, and the third layer is made of a silicon oxide film containing carbon. That is, a laminated structure is formed of a metal containing tantalum, a metal containing copper, a metal containing tungsten, a silicon oxide film, a silicon oxide film containing organic matter, a silicon nitride film, or a silicon nitride film to which an oxygen element is added. Even in such a case, CMP simulation of a laminated film made of various materials can be performed at high speed and with high accuracy.

(Embodiment 4)
A fourth embodiment of the semiconductor device shape prediction method according to the present invention will be described below with reference to FIG. FIG. 9 shows a top view (4) of the device pattern.

  This embodiment is intended for CMP polishing of a film formed by the STI process. In FIG. 9, FIG. 9 (1) is a stage before polishing, and the entire chip area is covered with a mesh 91 occupied by an oxide film. The time at the polishing start stage in FIG. As the polishing progresses, a mesh 92 from which the nitride film is exposed appears as shown in FIG. This time T is set to T = T1. As the polishing further proceeds, the nitride film is exposed in the entire chip area as shown in FIG.

  As the polishing further proceeds, as shown in FIGS. 9 (4) and 9 (5), the mesh 93 is eventually polished, and a mesh 93 appears in which the underlying film underlying the nitride film is exposed. When counting from T = 0, the time at which the base film is exposed is defined as T2. As described above, the time T1 until the oxide film is removed and the time T2 until the base film is exposed can be obtained. T1 and T2 described above are all obtained by simulation.

  Usually, when an oxide film residue is generated in the STI polishing process, a defect may occur in a later process. Further, when the nitride film is removed and the base is polished, the operation of the MOS device formed in a later process is adversely affected. Therefore, if the optimum polishing time is predicted in advance by simulation, it is possible to avoid the cause of failure described above. Therefore, if the optimum polishing time T3 is determined as T3 = (T1 + T2) / 2 and the above polishing time is applied to an actual polishing process, it is possible to prevent excessive shaving and remaining oxide film. Thereby, the polishing end point management by the process engineer can be more easily performed.

  As described above, according to the present embodiment, it is possible to avoid defects caused by polishing by predicting an optimal polishing time. In other words, polishing failure can be suppressed by reflecting the simulation result in an actual process.

(Embodiment 5)
Embodiment 5 of the semiconductor device shape prediction method according to the present invention will be described below.

  In the fourth embodiment, the optimum polishing time is calculated as T3 = (T1 + T2) / 2. However, any real value K (K ≧ 1) is used as T3 = (T1 + T2) / K. May be. In this case, the optimum value of K is determined by comparing experiments and simulations. Therefore, also in the present embodiment, the same effect as in the fourth embodiment can be expected.

(Embodiment 6)
A sixth embodiment of the semiconductor device shape prediction method according to the present invention will be described below.

  In the fourth embodiment, the STI is used as a polishing target composed of a plurality of layers. However, the same effect can be obtained even when applied to polishing a film composed of a plurality of multilayer structures. In this case, the polishing time T1 from the start of polishing of the M (1 ≦ M <N) layer until polishing and removal from the entire region of the device surface, and the M + 1 layer from the start of polishing on the device surface The polishing time T2 until polishing and removal from all the divided regions is obtained, and the optimum polishing time T3 is obtained as T3 = (T1 + T2) / K.

(Embodiment 7)
A seventh embodiment of the semiconductor device shape prediction method according to the present invention will be described below.

  In the above Embodiments 4 to 6, the polishing times T1, T2, and T3 are obtained. In this embodiment, a specific mesh Z (ix, iy) (ix, iy is a mesh number in the x direction, iy is a mesh number in the y direction), and the polishing amounts in the mesh Z (ix, iy) are H1, H2, and H3 when polishing is performed with the polishing times T1, T2, and T3. In the CMP polishing process, a special pattern for measuring the film thickness is prepared at a specific location in the chip, and it may be determined whether or not the polishing end point has been reached based on the polishing amount of this pattern. In order to cope with such an end point determination method, it is necessary to perform the determination based on the polishing amount instead of the polishing time. By setting H3 described above as the optimum polishing amount and performing the actual polishing, by controlling the polishing amount at the position corresponding to the mesh Z (ix, iy) to be H3, excessive polishing or Polishing residue can be prevented.

  As described above, according to the present embodiment, polishing failure can be suppressed by reflecting a simulation result in an actual process.

(Embodiment 8)
An eighth embodiment of the semiconductor device shape prediction method according to the present invention will be described below with reference to FIG. FIG. 10 shows a configuration diagram of a polishing time / polishing amount prediction system.

  The semiconductor device shape prediction method in the first to seventh embodiments is realized by a polishing time / polishing amount prediction system (shape prediction system) using a computer. In the present embodiment, the polishing time / polishing amount prediction is performed. An example of the system will be described.

  As shown in FIG. 10, the polishing time / polishing amount prediction system in the present embodiment includes signal lines 101, 102, 103 and 104, an input / output terminal 131, a calculation server 132, a data server 134, and a CMP apparatus 133. The The input / output terminal 131 includes means for inputting parameters of the stress response function, means for outputting the altitude of each region, means for outputting the T1, T2, T3, H1, H2, and H3. The computer server 132 includes means for calculating the altitude of each area at each time. The data server 134 includes means for storing the altitude of each area, means for storing the T1, T2, T3, H1, H2, and H3.

  When the product chip to be polished and the type of the stress response function F are designated from the input / output terminal 131, the polishing conditions and the type of deposited film, the design data of the product chip to be polished (usually GDSII and Stored in a format called) is transferred to the calculation server 132. The calculation server 132 executes a CMP polishing simulation to calculate T1, T2, T3, H1, H2, and H3 described in the above embodiments. This result is stored in the data server 134 and displayed on the input / output terminal 131.

  At the same time, the data is output to an external network through the signal line 104, and the data is transferred to each production site. Further, as soon as the results of T1, T2, T3, H1, H2, and H3 are known, the CMP apparatus 133 is automatically driven to perform polishing for a required polishing time or polishing amount. The driving of the CMP apparatus 133 may be executed by an instruction from the input / output terminal 131 instead of automatic construction.

  By configuring the system as described above, it is easy to accumulate a series of simulations and simulation results, and it is possible to quickly execute simulations and control the appropriate polishing time and amount according to the results. It is possible to avoid the occurrence of defects. In other words, when executing a CMP polishing simulation of a multi-layer device, a stress response function having different parameters for each layer is used, and an optimal polishing time and polishing amount are obtained from the simulation results, and the polishing end point of the actual CMP process is determined. By using it for management, polishing simulation of the laminated film can be executed quickly and with high accuracy, and device manufacturing defects can be prevented beforehand by accurately controlling the polishing time and the polishing amount.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention relates to a semiconductor device shape prediction technique, and is particularly effective when applied to a method for predicting the altitude of a device surface after a CMP process of a film formed by laminating a plurality of different materials.

It is sectional drawing (1) which shows a device pattern in Embodiment 1 in the shape prediction method of the semiconductor device concerning this invention. In Embodiment 1 in the shape prediction method of the semiconductor device concerning this invention, it is a top view (1) which shows a device pattern. In Embodiment 1 in the shape prediction method of the semiconductor device concerning this invention, it is a top view (2) which shows a device pattern. In Embodiment 1 in the shape prediction method of the semiconductor device concerning this invention, it is a characteristic view (1) which shows a stress response function. In Embodiment 1 in the shape prediction method of the semiconductor device concerning this invention, it is sectional drawing (2) which shows a device pattern. In Embodiment 1 in the shape prediction method of the semiconductor device concerning this invention, it is sectional drawing (3) which shows a device pattern. In Embodiment 1 in the shape prediction method of the semiconductor device concerning this invention, it is a top view (3) which shows a device pattern. In Embodiment 2 in the shape prediction method of the semiconductor device concerning this invention, it is a characteristic view (2) which shows a stress response function. In Embodiment 4 in the shape prediction method of the semiconductor device concerning this invention, it is a top view (4) which shows a device pattern. In Embodiment 8 in the shape prediction method of the semiconductor device concerning this invention, it is a block diagram which shows polishing time and polishing amount prediction system.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11 ... Pattern, 12 ... Oxide film, 13 ... Polishing pad, 15 ... Convex pattern, 21 ... Pattern, 51 ... Si substrate, 52 ... Oxide film, 53 ... Nitride film, 61 ... Mesh boundary line, 62 ... Mesh boundary line, 611: Divided mesh, 621: Divided mesh, 71: Mesh where oxide film remains, 72: Mesh where nitride film is exposed, 91: Mesh occupied by oxide film, 92 ... Mesh where nitride film is exposed, 93... Mesh on which base film is exposed 101 to 104 Signal line 131 Input / output terminal 132 132 Calculation server 133 CMP apparatus 134 Data server

Claims (11)

A method for predicting the shape of a semiconductor device using a computer for predicting the shape of a semiconductor device,
In predicting the elevation of the device surface after the CMP process for a film formed by laminating a plurality of different materials, the device surface is divided into regions in the plane direction, and the elevation corresponding to the polishing time in each divided region is calculated. When prediction is made based on one or more calculation formulas and the underlying material is exposed in any region due to the progress of polishing, the parameters included in the calculation formulas are calculated when calculating the elevation of the exposed region. A method for predicting a shape of a semiconductor device, wherein altitude calculation is performed by changing only in this region. In the semiconductor device shape prediction method according to claim 1,
A shape of a semiconductor device characterized in that, when any kind of stress response function is included in the calculation formula and the underlying material is exposed, parameters of the stress response function included are changed. Prediction method. In the semiconductor device shape prediction method according to claim 2,
Any one of an empirical formula obtained from actual measurement, a Gaussian function, and a step type function is used as the stress response function. In the semiconductor device shape prediction method according to claim 2,
A method for predicting a shape of a semiconductor device, wherein a parameter included in the stress response function is changed when a lower layer material is exposed. In the semiconductor device shape prediction method according to claim 2,
The stress response function includes a parameter having a length dimension as a parameter representing a distance at which a strain due to stress reaches, and the parameter is changed when the underlying material is exposed. Device shape prediction method. In the semiconductor device shape prediction method according to claim 1,
The target device is laminated with materials from the first layer to the N-th layer counted from the upper surface of the device, and the polishing time T1 until the first layer is polished and removed from all the divided regions on the device surface is determined. A method for predicting the shape of a semiconductor device. In the semiconductor device shape prediction method according to claim 6,
Polishing time T1 from the start of polishing of the M (1 ≦ M <N) layer to polishing and removal from all the divided regions on the device surface, and the M + 1 layer from the start of polishing to the entire surface of the device A method for predicting a shape of a semiconductor device, characterized by simultaneously obtaining a polishing time T2 until polishing and removal from a divided region. In the semiconductor device shape prediction method according to claim 7,
Using the polishing time T1 and the polishing time T2, the time T3 is calculated by the equation T3 = (T1 + T2) / K (K is a real number of 1 or more), and the time T3 is used for management of the polishing time. A feature prediction method of a semiconductor device. The shape prediction method of a semiconductor device according to claim 8,
Of all the divided regions at the polishing times T1 and T2 and the time T3, the polishing amount of one specified divided region is set to H1, H2 and H3, and the polishing amount H3 is used for managing the polishing amount. Semiconductor device shape prediction method. In the shape prediction method of the semiconductor device according to any one of claims 1 to 9,
The device has a stacked structure of a metal containing tantalum, a metal containing copper, a metal containing tungsten, a silicon oxide film, a silicon oxide film containing an organic material, a silicon nitride film, or a silicon nitride film to which an oxygen element is added. A method for predicting the shape of a semiconductor device. A semiconductor device shape prediction system using a computer for predicting the shape of a semiconductor device,
In predicting the elevation of the device surface after the CMP process for a film formed by laminating a plurality of different materials, the device surface is divided into regions in the plane direction, and the elevation corresponding to the polishing time in each divided region is calculated. When prediction is made based on one or more calculation formulas and the underlying material is exposed in any region due to the progress of polishing, the parameters included in the calculation formulas are calculated when calculating the elevation of the exposed region. Elevation calculation is carried out by changing only in this area,
When any kind of stress response function is included in the formula and the underlying material is exposed, the parameters of the stress response function included are changed,
The target device is laminated with materials from the first layer to the N-th layer counted from the upper surface of the device, and the device surface is fully divided after the M (1 ≦ M <N) layer starts polishing. A polishing time T1 until polishing and removal from the region and a polishing time T2 from the start of polishing until the M + 1 layer is polished and removed from all the divided regions of the device surface are simultaneously obtained,
Using the polishing time T1 and the polishing time T2, the time T3 is calculated by the equation T3 = (T1 + T2) / K (K is a real number of 1 or more), and the time T3 is used for management of the polishing time.
Of all the divided regions at the polishing times T1, T2 and T3, the polishing amount of one designated divided region is set to H1, H2, and H3, and the polishing amount H3 is used for polishing amount management.
Means for inputting parameters of the stress response function; means for calculating the elevation of each area at each time; means for outputting and storing the elevation of each area; and T1, T2, T3, H1, H2, and H3 A semiconductor device shape prediction system characterized in that it also has means for outputting and storing.

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