JP2007036068A - System and method for specifying cause of fault, and method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a system for specifying the causes of faults, capable of easily specifying a manufacturing process that causes faults of a semiconductor device. <P>SOLUTION: The system for specifying the cause of fault of the semicoductor device manufactured by a series of processes, respectively implemented with a group of manufacturing devices 31 to 3n, comprises a characteristics map forming part 10 for forming the characteristics map expressing an in-plane distribution of the electrical characteristics of the semiconductor device inspected by an inspecting device 5, an individual map forming part 11 for forming the individual map in every process expressing the in-plane distribution of an execution in respective processes measured by a measuring device 4, a synthetic map forming part 12 for forming the composited map, by selecting and compositing a plurality of individual maps out of the induvidual map in respective process, and a specifying part 13 for specifying the corresponding process as the cause of fault, by comparing the composited map with the characteristic map. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a failure cause identification method, and particularly provides a failure cause identification system, a failure cause identification method, and a semiconductor device manufacturing method.

  In the manufacturing process of a semiconductor device, it is important to identify and improve a manufacturing apparatus and a manufacturing process that cause a defect. Conventionally, a process (layer) that causes a defect is identified from a wafer map that represents electrical characteristics such as a fail bit map and a die sort (D / S) map, and a cross-sectional scanning microscope (SEM) analysis in the vicinity of the identified process. There is a technique for specifying a manufacturing apparatus and a manufacturing process that cause a defect from an analysis of the device QC data and product trend data (see, for example, Patent Document 1).

In the above method, when the cause of failure is in a single manufacturing apparatus or manufacturing process, it is easy to identify the cause of failure. However, it is difficult to specify when a plurality of manufacturing processes and corresponding manufacturing apparatuses are intertwined and cause defects. As described above, it may be difficult to specify the semiconductor device due to the cause of the defect.
JP 2004-158820 A

  An object of the present invention is to provide a failure cause identification system, a failure cause identification method, and a semiconductor device manufacturing method that can easily specify a manufacturing process that causes a failure of a semiconductor device.

  According to one aspect of the present invention, for semiconductor devices manufactured through a series of steps executed by a group of manufacturing apparatuses, (a) aspects of electrical characteristics of the semiconductor devices inspected by the inspection apparatus A characteristic map forming unit that forms a characteristic map that expresses the internal distribution, and (b) a single map formation that forms a single map that expresses the in-plane distribution of the performance of each process measured by the measuring device for each process. And (c) a composite map forming unit that forms a composite map by selecting a plurality of single maps from a single map for each process, and (d) comparing the composite map with the characteristic map. Thus, a failure cause identification system including a identification unit that identifies a corresponding process as a failure cause is provided.

  According to another aspect of the present invention, (b) a step of executing a series of processes for manufacturing a semiconductor device, (b) a step of measuring the performance of each process, and (c) a series of processes. A step of inspecting the electrical characteristics of the semiconductor device after passing, (d) a step of forming a characteristic map representing the in-plane distribution of the electrical characteristics, and (e) an in-plane distribution of the performance for each process. A step of forming a single map to be expressed; (f) a step of selecting a plurality of single maps from the single maps for each process and combining them to form a composite map; and (g) a composite map and a characteristic map. By comparing these, a failure cause identification method including a step of identifying a corresponding process as a failure cause is provided.

  According to another aspect of the present invention, (b) a step of executing a series of processes for manufacturing a semiconductor device, (b) a step of measuring the performance of each process, and (c) a series of processes. A step of inspecting the electrical characteristics of the semiconductor device after passing, and (d) forming a characteristic map that expresses the in-plane distribution of electrical characteristics, and a single map that expresses the in-plane distribution of workmanship for each process Create and select multiple single maps from the single maps for each process, combine them to form a composite map, and compare the composite map with the characteristic map to identify the corresponding process as the cause of failure A method of manufacturing a semiconductor device, comprising: (e) correcting a manufacturing condition of a process identified as a cause of a defect; and (f) executing a series of processes using the corrected manufacturing condition. It is provided.

  According to the present invention, it is possible to provide a failure cause identification system, a failure cause identification method, and a semiconductor device manufacturing method capable of easily specifying a manufacturing process that causes a failure of a semiconductor device.

  Next, embodiments of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones. Therefore, specific thicknesses and dimensions should be determined in consideration of the following description. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings. Further, the embodiments described below exemplify apparatuses and methods for embodying the technical idea of the present invention, and the technical idea of the present invention includes the material, shape, structure, The layout is not specified as follows. The technical idea of the present invention can be variously modified within the scope of the claims.

  As shown in FIG. 1, the failure cause identifying system according to the embodiment of the present invention is a group of manufacturing apparatuses 31, 32, 33,... That execute each of a series of steps for manufacturing a semiconductor device. .., 3n, a measuring device 4 for measuring the performance of each process, an inspection device 5 for inspecting the electrical characteristics of the semiconductor device after a series of processes, and a characteristic expressing the in-plane distribution of the electrical characteristics A characteristic map forming unit 10 that forms a map, a single map forming unit 11 that forms a single map that expresses the in-plane distribution of performance for each process, and a plurality of single maps from the single map for each process Are combined to form a composite map, and a composite unit and a characteristic map are compared to identify a corresponding process as a cause of failure.

  The single map forming unit 11, the characteristic map forming unit 10, the composite map forming unit 12, and the specifying unit 13 are included in a module in the central processing unit (CPU) 1, for example. The CPU 1, the group of manufacturing apparatuses 31, 32, 33,..., 3 n, the measuring apparatus 4 and the inspection apparatus 5 are connected by a bus 9. A main storage device 6, an input device 7, an output device 8 and the like are connected to the bus 9. In addition to the bus 9, connection states using various communication networks such as a wireless LAN can be employed.

The manufacturing apparatuses 31, 32, 33,..., 3n include, for example, an ion implantation apparatus, an impurity diffusion apparatus, a thermal oxidation apparatus for forming a silicon oxide film (SiO ₂ film), an SiO ₂ film, and a phosphor glass ( Chemical vapor deposition (CVD) apparatus for depositing PSG) film, boron glass (BSG) film, boron phosphorous glass (BPSG) film, silicon nitride film (Si ₃ N ₄ film), polysilicon film, etc., PSG film, Heat treatment apparatus for reflowing (melting) BSG film, BPSG film, etc., heat treatment apparatus for densifying CVD oxide film, etc., heat treatment apparatus for forming silicide film, sputtering apparatus for depositing metal wiring layer, vacuum evaporation apparatus, and metal wiring Plating processing apparatus for forming a layer by plating, chemical / mechanical polishing (CMP) apparatus for polishing the surface of a semiconductor substrate, dry or wet etching for etching the surface of a semiconductor substrate Etching device, cleaning device for resist removal and cleaning with solution, spin coating device (spinner) related to photolithography processing, exposure device such as stepper, dicing device, and electrode of dicing chip-like semiconductor device connected to lead frame Various manufacturing apparatuses such as a bonding apparatus are included.

  Further, these manufacturing apparatuses 31, 32, 33,..., 3n include various inspection apparatuses and measuring apparatuses such as an interference film thickness meter, an ellipsometer, a contact film thickness meter, a microscope, and a resistance measuring device. May also be included. Furthermore, ancillary facilities such as a pure water treatment device and a gas purification device may be included. Further, these manufacturing apparatuses 31, 32, 33,..., 3n can be applied to either a batch type apparatus or a single wafer type apparatus. The batch type apparatus or the single wafer type apparatus may be similarly applied to all the embodiments described later.

  As the measuring device 4, a scanning electron microscope (SEM), an interference film thickness meter, an ellipsometer, or the like can be used. The measuring device 4 measures the quality (QC data) such as the thickness of the thin film and the dimension and shape of the pattern in each process. A plurality of types and a plurality of measuring devices 4 may be arranged according to the manufacturing devices 31, 32, 33,. The measured performance is stored in the performance storage unit 21 of the data storage device 2.

  As the inspection device 5, a D / S tester, a final tester, or the like can be used. The inspection device 5 performs a D / S test, a final test, or the like on the semiconductor device that has undergone a series of steps to inspect the electrical characteristics. The result of the inspection is stored in the characteristic storage unit 22 of the data storage device 2.

  Here, an element isolation (STI) formation process in the manufacturing process of the semiconductor device using the manufacturing apparatuses 31, 32, 33,..., 3n is described with reference to the flowchart of FIG. This will be described with reference to the process cross-sectional view of FIG.

In step S <b> 11 of FIG. 2, the lot is input to the production line 3. In step S12, as shown in FIG. 3, a buffer oxide film (thermal oxide film) 102 is formed on the silicon (Si) substrate 101 by a thermal oxidation method. In step S13, a silicon nitride film (Si ₃ N ₄ film) 103 is deposited on the thermal oxide film 102 by chemical vapor deposition (CVD) or the like. In step S14, a TEOS film 104 is deposited as a hard mask on the Si ₃ N ₄ film 103 by CVD or the like. In step S 15, a resist film 105 is applied on the TEOS film 104.

In step S16, the quality (QC data) of the thermal oxide film 102, the Si ₃ N ₄ film 103, and the TEOS film 104, such as the film thickness T _SiN, is measured using the measurement apparatus 4 shown in FIG. The measured performance is stored in the performance storage unit 21.

In step S17, as shown in FIG. 4, the resist film 105 is patterned using a lithography technique. In step S19, as shown in FIG. 5, using the patterned resist film 105 as a mask, the TEOS film 104, the Si ₃ N ₄ film 103, and a part of the thermal oxide film 102 are formed by reactive ion etching (RIE) or the like. Selectively remove. In step S20, the remaining resist film 103 is removed using a registry mover or the like as shown in FIG. In step S <b> 21, the quality of the opening width W _{SiN and the} like of the Si ₃ N ₄ film 103 is measured using the measuring device 4. The measured performance is stored in the performance storage unit 21.

  In step S22, as shown in FIG. 7, a part of the Si substrate 101 is selectively removed by RIE using the TEOS film 104 as a hard mask to form the STI trench 100. Further, in the pull back process, as shown in FIG. 8, the top portion of the TEOS film 104 is isotropically etched so as to recede from the end portion of the Si substrate 101. The pull-back process prevents the oxide film embedded in the STI trench 100 in the subsequent process from dropping into the STI trench 100 and, at the same time, widens the STI opening and facilitates the embedding.

In step S23, using the measurement apparatus 4, the STI opening width W _Si , the STI groove depth D _STI from the surface of the Si substrate 101 to the bottom of the STI groove 100, and the STI taper angle θ {= (θ _L + θ _R ) / 2} Measure the performance of etc. The measured performance is stored in the performance storage unit 21.

  In step S24, as shown in FIG. 9, the sidewall of the Si substrate 101 is oxidized by a thermal oxidation method or the like. In step S25, as shown in FIG. 10, the insulating film 106 is embedded by high-density plasma CVD (HDP-CVD) or the like.

  In each process, the device QC data is acquired from the corresponding manufacturing devices 31, 32, 33,..., 3n and stored in the device QC data storage unit 23. Further, the lot QC data to be processed is acquired and stored in the lot QC data storage unit 24.

  Examples of processes that may cause defects in the semiconductor device include an element isolation formation process, an impurity implantation process, a gate electrode formation process, and a multilayer wiring process. In the embodiment of the present invention, for the sake of simplicity, only the element isolation forming step as shown in FIG. 2 is considered.

  The CPU 1 illustrated in FIG. 1 includes a characteristic map forming unit 10, a single map forming unit 11, a composite map forming unit 12, a specifying unit 13, and a correcting unit 14. The characteristic map forming unit 10 forms a characteristic map that represents the in-plane distribution of the electrical characteristics of the semiconductor device after a series of steps based on the inspection result stored in the characteristic storage unit 22. The characteristic map includes a D / S map, a fail bit map, and the like. FIG. 11 shows a D / S map representing the in-wafer distribution as a logic D / S result. “◯” indicates a non-defective product, “Δ” indicates redundancy relief, “■” indicates a DC failure, and “▼” indicates an operation (function) failure. The characteristic map is stored in the characteristic map storage unit 25 shown in FIG.

The single map forming unit 11 forms a single map representing the in-plane distribution of the performance of the semiconductor device for each process based on the performance stored in the performance storage unit 21. It is preferable to measure the performance for each mesh obtained by dividing the wafer surface in chip units or shot units, but in reality, it is based on the performance of several to 10 or more points in the surface, or about 50 points at best. Using the interpolation method such as bilinear plot and simple arithmetic mean, the performance of each mesh is generated. The single map forming unit 11 is, for example, a single map that expresses the in-plane distribution of the STI opening width W _Si , a single map that expresses the in-plane distribution of the STI depth D _STI , and the quality of the STI taper angle θ. A single map expressing the in-plane distribution is formed as shown in FIGS. The single map is stored in the single map storage unit 26 of the data storage device 2.

  The composite map forming unit 12 shown in FIG. 1 selects a plurality of single maps from the single maps for each process formed by the single map forming unit 11 and combines them to create a new index. Form a composite map. The composite map forming unit 12 includes a process number determination module 121, a selection module 122, and a composite module 123.

The process number determination module 121 determines the number of processes to be combined as an index. The selection module 122 considers the manufacturing process flow and lists what indexes can be obtained from the performance (single map) in each unit process. For example, using the STI depth D _STI and the STI opening width W _Si shown in FIG. 8 which are the results of the etching process in step S22 and the lithography process in step S17 in FIG. Create as index I ₁ :
I ₁ = D _STI / W _Si (1)
As another example, the film thickness T _SiN and STI depth D _STI of the thermal oxide film 102, the Si ₃ N ₄ film 103 and the TEOS film 104, which are the results of the deposition process in steps S12 to S14, and the performance of the lithography process in step S17. Using the Si ₃ N ₄ opening width W _SiN , the index I ₂ is created by Equation (2).

I ₂ = (T _SiN + D _STI ) / W _SiN (2)
As another example, using the Si ₃ N ₄ opening width W _SiN and the STI depth D _STI , an approximation of the STI cross-sectional area under the Si substrate 101 is created as an index I ₃ by Equation (3).

I ₃ = D _STI (W _Si −D _STI / tan θ) (3)
As another example, by using the film thickness T _SiN , the STI depth D _STI , and the Si ₃ N ₄ opening width W _SiN , an approximation of the opening area under the Si ₃ N ₄ film 103 is used as an index by the equation (4). to create as I _4.

I ₄ = (T _SiN + D _STI ) {W _SiN − (T _SiN + D _STI ) / tan θ} (4)
The synthesis module 123 shown in FIG. 1 selects a plurality of single maps based on the list of indices I _{1 to} I ₄ selected by the selection module 122, and synthesizes them to form a composite map. For example, a composite map that represents the in-plane distribution of the aspect ratio indicating the index I ₁ using the STI opening width W _Si shown in the single map of FIG. 12 and the STI depth D _STI shown in the single map of FIG. As shown in FIG. Note that the composite map forming unit 12 may form not only a single composite map, but also a plurality of types of composite maps corresponding to the indices I _{1 to} I ₄ , for example.

  The identifying unit 13 illustrated in FIG. 1 compares the composite map and the characteristic map. As a method for comparison, for example, the shade of a color representing a numerical value representing a shot (mesh) that divides the composite map and the characteristic map is normalized step by step with a numerical value between 0 and 1. Then, the numerical value is compared with the characteristic map and the composite map for each shot (mesh), and the composite map is related to the characteristic map if the sum of the differences is smaller than the threshold value stored in the threshold value storage unit 28. Judge.

  Alternatively, the shade of a color representing a numerical value representing a shot (mesh) is standardized step by step with a numerical value between 0 and 1. A contour map (contour diagram) is drawn for each wafer based on this numerical value. A threshold value used as a criterion for similarity determination stored in the threshold value storage unit 28 is read out, and it is determined whether the composite map is related to the characteristic map from the similarity of contour lines corresponding to the threshold value. When comparing for each mesh, the corresponding coordinates are compared with each other. However, in the contour diagram, the mesh sizes of the composite map and the characteristic map may not match.

  When there are a plurality of types of composite maps, the specifying unit 13 compares each of the plurality of composite maps with the characteristic map to determine whether the composite map is similar to the characteristic map. A composite map having a similar tendency having a high correlation with the characteristic map is extracted from a plurality of types of composite maps, and a manufacturing process and a manufacturing apparatus corresponding to the quality of the extracted composite map are identified as the cause of failure. For example, when the in-plane distribution of the composite map shown in FIG. 15 and the in-plane distribution of the characteristic map shown in FIG. 11 are determined to have a high correlation, the etching process of step S22 shown in FIG. And the lithography process of step S17 and the manufacturing apparatus corresponding to it are specified as the cause of the defect.

  The correction unit 14 shown in FIG. 1 corrects the manufacturing conditions identified as the cause of the defect and the manufacturing conditions of the manufacturing process. The corrected manufacturing conditions are stored in the manufacturing condition storage unit 20, and the previous manufacturing conditions are updated.

  The CPU 1 shown in FIG. 1 further includes an input / output control device (interface) and a storage device management device (not shown). The input / output control device (interface) controls input / output of signals and the like between the CPU 1, the input device 7, and the output device 8. The storage device management device manages input / output with the data storage device 2 and the main storage device 6.

  The data storage device 2 includes a manufacturing condition storage unit 20 that stores manufacturing conditions, a performance storage unit 21 that stores the quality measured by the measuring device 4, and a characteristic storage unit 22 that stores the electrical characteristics acquired by the inspection device 5. , Obtained from the device QC data storage unit 23 for storing the device QC data obtained from the manufacturing devices 31, 32, 33,..., 3n, and the manufacturing devices 31, 32, 33,. A lot QC data storage unit 24 for storing lot QC data, a characteristic map storage unit 25 for storing a characteristic map formed by the characteristic map forming unit 10, and a single map storage for storing a single map formed by the single map forming unit 11. Unit 26, composite map storage unit 27 that stores the composite map created by the composite map forming unit 12, determination of the similarity between the characteristic map and the composite map Threshold storage unit 28 that stores the threshold value that is a quasi, failure cause storage unit that stores the manufacturing devices 31, 32, 33,... 29.

  As the input device 7, for example, a recognition device such as a keyboard, a mouse, and an OCR, a graphic input device such as an image scanner, and a special input device such as a voice input device can be used. As the output device 8, a display device such as a liquid crystal display or a CRT display, a printing device such as an ink jet printer or a laser printer, or the like can be used. The output device 8 can display, for example, the characteristic map shown in FIG. 11, the single map shown in FIGS. 12 to 14, the composite map shown in FIG.

  The main storage device 6 functions as a temporary data memory or the like that temporarily stores data or the like used during program execution processing in the CPU 1 or is used as a work area. As the main storage device 6, for example, a semiconductor memory, a magnetic disk, an optical disk, a magneto-optical disk, a magnetic tape, or the like can be used.

  Next, the failure cause identification method according to the embodiment of the present invention will be described with reference to the flowchart of FIG. In addition, a series of processes are previously performed using a corresponding group of manufacturing apparatuses 31, 32, 33,..., 3n to manufacture a semiconductor device. The performance of the semiconductor device is measured for each series of processes, and the measurement result is stored in the performance storage unit 21. The electrical characteristics of the semiconductor device after a series of steps are inspected, and the inspection results are stored in the characteristic storage unit 22.

  In step S <b> 0, the characteristic map forming unit 10 forms a characteristic map that represents the in-plane distribution of the electrical characteristics of the semiconductor device after a series of steps based on the inspection result.

  In step S <b> 1, the single map forming unit 11 forms a plurality of single maps representing the in-plane distribution of performance for each process based on the measurement result stored in the performance storage unit 21.

  In step S2, the composite map forming unit 12 forms a composite map by the following steps S2a to S2c. In step S2a, the process number determination module 121 determines the number of processes to be combined as an index. The selection module 122 selects an index obtained by combining performance with the determined number of steps. Based on the selected index, the synthesis module 123 selects a plurality of single maps from a single map for each process, and combines them to form a composite map.

  In step S <b> 3, the specifying unit 13 extracts a composite map having a high correlation with the characteristic map by comparing the composite map with the characteristic map. A manufacturing process and a manufacturing apparatus corresponding to the single map and the quality of the extracted composite map are identified as the cause of the defect.

  In step S4, the correction unit 14 corrects the manufacturing process and the manufacturing conditions of the manufacturing apparatus identified as the cause of the defect. The corrected manufacturing conditions are stored in the manufacturing condition storage unit 20.

  According to the failure cause identification system and the failure cause identification method according to the embodiment of the present invention, a composite map obtained by combining a plurality of single maps is compared with a characteristic map, and thus a plurality of manufacturing processes cause a failure. However, it is possible to easily specify a plurality of manufacturing processes as causes of defects. Therefore, it is possible to specify the cause of the failure in a multifaceted manner with higher precision than when only a single manufacturing process is specified. For example, it is possible to easily extract a systematic failure that is likely to cause an electrical failure with respect to the appearance that appears normal at a glance.

  A series of procedures shown in FIG. 16, that is: (a) a characteristic map representing in-plane distribution of electrical characteristics of the semiconductor device after a series of steps based on the electrical characteristics acquired by the inspection apparatus 5 (B) a step of forming a single map representing the in-plane distribution of performance based on the performance measured by the measuring device 4 for each process; (c) a single map for each process. A step of selecting a plurality of single maps from them and synthesizing them to form a composite map; (d) comparing the composite map with the characteristic map, and a step corresponding to the single map and the quality of the composite map. (E) a step of correcting the manufacturing conditions of the process identified as the cause of the defect is an algorithm program equivalent to FIG. A constant program) can be executed by controlling the defect cause identifying device shown in FIG.

  This program may be stored in the data storage device 2 of the computer system constituting the failure cause identification system shown in FIG. Further, the program can be stored in a computer-readable recording medium, and the recording medium can be read into the data storage device 2 of the failure cause identification system to execute the series of procedures of the present invention.

  Here, the “computer-readable recording medium” means a medium that can record a program such as an external memory device of a computer, a semiconductor memory, a magnetic disk, an optical disk, a magneto-optical disk, and a magnetic tape. To do. Specifically, a flexible disk, CD-ROM, MO disk, etc. are included in the “computer-readable recording medium”. For example, the main body of the failure cause identification system can be configured to incorporate or externally connect a flexible disk device (flexible disk drive) and an optical disk device (optical disk drive). Inserting a flexible disk into the flexible disk drive or a CD-ROM into the optical disk drive from its insertion slot and performing a predetermined read operation causes the programs stored in these recording media to be defective. It can be installed in the data storage device 2 constituting the specific system. A ROM or magnetic tape device can also be used by connecting a predetermined drive device. Furthermore, this program can be stored in the data storage device 2 via an information processing network such as the Internet.

  Next, a method for manufacturing a semiconductor device (LSI) according to the embodiment of the present invention will be described with reference to the flowchart of FIG. The semiconductor device manufacturing method described below is an example, and it is needless to say that the semiconductor device can be realized by various other manufacturing methods including this modification.

  (A) First, in step S100, electrical characteristics are obtained by process simulation / lithography simulation or device simulation. LSI circuit simulation is performed using the electrical characteristics, and design pattern layout data (design data) is created.

  (B) Next, in step S200, the layout data created in step S100 is converted into drawing data. Based on the drawing data, using a pattern generator (PG) or the like, a photomask for each layer corresponding to each stage of the LSI manufacturing process is produced, and a set of photomasks is prepared.

  (C) In the front-end process (wafer process) in step S302, a series of steps including an oxidation process in step S310, a resist coating process in step S311, a photolithography process in step S312, an ion implantation process in step S313, and a heat treatment process in step S314. The above process is repeated using a corresponding group of manufacturing apparatuses 31, 32, 33,..., 3n to process the wafer. In each process, the quality is obtained by the measuring device 4. The performance is stored in the performance storage unit 21 as needed. When the series of processes is completed, the process proceeds to step S303.

  (D) In step S303, a back-end process (surface wiring process) in which wiring processing is performed on the wafer surface is performed. In the back-end process, a series of processes such as a chemical vapor deposition (CVD) process in step S315, a resist coating process in step S316, a photolithography process in step S317, an etching process in step S318, and a metal deposition process in step S319, The wafer is processed by repeatedly using a corresponding group of manufacturing apparatuses 31, 32, 33,..., 3n. In each process, the quality is obtained by the measuring device 4. The performance is stored in the performance storage unit 21 as needed. When the multilayer wiring structure is completed through a series of steps, the process proceeds to step S304.

  (E) In step S304, the wafer is divided into a predetermined chip size by a dicing device such as a diamond blade. Then, after mounting on a packaging material such as metal or ceramics and connecting the electrode pad on the chip and the lead of the lead frame with a gold wire, a required package assembly process such as resin sealing is performed.

  (F) In step S400, the semiconductor device is completed through predetermined inspections such as a characteristic inspection relating to performance and function of the semiconductor device, a lead shape / dimension state, and a reliability test. Here, a D / S test, a final test, or the like is performed by the inspection device 5 to acquire electrical characteristics. The acquired electrical characteristics are stored in the characteristic storage unit 22. Then, the cause of the failure is specified by executing the steps S0 to S4 shown in FIG. 16, and the manufacturing apparatuses 31, 32, 33,... The condition is corrected. Subsequent lots are processed by executing the chip manufacturing process in step S300 using the corresponding group of manufacturing apparatuses 31, 32, 33,..., 3n using the corrected manufacturing conditions.

  (G) In step S500, the semiconductor device that has cleared the above process is shipped after being packaged for protection from moisture, static electricity, and the like.

  As described above, according to the manufacturing method of the semiconductor device according to the embodiment of the present invention, since the subsequent lots are manufactured under the corrected manufacturing conditions, the occurrence of defects can be suppressed, and the lot or wafer surface can be controlled. The amount of variation can be reduced. Therefore, the yield can be improved.

  An example of a characteristic map (D / S map) dissimilar to the composite map shown in FIG. 15 is shown in FIGS. “◯” indicates a non-defective product, “Δ” indicates redundancy relief, “■” indicates a DC failure, and “▼” indicates an operation (function) failure.

(Modification)
As a modification of the embodiment of the present invention, an example of forming a composite map expressing the in-plane distribution of the void generation rate at the time of STI embedding in step S25 shown in FIG. 2 will be described.

The single map forming unit 11 extracts the average values of the STI opening width W _Si , STI depth D _STI and taper angle θ for each shot, and expresses the in-plane distributions shown in FIGS. A single map is formed. Further, the variations in the performance of the STI opening width W _Si , the STI depth D _STI and the taper angle θ are extracted, and a single map representing the in-plane distribution is formed as shown in FIGS. The number of measurement points for each shot is, for example, about 100 to 120.

The composite map forming unit 12 generates about 100 to 1000 normal random numbers having the above average value and variation so as to be one set (one sample) with the STI opening width W _Si , the STI depth D _STI , and the taper angle θ. To do. Based on the STI opening width W _Si , the STI depth D _STI , and the taper angle θ, the STI cross-sectional shape is calculated using Equation (3).

  Further, the composite map forming unit 12 parameterizes the characteristics (apparatus QC data) of the STI embedding apparatus, and forms a wafer map expressing the in-plane distribution of the characteristics as shown in FIG. Here, the deposition rate of the insulating film 106 by HDP-CVD is selected as a parameter.

The synthetic map forming unit 12 executes simulation for all samples based on the calculated STI cross-sectional shape and deposition rate, and predicts and predicts the cross-sectional shape when the insulating film 106 is deposited by HDP-CVD. It is determined whether or not there is a void in the cross-sectional shape. The void generation rate is calculated as an index I ₅ by Equation (5), where Sv is the number of void generation samples and Sa is the total number of valid samples.

I ₅ = Sv / Sa (5)
The composite map forming unit 12 forms a composite map representing the in-plane distribution of the index I ₅ as shown in FIG.

The specifying unit 13 compares the composite map shown in FIG. 26 with the D / S data as shown in FIG. If they are similar to each other, the void has an influence on the electrical characteristics, and the lithography process in step S17 and the etching process in step S22 related to the STI opening width W _Si , the STI depth D _STI and the taper angle θ; The corresponding manufacturing device is identified as the cause of failure.

  According to the modification of the embodiment of the present invention, a composite map may be formed by combining three or more single maps. Furthermore, a composite map may be formed in consideration of the device QC data such as the deposition rate, and the cause of the failure can be specified more precisely.

(Other embodiments)
As described above, the present invention has been described according to the embodiment. However, it should not be understood that the description and drawings constituting a part of this disclosure limit the present invention. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.

  For example, a semiconductor device is manufactured using the group of manufacturing apparatuses 31, 32, 33,..., 3 n shown in FIG. 1, the quality is measured using the measuring apparatus 4, and the inspection apparatus 5 is used. Although the electrical characteristics were examined, it is also possible to predict performance and electrical characteristics by simulation. For example, the single map forming unit 11 executes a simulation based on the manufacturing conditions stored in the manufacturing condition storage unit 20 and the device QC data stored in the device QC data storage unit 23, and predicts the performance. A single map may be formed. The characteristic map forming unit 10 may create a characteristic map by executing through simulation and predicting electrical characteristics.

  Further, the composite map shown in FIG. 15 and the characteristic map shown in FIG. 11 are compared. When a single process is specified, for example, a simple map such as each of the single maps shown in FIGS. One single map and the characteristic map may be compared.

  As described above, the present invention naturally includes various embodiments not described herein. Therefore, the technical scope of the present invention is defined only by the invention specifying matters according to the scope of claims reasonable from the above description.

It is a block diagram which shows an example of the defect cause identification system which concerns on embodiment of this invention. It is a flowchart for demonstrating the element isolation formation process which concerns on embodiment of this invention. It is process sectional drawing of the element isolation formation process which concerns on embodiment of this invention. FIG. 5 is a process cross-sectional view subsequent to FIG. 3 of the element isolation formation process according to the embodiment of the present invention. FIG. 5 is a process cross-sectional view subsequent to FIG. 4 of the element isolation formation process according to the embodiment of the present invention. FIG. 6 is a process cross-sectional view subsequent to FIG. 5 of the element isolation formation process according to the embodiment of the present invention. FIG. 7 is a process cross-sectional view subsequent to FIG. 6 of an element isolation formation process according to an embodiment of the present invention. FIG. 8 is a process cross-sectional view subsequent to FIG. 7 of the element isolation formation process according to the embodiment of the present invention. FIG. 9 is a process cross-sectional view subsequent to FIG. 8 of the element isolation formation process according to the embodiment of the present invention. FIG. 10 is a process cross-sectional view subsequent to FIG. 9 of the element isolation formation process according to the embodiment of the present invention. It is the schematic which shows an example of the characteristic map (D / S map) which concerns on embodiment of this invention. It is the schematic which shows an example of the single map expressing the in-plane distribution of the average value of the quality of STI opening width which concerns on embodiment of this invention. It is the schematic which shows an example of the single map expressing the in-plane distribution of the average value of the performance of STI depth which concerns on embodiment of this invention. It is the schematic which shows an example of the single map expressing the in-plane distribution of the average value of the performance of the STI taper angle which concerns on embodiment of this invention. It is the schematic which shows an example of the synthetic | combination map which concerns on embodiment of this invention. It is a flowchart for demonstrating an example of the defect cause identification method which concerns on embodiment of this invention. 6 is a flowchart for explaining an example of a method of manufacturing a semiconductor device according to an embodiment of the present invention. It is the schematic which shows another example of the characteristic map which concerns on embodiment of this invention. It is the schematic which shows another example of the characteristic map which concerns on embodiment of this invention. It is the schematic which shows another example of the characteristic map which concerns on embodiment of this invention. It is the schematic which shows another example of the characteristic map which concerns on embodiment of this invention. It is the schematic which shows an example of the single map expressing the in-plane distribution of the dispersion | variation in the quality of the STI opening width which concerns on the modification of embodiment of this invention. It is the schematic which shows an example of the single map expressing the in-plane distribution of the dispersion | variation in the quality of STI depth which concerns on the modification of embodiment of this invention. It is the schematic which shows an example of the single map expressing the in-plane distribution of the dispersion | variation in the quality of the STI taper angle which concerns on the modification of embodiment of this invention. It is the schematic which shows an example of the wafer map expressing the in-plane distribution of the deposition rate which concerns on the modification of embodiment of this invention. It is the schematic which shows an example of the synthetic | combination map which concerns on the modification of embodiment of this invention. It is the schematic which shows an example of the characteristic map which concerns on the modification of embodiment of this invention.

Explanation of symbols

1. Central processing unit (CPU)
2 ... Data storage device 4 ... Measuring device 5 ... Inspection device 6 ... Main storage device 7 ... Input device 8 ... Output device 9 ... Bus 10 ... Characteristic map formation unit 11 ... Single map formation unit 12 ... Composite map formation unit 13 ... Specific Unit 14 ... Correction unit 20 ... Manufacturing condition storage unit 21 ... Performance storage unit 22 ... Characteristic storage unit 23 ... Device QC data storage unit 24 ... Lot QC data storage unit 25 ... Characteristic map storage unit 26 ... Single map storage unit 27 ... Composition Map storage unit 28 ... Threshold storage unit 29 ... Defect cause storage unit 31, 32, 33, ..., 3n ... Manufacturing apparatus 121 ... Process number determination module 122 ... Selection module 123 ... Composition module

Claims (5)

For a semiconductor device manufactured through a series of steps executed by a group of manufacturing devices,
A characteristic map forming unit for forming a characteristic map representing an in-plane distribution of electrical characteristics of the semiconductor device inspected by the inspection apparatus;
A single map forming unit that forms a single map that expresses the in-plane distribution of the performance of each of the processes measured by the measuring device for each of the processes;
A composite map forming unit that forms a composite map by selecting a plurality of single maps from the single maps for each of the processes;
A failure cause identification system comprising: a identifying unit that identifies the corresponding process as a failure cause by comparing the composite map and the characteristic map. The composite map forming unit forms a plurality of types of the composite map,
The failure cause identifying system according to claim 1, wherein the specifying unit compares the characteristic map with each of the plurality of types of composite maps.   The failure cause identifying system according to claim 1, wherein the composite map forming unit considers apparatus QC data of the manufacturing apparatus. Performing a series of steps for manufacturing a semiconductor device;
Measuring the performance of each of the processes;
Inspecting electrical characteristics of the semiconductor device after the series of steps;
Forming a characteristic map representing an in-plane distribution of the electrical characteristics;
Forming a single map representing the in-plane distribution of the performance for each of the processes;
Selecting a plurality of single maps from the single maps for each of the processes and combining them to form a composite map;
A defect cause identifying method comprising: comparing the composite map with the characteristic map to identify the corresponding process as a defect cause. Performing a series of steps for manufacturing a semiconductor device;
Measuring the performance of each of the processes;
Inspecting electrical characteristics of the semiconductor device after the series of steps;
Forming a characteristic map representing the in-plane distribution of the electrical characteristics, forming a single map representing the in-plane distribution of the performance for each of the processes, and selecting a plurality of maps from the single maps for the respective processes. Identifying the corresponding process as a cause of defect by comparing the composite map and the characteristic map,
Correcting the manufacturing conditions of the process identified as the cause of the defect;
Performing the series of steps using the corrected manufacturing conditions. A method for manufacturing a semiconductor device, comprising:

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