JP2008235623A - Method of flattening semiconductor device and semiconductor device flattening system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of flattening a semiconductor device which can suppress irregularity in a chip while minimizing a quantity of dummy pattern insertion by removing part of a dummy pattern, and also a semiconductor device flattening system. <P>SOLUTION: In the method of flattening a semiconductor device which introduces the dummy pattern as not to electrically function except for grooves formed as wiring with use of a simulation server during manufacture of the semiconductor device, the dummy pattern having a prescribed spacing is introduced in all area other than wiring and other locations where such a pattern as to electrically function is present on design data, and then the dummy pattern on the design data is removed from such a location that a film thickness is predicted to become large after CMP process to manufacture a shadow mask using the design data after the dummy pattern is removed. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a method for planarizing a semiconductor device and a planarization system for a semiconductor device, and more particularly to a technique effective when applied to a planarization method using a dummy pattern.

Conventionally, there have been the following techniques as a method for planarizing a semiconductor device.
(1) Japanese Patent Application Laid-Open No. 2003-32419 (Patent Document 1) describes a method of disposing a dummy pattern over the entire wiring gap of a product chip and then removing it.
(2) Japanese Patent Application Laid-Open No. 2002-342399 (Patent Document 2) describes a method for confirming by simulation whether a step after CMP is within an allowable range.
Japanese Patent Laid-Open No. 2003-32419 JP 2002-342399 A

  However, the method described in Patent Document 1 prepares a dummy pattern in which a large dummy and a small dummy are overlapped, and erases a dummy pattern that overlaps the prohibited area and a small dummy pattern that overlaps the large dummy. The dummy pattern is arranged in the entire wiring gap of the product chip, and is not a method of deleting the dummy pattern using simulation. For this reason, it is not always possible to delete the dummy pattern only at an appropriate location, and there is a concern that the flatness is deteriorated.

  In the method described in Patent Document 2, the surface level difference of the polished surface is evaluated using simulation, the pattern density is determined based on the evaluation result, and the dummy pattern is within the dummy pattern allowable region so as to be the pattern density. Although the pattern is arranged and the simulation is used, it is only for confirming whether or not the surface step is at the specified value, and does not lead to improvement of flatness.

  Accordingly, an object of the present invention is to provide a semiconductor device flattening method capable of minimizing the amount of dummy pattern insertion and suppressing unevenness in a chip by deleting a part of the dummy pattern using simulation. An object of the present invention is to provide a planarization system for a semiconductor device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  According to the planarization method of a semiconductor device according to the present invention, a plating film is formed on a groove formed on a substrate surface, the groove is embedded with a plating film, and a plating film deposited on a portion other than the groove is removed by performing a CMP process. A method of planarizing a semiconductor device that introduces a dummy pattern that does not function electrically other than a groove formed as a wiring in the manufacture of a semiconductor device that forms a wiring, and the dummy pattern is designed using a simulation server In the design data from the place where the film thickness after the CMP process is expected to increase after being introduced into the entire area except for the place where wiring or other electrically functioning patterns exist on the data, The dummy mask is deleted, and the shadow mask is manufactured using the design data after the dummy pattern is deleted.

  The planarization method for a semiconductor device according to the present invention includes forming a plating film on a groove formed on a substrate surface, filling the groove with a plating film, and performing a CMP process to deposit a plating film deposited on a portion other than the groove. A method of planarizing a semiconductor device that introduces a dummy pattern that does not function electrically other than a groove formed as a wiring in the manufacture of a semiconductor device to be removed to form a wiring. The process of extracting the characteristics of the accumulated design data of the semiconductor device, and based on the extracted data, specified in all areas other than the place where the wiring or other electrically functioning pattern exists on the design data. The process of placing dummy patterns at intervals and the simulation of the plating film thickness in the design data where the dummy patterns are placed A step of performing a simulation of a film thickness after polishing by the CMP process based on a simulation result of the thickness of the plating film and a CMP process condition, and a dummy based on the simulation result of the film thickness after polishing. The process of specifying the area from which the pattern is deleted, the process of deleting the dummy pattern in the specified area from the dummy pattern placed on the design data, and the design data from which the dummy pattern has been deleted as design data for creating mask data And a step of accumulating in the design data server.

  The planarization system for a semiconductor device according to the present invention forms a plating film on a groove formed on the substrate surface, fills the groove with a plating film, and performs a CMP process to deposit a plating film deposited on a portion other than the groove. A semiconductor device planarization system that introduces a dummy pattern that does not function electrically other than a trench formed as a wiring in the manufacture of a semiconductor device that is removed and forms wiring, and the design data of the semiconductor device is accumulated A design data server; and a simulation server for executing a simulation based on the design data stored in the design data server, the simulation server extracting means for extracting design data features of the semiconductor device stored in the design data server; Based on the extracted data, wiring or other electrical functions on the design data Means for arranging dummy patterns at specified intervals in all areas other than the place where the pattern to be present exists, means for executing a simulation of the thickness of the plating film in the design data in which the dummy pattern is arranged, and the thickness of the plating film Means for executing simulation of film thickness after polishing by CMP process based on the simulation result of the thickness and CMP process conditions, and means for designating a region for deleting the dummy pattern based on simulation result of film thickness after polishing And means for deleting the dummy pattern in the designated area from the dummy pattern arranged on the design data, and means for storing the design data from which the dummy pattern has been deleted in the design data server as design data for creating mask data It has.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  According to the present invention, it is possible to suppress the unevenness in the chip while minimizing the insertion amount of the dummy pattern, and it is possible to reduce both the wiring delay and the defect.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

(Embodiment 1)
A planarization method for a semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS. The semiconductor device planarization method according to the first embodiment of the present invention is realized by, for example, a semiconductor device planarization system (FIG. 8) described later.

  FIG. 1 is a cross-sectional view showing a device pattern for explaining a planarization method for a semiconductor device according to the first embodiment of the present invention, and FIG. 2 explains a planarization method for the semiconductor device according to the first embodiment of the present invention. FIG. 3 is a diagram showing an example of dummy pattern placement for the purpose, and FIG. 3 is a diagram showing a Cu convex shape on the groove pattern at the stage where plating is completed for explaining the planarization method of the semiconductor device according to the first embodiment of the present invention. 4 is a diagram showing the correlation between the width of the groove pattern and the height of the convex shape formed on the groove pattern for explaining the planarization method of the semiconductor device according to the first embodiment of the present invention, and FIG. FIG. 6 is a flow chart showing the procedure of the semiconductor device planarization method according to the first embodiment of the present invention. FIG. 6 is a schematic diagram for explaining the removal of the dummy pattern in the semiconductor device planarization method according to the first embodiment of the present invention. FIG.

  First, an outline of the damascene method, which is a wiring formation method using the CMP method, will be described. First, after a groove is formed by etching on a Si substrate, Cu is deposited by a plating method, and plating is continued until the substrate is covered. At this stage, the plating layer is ideally required to fill all the grooves present on the device.

  For this reason, the Cu plating layer is formed not only in the groove shape but also in the groove-free portion as shown in FIG. In this state, the Cu between the grooves is in a conductive state and cannot be used as a wiring. Therefore, the Cu plating layer is polished by a CMP process, and each groove is electrically connected as shown in FIG. Keep insulated. The above is the outline of the damascene method.

  When the damascene method is performed on a chip in which only the wiring is patterned at the stage where the LSI design has been completed, unevenness variation in the chip becomes severe, and dishing (Cu film can be scraped on the plate) defects and erosion (underlayer is excessive) (Polished) may occur. Therefore, means for improving the flatness by introducing a “dummy pattern” that does not intentionally function electrically at the time of LSI design is used.

  FIG. 2 shows an example of dummy pattern installation. In general, the dummy pattern is a square pattern of about 1 μm or smaller, and is installed in a vacant space without wiring with a space of about 0.5 μm to 1 μm between the dummy patterns. According to our original study, the effect of improving the flatness of the dummy pattern is as described below.

  As shown in FIGS. 3A and 3B, the height of the Cu convex shape on the groove pattern varies depending on the fine density of the groove pattern such as a fine groove and a wide groove when the plating is completed. According to our own study, as shown in FIG. 4, it is clear that there is a correlation between the width of the groove pattern and the height of the convex shape formed on the groove pattern.

  Therefore, if a finer dummy pattern is arranged, the convex shape of the upper part becomes higher. The wiring pattern of an LSI chip often includes a pattern having a width of 1 μm or more and Cu in the upper part of the groove having a concave shape. Therefore, if a dummy pattern is arranged around these thick wirings, it can be expected that the convex shape of the dummy pattern and the concave shape of the wiring part are offset during CMP and become flat.

  However, on the other hand, in an actual chip with complicated patterns, it is often difficult to judge whether or not it is necessary to simply fill the periphery of a wiring having a width of 1 μm or more with a dummy pattern. Therefore, in many of the conventional cases, a dummy pattern is often entirely inserted in a portion where no chip wiring exists as in Patent Documents 1 and 2 described above.

  When a large number of dummy patterns are inserted in this manner, the dummy pattern functions as a floating electrode, so that the capacitance between the wirings increases, which may cause a chip operation to be delayed due to a so-called RC delay.

  From the above, in the present embodiment, flatness is maintained while reducing the amount of dummy patterns introduced using the procedure shown in the flowchart of FIG. Hereinafter, the procedure shown in the flowchart of FIG. 5 will be described. Each procedure is realized by a semiconductor device planarization system (FIG. 8) described later.

  (S1) As soon as the wiring design data for the chip is completed, it is obtained. As for the means to obtain, it is desirable that the labor saving means by automation is introduced.

  (S2) Next, a dummy pattern is inserted into all empty areas of the chip wiring design data obtained in S1. Here, the shape of the dummy pattern is a square of 0.5 μm square, and the interval is also 0.5 μm. In particular, it is not necessary to enter the area where introduction of wiring is prohibited in wiring design.

(S3) Next, the Cu surface height in the chip after plating is calculated. The calculation method is as follows. The chip is divided into meshes (preferably about 10 μm if possible), the average value of the groove width is calculated from the total wiring length in each mesh, and is calculated by comparing with the data shown in FIG. 4 (S4). The CMP simulation is executed using the data calculated in step 1 and the process data. Simulation techniques have been studied in many institutions so far. Tugbawa, T .; Park, D.C. Boning, T. Pan, P.M. Li, S.M. Hymes, T .; Brown, and L.L. Camilletti, “A Material Model of Pattern Dependencies in Cu CMP Processes”, CMP Symposium, Electrochemical Society Meeting, Vol. PV99-37, pp. 605-615, Honolul, HA, Oct. 1999. Etc. are announced.

  In the CMP simulation method, the film thickness distribution in the chip can be calculated with respect to the polishing time and the polishing amount. In many cases, the process conditions are determined by the polishing time or the polishing amount, and this value is input to the simulator. Thereby, the height distribution after polishing can be obtained as an output. Other necessary simulation parameters include the pad pressure during CMP polishing, the Young's modulus of the polishing pad, and the dependency of the polishing rate on the polishing pressure.

  (S5) Next, the position of a particularly high portion (hereinafter referred to as “high region”) is extracted from the height distribution obtained in S4. Although several extraction methods are conceivable, in this embodiment, when the lowest height is A [nm] and the highest height is B [nm], the height is equal to or less than B [nm] and A−N. Extract a region that is greater than or equal to B [nm]. At this time, in this embodiment, N = 0.10, but it is desirable to find the most optimal value by repeating trial and error.

  Our experience shows that in many cases the optimum value is between N = 0.02 and 0.30.

  As a result, other dummy patterns can be deleted while leaving only the minimum dummy pattern necessary for flattening, and both reduction of wiring delay and securing of flatness can be achieved.

  (S6) FIG. 6 shows a schematic diagram of the high region extracted in S5. The design data of the dummy pattern existing in this high area is removed, and new design data is generated. In many cases, the design data is created in a format called GDSII format, and the GDSII format is also used in this embodiment.

  (S7) A shadow mask is created from the GDSII format design data created in S6. This makes it possible to manufacture a product that maintains flatness while reducing the amount of dummy patterns.

  When the above procedure is applied to a 10 mm square 0.13 μm process rule chip, the number of dummy patterns can be reduced by 20% or more, and the flatness can be improved by about 10%. It was revealed.

  As described above, in the present embodiment, the amount of dummy patterns can be reduced while maintaining or improving flatness. Moreover, the prospect that RC delay resulting from an electrostatic capacitance could also be reduced by reducing a dummy pattern was obtained.

  As a result, the shape after polishing with high flatness can be formed easily and at high speed, and the existence density of dummy patterns existing around the wiring can be suppressed, so that the electrical signal delay due to the capacitance between the wiring and the dummy pattern is suppressed. It becomes possible to do.

  In addition, since the simulation is used, it is possible to create a pattern at a design stage before manufacturing, with higher quantitativeness.

(Embodiment 2)
Although the procedure for removing the dummy pattern has been described with reference to FIG. 5 in the first embodiment, the procedure as shown in FIG. 7 may be used. FIG. 7 is a flowchart showing a procedure of a method for planarizing a semiconductor device according to the second embodiment of the present invention. In the procedure of FIG. 7, the procedures of S8 and S9 are added to the procedure of FIG. Hereinafter, the procedure shown in the flowchart of FIG. 7 will be described.

  In FIG. 7, the procedures of S1 to S7 are the same as those of the first embodiment shown in FIG. 5, and here, the procedures of S8 and S9 added in the present embodiment will be described.

  (S8) S6 It is calculated how much the uneven distribution (height maximum value-minimum value) is improved by the data obtained by removing the created dummy pattern.

  (S9) Next, it is determined whether (height maximum value−minimum value) has reached an extreme value (that is, the minimum value) based on the data calculated in S8.

  The reason that such a determination is necessary is that there is a high possibility that the dummy pattern amount is not reduced to the optimum amount by removing the dummy pattern once. Therefore, when the extreme value has not been reached, the process returns to the step (S6) of further removing the dummy pattern.

  This is repeated until (maximum height-minimum value) reaches an extreme value. If the dummy pattern is removed after passing the extreme value, irregularities increase on the contrary, so that it is always stopped when the extreme value is reached. It was found that by such a procedure, the dummy pattern that can be removed is 30% or more, and the flatness can be improved by about 15%.

  As described above, according to the present embodiment, it is possible to further increase the flatness and reduce the dummy pattern introduction amount. In addition, it is considered that the RC delay due to the capacitance can be further reduced by reducing the dummy pattern amount.

  In the first and second embodiments, the shape of the dummy pattern is 0.5 μm square and the interval between the dummy patterns is 0.5 μm, but it may be a rectangle or a square having a short side of 1 μm or less.

  As is apparent from the figure showing the rise of the convex shape shown in FIG. 4, when the size of the dummy pattern is 1 μm or less in width, the dummy pattern rises, thereby affecting the influence of the concave wiring. This is because they can be offset. Further, the distance between the respective dummy patterns may be 0.05 μm to 1 μm. In this way, when the shape of the dummy pattern is changed, there is a possibility that the optimum value of the value of N at the time of optimization may change, so it is necessary to search for the optimum value.

  In particular, in the Cu plating method, a phenomenon is known in which a film thickness is particularly increased in an upper part of a region in which a narrow pattern is dense after plating. Therefore, by introducing a fine pattern such as a dummy pattern in an area where the film thickness is relatively low, the film thickness in that area can be increased. On the other hand, in the region where the film thickness is increased, the dummy pattern is removed by the method described above, so that thickening of the film thickness can be prevented. Aiming at obtaining such an effect, it is possible to obtain a flat film thickness distribution as a whole by adopting a fine dummy pattern (for example, short side 0.05 μm to 1 μm, interval 0.05 to 1 μm). It becomes.

Further, in the first and second embodiments, the substrate is Si, although the plating film was Cu, the substrate is Si, SiO _2, SiO ₂ containing carbon, a SiO ₂ or combinations thereof containing fluorine, plating film May be Cu, Ni, Co, Ru, or an alloy or laminated film thereof. As a result, it is possible to maintain and improve the flatness and reduce the wiring delay corresponding to various plating films and bases.

(Embodiment 3)
Next, the configuration and operation of the planarization system for a semiconductor device according to the third embodiment of the present invention will be described with reference to FIG. FIG. 8 is a configuration diagram showing a configuration of a planarization system for a semiconductor device according to the third embodiment of the present invention.

  In FIG. 8, the semiconductor device planarization system includes signal lines 101 to 105, a design data server 130, a terminal device 131, a process / simulation data server 132, and a simulation computer cluster 134. The process / simulation data server 132 and the simulation computer cluster 134 constitute a simulation server.

  The design data server 130 stores design data from the latest product to an old product, and the design data is supplied to the process / simulation data server 132 through the signal line 102.

  The process / simulation data server 132 stores process information (particularly related to CMP, pad-related parameters, polishing rate data, etc.) from the latest to old products, and also stores parameters necessary for simulation. ing.

  Furthermore, the latest parameters can be obtained from the signal line 104 connected to the external network as necessary.

  A dummy pattern optimization command is issued from the terminal device 131, and the command is interpreted by the process / simulation data server 132 through the signal line 101. The process / simulation data server 132 extracts features of the design data of the semiconductor device, collects the extracted data and information necessary for the simulation such as information on the CMP process conditions, and sends them to the simulation computer cluster 134 through the signal line 103. Then, the procedure described in the second embodiment is executed.

  As soon as this execution is completed, the design data with the dummy pattern reduced is transmitted to the design data server 130 through the signal lines 103 and 102. The design data from which the dummy patterns are reduced is further supplied to the mask manufacturing department through the signal line 105 as necessary.

  The semiconductor device flattening system as described above enables systematic and automatic optimum dummy pattern insertion, enabling almost all operations related to dummy pattern insertion and deletion to be performed in a short time. It is possible to mask the design data in which is inserted / deleted, and the dummy design TAT can be reduced. In addition, wiring delay can be reduced while maintaining the flatness of the film thickness distribution.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention relates to a method for planarizing a semiconductor device and a planarization system for a semiconductor device, and can be widely applied to devices and systems that use a dummy pattern for planarization.

(A), (b) is sectional drawing which shows the device pattern for demonstrating the planarization method of the semiconductor device which concerns on Embodiment 1 of this invention. It is a figure which shows the example of dummy pattern installation for demonstrating the planarization method of the semiconductor device which concerns on Embodiment 1 of this invention. (A), (b) is a figure which shows Cu convex shape on the groove | channel pattern of the stage where the plating for demonstrating the planarization method of the semiconductor device which concerns on Embodiment 1 of this invention was complete | finished. It is a figure which shows the correlation of the width of the groove pattern for demonstrating the planarization method of the semiconductor device which concerns on Embodiment 1 of this invention, and the height of the convex shape formed on a groove pattern. It is a flowchart which shows the procedure of the planarization method of the semiconductor device which concerns on Embodiment 1 of this invention. It is a schematic diagram for demonstrating the removal of the dummy pattern of the planarization method of the semiconductor device which concerns on Embodiment 1 of this invention. It is a flowchart which shows the procedure of the planarization method of the semiconductor device which concerns on Embodiment 2 of this invention. It is a block diagram which shows the structure of the planarization system of the semiconductor device which concerns on Embodiment 3 of this invention.

Explanation of symbols

  101-105 ... signal lines, 130 ... design data server, 131 ... terminal device, 132 ... process / simulation data server, 134 ... computer cluster for simulation.

Claims (9)

A semiconductor in which a plating film is formed on a groove formed on a substrate surface, the groove is filled with the plating film, and a CMP process is performed to remove the plating film deposited on a portion other than the groove to form a wiring. In the manufacture of a device, a method for planarizing a semiconductor device that introduces a dummy pattern that does not function electrically other than the groove formed as the wiring,
Using a simulation server, the dummy pattern is introduced into the design data at all intervals other than the place where the wiring or other electrically functioning pattern exists, and then after the CMP process. A method for planarizing a semiconductor device, comprising: deleting a dummy pattern on the design data from a place where the film thickness is predicted to be thick, and manufacturing a shadow mask using the design data after the dummy pattern is deleted . The method for planarizing a semiconductor device according to claim 1,
Flatness of a semiconductor device, wherein simulation is used to predict a portion where the film thickness is thick, and the design data is generated by removing the dummy pattern from a portion where the film thickness is thick based on a result of the simulation Method. The method for planarizing a semiconductor device according to claim 2,
The portion where the film thickness is increased is defined as B-A.N (where N is a real number between 0 and 1) [nm] where A [nm] is the lowest film thickness and B [nm] is the highest film thickness. ] To B [nm]. A method for planarizing a semiconductor device, wherein: In the planarization method of the semiconductor device according to claim 3,
A method of planarizing a semiconductor device, wherein the value of N is 0.02 to 0.30. In the planarization method of the semiconductor device according to claim 3,
A method of planarizing a semiconductor device, wherein the value of N is 0.10. The method for planarizing a semiconductor device according to claim 1,
A planarization method of a semiconductor device, wherein the dummy pattern has a rectangular or square shape with a short side of 1 μm or less, and a distance between the dummy patterns is 0.05 μm to 1 μm. The method for planarizing a semiconductor device according to claim 1,
Said substrate is Si, SiO _2, SiO ₂ containing carbon, a SiO ₂ or a combination thereof, including fluorine,
A method of planarizing a semiconductor device, wherein the plating film is Cu, Ni, Co, Ru, an alloy thereof, or a laminated film. A semiconductor in which a plating film is formed on a groove formed on a substrate surface, the groove is filled with the plating film, and a CMP process is performed to remove the plating film deposited on a portion other than the groove to form a wiring. In the manufacture of a device, a method for planarizing a semiconductor device that introduces a dummy pattern that does not function electrically other than the groove formed as the wiring,
The simulation server
Extracting the characteristics of the design data of the semiconductor device accumulated in the design data server;
Based on the extracted data, placing dummy patterns at specified intervals in all areas other than where the wiring or other electrically functioning pattern exists on the design data;
Performing a simulation of the thickness of the plating film in the design data in which the dummy pattern is disposed;
Executing a simulation of the film thickness after polishing by the CMP process based on the simulation result of the thickness of the plating film and the CMP process conditions;
Based on the simulation result of the film thickness after polishing, a step of designating a region to delete the dummy pattern;
Deleting the dummy pattern of the specified area from the dummy pattern arranged on the design data;
And a step of storing the design data from which the dummy pattern has been deleted as design data for creating mask data in the design data server. A semiconductor in which a plating film is formed on a groove formed on a substrate surface, the groove is filled with the plating film, and a CMP process is performed to remove the plating film deposited on a portion other than the groove to form a wiring. In the manufacture of a device, a semiconductor device planarization system for introducing a dummy pattern that does not function electrically other than the groove formed as the wiring,
A design data server storing design data of the semiconductor device;
A simulation server for executing a simulation based on the design data stored in the design data server,
The simulation server
Means for extracting features of the design data of the semiconductor device stored in the design data server;
Based on the extracted data, means for arranging dummy patterns at specified intervals in all areas other than the place where the wiring or other electrically functioning pattern exists on the design data;
Means for executing a simulation of the thickness of the plating film in the design data in which the dummy pattern is arranged;
Means for performing a simulation of the film thickness after polishing by the CMP process based on the simulation result of the thickness of the plating film and the CMP process conditions;
Based on the simulation result of the film thickness after polishing, means for designating a region to delete the dummy pattern;
Means for deleting the dummy pattern of the designated area from the dummy pattern arranged on the design data;
A planarization system for a semiconductor device, comprising: means for storing, in the design data server, design data from which the dummy pattern has been deleted as design data for creating mask data.

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