CN112291933A - Compensation method for keeping impedance continuity of routing layer - Google Patents
Compensation method for keeping impedance continuity of routing layer Download PDFInfo
- Publication number
- CN112291933A CN112291933A CN202011080174.5A CN202011080174A CN112291933A CN 112291933 A CN112291933 A CN 112291933A CN 202011080174 A CN202011080174 A CN 202011080174A CN 112291933 A CN112291933 A CN 112291933A
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- China
- Prior art keywords
- compensation
- shaped groove
- section
- area
- isosceles triangle
- Prior art date
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- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 25
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 7
- 239000011889 copper foil Substances 0.000 claims abstract description 7
- 238000004088 simulation Methods 0.000 claims abstract description 6
- 239000010410 layer Substances 0.000 description 22
- 238000010586 diagram Methods 0.000 description 5
- 238000006467 substitution reaction Methods 0.000 description 3
- 230000000052 comparative effect Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0005—Apparatus or processes for manufacturing printed circuits for designing circuits by computer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0237—High frequency adaptations
- H05K1/025—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0002—Apparatus or processes for manufacturing printed circuits for manufacturing artworks for printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/07—Electric details
- H05K2201/0776—Resistance and impedance
- H05K2201/0784—Uniform resistance, i.e. equalizing the resistance of a number of conductors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Structure Of Printed Boards (AREA)
Abstract
The invention provides a compensation method for keeping impedance continuity of a routing layer, which comprises the following steps: creating a compensation section on a wiring layer needing compensation, and calculating the area of the compensation section; adding a V-shaped groove on the compensation layer surface, wherein the area of the cross section of the V-shaped groove is equal to that of the compensation section; filling copper foil in the V-shaped groove; and setting simulation comparison before and after compensation, and detecting impedance continuity before and after compensation. According to the invention, the impedance continuity of the wiring is maintained by adding the V-shaped groove on the wiring layer and compensating the wiring line width in a three-dimensional manner.
Description
Technical Field
The invention belongs to the technical field of printed circuit board design, and particularly relates to a compensation method for keeping impedance continuity of a wiring layer.
Background
In printed circuit board designs, BGA packaged chips are often used. When the pin pitch of the BGA chip is less than or equal to 0.5mm, the line width of the outgoing pin wiring is changed from thin to thick, so that wiring impedance in a BGA area is discontinuous, in the prior art, the line width length of the wiring to be compensated can be shortened as far as possible, the length of the discontinuous impedance is shortened as far as possible, and the impedance discontinuity cannot be completely avoided.
Disclosure of Invention
In view of the above-mentioned deficiencies of the prior art, the present invention provides a compensation method for maintaining impedance continuity of a trace plane, so as to solve the above-mentioned technical problem.
In a first aspect, the present invention provides a compensation method for maintaining impedance continuity in a trace plane, including:
creating a compensation section on a wiring layer needing compensation, and calculating the area of the compensation section;
adding a V-shaped groove on the compensation layer surface, wherein the area of the cross section of the V-shaped groove is equal to that of the compensation section;
filling copper foil in the V-shaped groove;
and setting simulation comparison before and after compensation, and detecting impedance continuity before and after compensation.
Further, the method further comprises:
the cross section of the V-shaped groove is in an isosceles triangle shape;
the bottom of the isosceles triangle is the length of the V-shaped groove;
the height of the isosceles triangle is the depth of the V-shaped groove.
Further, the method further comprises:
measuring the layer thickness of a layer surface needing to be compensated for routing, and taking the layer thickness and the actual line width as a rectangular cross section which is taken as a compensation section;
and calculating the product of the layer thickness and the line width to obtain the area of the compensation section.
Further, the method further comprises:
the area of the cross section of the V-shaped groove is the area of an isosceles triangle;
calculating a relation of height of the isosceles triangle according to the area of the isosceles triangle;
and determining the length and the depth of the V-shaped groove according to the relational expression.
The beneficial effect of the invention is that,
according to the compensation method for keeping impedance continuity of the wiring layer, the impedance continuity of the wiring is kept in a mode of adding the V-shaped groove on the wiring layer and compensating the wiring line width in a three-dimensional mode.
In addition, the invention has reliable design principle, simple structure and very wide application prospect.
Drawings
In order to more clearly illustrate the embodiments or technical solutions in the prior art of the present invention, the drawings used in the description of the embodiments or prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without creative efforts.
FIG. 1 is a schematic flow diagram of a method of one embodiment of the invention.
FIG. 2 is a schematic illustration of a compensated cross-section of one embodiment of the present invention.
FIG. 3 is a cross-sectional area variation diagram of one embodiment of the present invention.
Fig. 4 is a simulation comparison diagram provided in the embodiment of the present invention.
FIG. 5 is a comparative illustration of a stack according to an embodiment of the present invention
Detailed Description
In order to make those skilled in the art better understand the technical solution of the present invention, the technical solution in the embodiment of the present invention will be clearly and completely described below with reference to the drawings in the embodiment of the present invention, and it is obvious that the described embodiment is only a part of the embodiment of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
FIG. 1 is a schematic flow diagram of a method of one embodiment of the invention. As shown in fig. 1, the method includes:
Optionally, as an embodiment of the present invention, the method further includes:
the cross section of the V-shaped groove is in an isosceles triangle shape;
the bottom of the isosceles triangle is the length of the V-shaped groove;
the height of the isosceles triangle is the depth of the V-shaped groove.
Optionally, as an embodiment of the present invention, the method further includes:
measuring the layer thickness of a layer surface needing to be compensated for routing, and taking the layer thickness and the actual line width as a rectangular cross section which is taken as a compensation section;
and calculating the product of the layer thickness and the line width to obtain the area of the compensation section.
Optionally, as an embodiment of the present invention, the method further includes:
the area of the cross section of the V-shaped groove is the area of an isosceles triangle;
calculating a relation of height of the isosceles triangle according to the area of the isosceles triangle;
and determining the length and the depth of the V-shaped groove according to the relational expression.
In order to facilitate understanding of the present invention, the following further describes a compensation method for maintaining impedance continuity at a trace level according to the principles of the present invention.
Specifically, the compensation method for maintaining the impedance continuity of the routing plane includes:
1. as shown in fig. 2, 1, for example, to ensure that the trace impedance of the L3 layer of the area where the BGA is located is continuous, the line width meeting the requirement of 50ohm impedance is 3.8 mil, the breakout line width is 3.1 mil, a V-shaped groove (isosceles triangle) is added on the trace layer, copper foil is filled in the groove, and the trace impedance of the BGA area is continuous by means of three-dimensional compensation of the trace line width.
2. Under the conditions that the copper foils have the same density and the three-dimensional compensation has the same trace length, a is the breakout line width, b is the normal line width, H is the thickness of the layer to be compensated, H is the depth of the V-shaped groove, and H is 0.5H a, so that the depth of the V-shaped groove per unit area is 2H b/a.
3. As shown in the comparative lamination diagram of fig. 5, when the thickness of the layer L3 to be compensated is 1.2mi, the V-shaped groove has a depth H2H b/a 2H 1.2 x 3.8/3.1H 2.94mi, and the isosceles triangular groove having a base length of 3.1mi and a height of 2.94mi is filled with copper foil, so that the trace impedance of the layer L3 in the BGA area is continuous by compensating the trace line width in a three-dimensional manner.
4. The compensation mode is not limited to the surface layer where the BGA chip is located, and is also suitable for inner-layer routing.
5. After simulation, for example, as shown in fig. 4, it can be seen that the impedance before compensation has jump; the impedance after compensation tends to be stable, and the impedance continuity is obviously improved.
Although the present invention has been described in detail by referring to the drawings in connection with the preferred embodiments, the present invention is not limited thereto. Various equivalent modifications or substitutions can be made on the embodiments of the present invention by those skilled in the art without departing from the spirit and scope of the present invention, and these modifications or substitutions are within the scope of the present invention/any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (4)
1. A compensation method for keeping impedance continuity of a routing layer is characterized by comprising the following steps:
creating a compensation section on a wiring layer needing compensation, and calculating the area of the compensation section;
adding a V-shaped groove on the compensation layer surface, wherein the area of the cross section of the V-shaped groove is equal to that of the compensation section;
filling copper foil in the V-shaped groove;
and setting simulation comparison before and after compensation, and detecting impedance continuity before and after compensation.
2. A compensation method for maintaining the continuity of the trace plane impedance according to claim 1, wherein the method further comprises:
the cross section of the V-shaped groove is in an isosceles triangle shape;
the bottom of the isosceles triangle is the length of the V-shaped groove;
the height of the isosceles triangle is the depth of the V-shaped groove.
3. A compensation method for maintaining the continuity of the trace plane impedance according to claim 1, wherein the method further comprises:
measuring the layer thickness of a layer surface needing to be compensated for routing, and taking the layer thickness and the actual line width as a rectangular cross section which is taken as a compensation section;
and calculating the product of the layer thickness and the line width to obtain the area of the compensation section.
4. A compensation method for maintaining the continuity of the trace level impedance according to claim 2, wherein the method further comprises:
the area of the cross section of the V-shaped groove is the area of an isosceles triangle;
calculating a relation of height of the isosceles triangle according to the area of the isosceles triangle;
and determining the length and the depth of the V-shaped groove according to the relational expression.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011080174.5A CN112291933A (en) | 2020-10-10 | 2020-10-10 | Compensation method for keeping impedance continuity of routing layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011080174.5A CN112291933A (en) | 2020-10-10 | 2020-10-10 | Compensation method for keeping impedance continuity of routing layer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN112291933A true CN112291933A (en) | 2021-01-29 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011080174.5A Pending CN112291933A (en) | 2020-10-10 | 2020-10-10 | Compensation method for keeping impedance continuity of routing layer |
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| Country | Link |
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| CN (1) | CN112291933A (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100643408B1 (en) * | 2005-10-10 | 2006-11-10 | 삼성전자주식회사 | Printed circuit board |
| CN103944006A (en) * | 2013-01-18 | 2014-07-23 | 莫列斯公司 | Improved cable assembly and circuit board |
| CN104582290A (en) * | 2015-01-30 | 2015-04-29 | 浪潮电子信息产业股份有限公司 | Method for realizing high-speed line impedance continuity |
| CN109831869A (en) * | 2019-02-25 | 2019-05-31 | 维沃移动通信有限公司 | A kind of paster technique, pcb board and mobile terminal |
| US10485096B2 (en) * | 2017-11-29 | 2019-11-19 | Dell Products L.P. | Differential trace pair system |
| CN111132449A (en) * | 2020-01-02 | 2020-05-08 | 成都理工大学 | Ball grid array package PCB substrate and impedance matching method thereof |
-
2020
- 2020-10-10 CN CN202011080174.5A patent/CN112291933A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100643408B1 (en) * | 2005-10-10 | 2006-11-10 | 삼성전자주식회사 | Printed circuit board |
| CN103944006A (en) * | 2013-01-18 | 2014-07-23 | 莫列斯公司 | Improved cable assembly and circuit board |
| CN104582290A (en) * | 2015-01-30 | 2015-04-29 | 浪潮电子信息产业股份有限公司 | Method for realizing high-speed line impedance continuity |
| US10485096B2 (en) * | 2017-11-29 | 2019-11-19 | Dell Products L.P. | Differential trace pair system |
| CN109831869A (en) * | 2019-02-25 | 2019-05-31 | 维沃移动通信有限公司 | A kind of paster technique, pcb board and mobile terminal |
| CN111132449A (en) * | 2020-01-02 | 2020-05-08 | 成都理工大学 | Ball grid array package PCB substrate and impedance matching method thereof |
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Application publication date: 20210129 |
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| RJ01 | Rejection of invention patent application after publication |