CN112289903B - Light emitting diode chip and manufacturing method thereof - Google Patents
Light emitting diode chip and manufacturing method thereof Download PDFInfo
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- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/16—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous
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- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
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- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
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- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/14—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
- H01L33/145—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure with a current-blocking structure
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- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/20—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
Abstract
The present disclosure provides a light emitting diode chip and a manufacturing method thereof, which belongs to the technical field of semiconductors, wherein the light emitting diode chip comprises a substrate, an N-type semiconductor layer, an active layer, a P-type semiconductor layer, an N-type electrode, a P-type electrode and a distributed Bragg reflector; the N-type semiconductor layer, the active layer and the P-type semiconductor layer are sequentially stacked on the first surface of the substrate; a groove extending to the N-type semiconductor layer is formed in the P-type semiconductor layer, the N-type electrode is arranged on the N-type semiconductor layer in the groove, and the P-type electrode is arranged on the P-type semiconductor layer; the distributed Bragg reflector is paved on a second surface of the substrate, wherein the second surface is the opposite surface of the first surface; and part of the edge area of the N-type semiconductor layer is a light scattering structure, and the light scattering structure is formed by a crystal structure with crystal defects. The LED light source is beneficial to improving the front light emitting efficiency of the LED.
Description
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a light emitting diode chip and a method for manufacturing the same.
Background
An LED (Light Emitting Diode) is a semiconductor device capable of Emitting Light. The LED has the advantages of low voltage, low power consumption, small volume, light weight, long service life, high reliability and the like, and is rapidly and widely applied to the fields of traffic signal lamps, automobile interior and exterior lamps, urban landscape lighting, mobile phone backlight sources, outdoor full-color display screens and the like. With the gradual change and the wide application field of the LED, the performance requirements of the market on the LED are continuously improved, particularly the luminous brightness of the LED.
The chip is the core device of the LED. In the related art, the LED chip includes a substrate, an N-type semiconductor layer, an active layer, a P-type semiconductor layer, an N-type electrode, a P-type electrode, and a DBR (Distributed Bragg reflector). The N-type semiconductor layer, the active layer and the P-type semiconductor layer are sequentially stacked on the first surface of the substrate, and a groove extending to the N-type semiconductor layer is formed in the P-type semiconductor layer. The N-type electrode is arranged on the N-type semiconductor layer in the groove, and the P-type electrode is arranged on the P-type semiconductor layer. The DBR is disposed on a second surface of the substrate, the second surface being an opposite surface of the first surface.
The N-type electrode and the P-type electrode inject current, and electrons provided by the N-type semiconductor layer and holes provided by the P-type semiconductor layer migrate into the active layer to be recombined to emit light. The light emitted from the active layer is emitted in all directions, but the LED application can only use the light emitted from the front surface of the chip (i.e. the side where the P-type electrode is located). In the related art, the DBR is used for reflecting light rays emitted to the back surface of the chip (namely the side where the DBR is located), the reflection effect is limited, and the front light emitting efficiency of the LED still needs to be improved.
Disclosure of Invention
The embodiment of the disclosure provides a light emitting diode chip and a manufacturing method thereof, which are beneficial to improving the front light emitting efficiency of an LED. The technical scheme is as follows:
in one aspect, an embodiment of the present disclosure provides a light emitting diode chip, where the light emitting diode chip includes a substrate, an N-type semiconductor layer, an active layer, a P-type semiconductor layer, an N-type electrode, a P-type electrode, and a distributed bragg reflector; the N-type semiconductor layer, the active layer and the P-type semiconductor layer are sequentially stacked on the first surface of the substrate; a groove extending to the N-type semiconductor layer is formed in the P-type semiconductor layer, the N-type electrode is arranged on the N-type semiconductor layer in the groove, and the P-type electrode is arranged on the P-type semiconductor layer; the distributed Bragg reflector is paved on a second surface of the substrate, wherein the second surface is the opposite surface of the first surface; and part of the edge area of the N-type semiconductor layer is a light scattering structure, and the light scattering structure is formed by a crystal structure with crystal defects.
Optionally, the crystal defects within the light scattering structure gradually decrease in a direction from the substrate to the active layer.
Optionally, the light scattering structure is spaced apart from the active layer.
Optionally, the light emitting diode chip further includes a current blocking layer and a transparent conductive layer, where the current blocking layer includes a first sub-layer, a second sub-layer and a third sub-layer; the first sublayer is arranged between the edge area of the P-type electrode and the P-type semiconductor layer, the second sublayer is arranged on the first sublayer and the P-type semiconductor layer around the first sublayer, the third sublayer is arranged on the second sublayer and the P-type semiconductor layer around the second sublayer, and the transparent conducting layer is arranged on the current blocking layer and the P-type semiconductor layer around the current blocking layer.
Optionally, a plurality of through holes are formed in the second sub-layer on the P-type semiconductor layer around the first sub-layer, and each through hole extends from the third sub-layer to the P-type semiconductor layer.
Optionally, the number of the through holes is gradually increased along a direction away from the P-type electrode.
Optionally, the cross section of the through hole is an isosceles triangle, a vertex angle of the isosceles triangle points to the P-type electrode, and the cross section of the through hole is perpendicular to the extending direction of the through hole.
On the other hand, the embodiment of the present disclosure provides a manufacturing method of a light emitting diode chip, where the manufacturing method includes:
forming a growing N-type semiconductor layer on the first surface of the substrate, wherein a partial region of the N-type semiconductor layer is a light scattering structure, and the light scattering structure is formed by a crystal structure with crystal defects;
sequentially growing an active layer and a P-type semiconductor layer on the N-type semiconductor layer;
forming a groove extending to the N-type semiconductor layer on the P-type semiconductor layer;
arranging an N-type electrode on the N-type semiconductor layer in the groove, and arranging a P-type electrode on the P-type semiconductor layer;
and laying a distributed Bragg reflector on a second surface of the substrate, wherein the second surface is the opposite surface of the first surface.
Optionally, the forming a grown N-type semiconductor layer on the first surface of the substrate includes:
growing an N-type semiconductor layer on the first surface;
forming a protective layer in a central region of the N-type semiconductor layer;
implanting ions into an edge region of the N-type semiconductor layer;
corroding the edge area of the N-type semiconductor layer to form a light scattering structure;
and removing the protective layer.
Optionally, the manufacturing method includes:
forming a first sub-layer on a region of the P-type semiconductor layer opposite to an edge region of the P-type electrode;
forming a second sublayer on the first sublayer and the P-type semiconductor layer around the first sublayer;
forming a third sublayer on the P-type semiconductor layer around the second sublayer and the second sublayer, wherein the first sublayer, the second sublayer and the third sublayer constitute a current blocking layer;
and forming a transparent conducting layer on the third sub-layer and the P-type semiconductor layer around the third sub-layer.
The technical scheme provided by the embodiment of the disclosure has the following beneficial effects:
the light scattering structure is formed in the partial edge region of the N-type semiconductor layer through the crystal structure with the crystal defects, the light scattering structure can scatter light, on one hand, the angle of the light emitted to the side of the DBR is changed, the large incident angle is changed into the small incident angle, and the DBR is favorable for reflecting the light to the side of the P-type electrode to emit the light; on the other hand changes the light angle of shooting to the chip side, and partial light can reflect to the side of P type electrode and jet out, and partial light can reflect to the DBR and reflect to the side of P type electrode and jet out to increase the light that the side of P type electrode jetted out, promote LED's positive light-emitting efficiency.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a light emitting diode chip provided in an embodiment of the present disclosure;
FIG. 2 is a top view of a light scattering structure provided by embodiments of the present disclosure;
fig. 3 is a schematic structural diagram of a current blocking layer provided by an embodiment of the present disclosure;
FIG. 4 is a top view of a via provided by an embodiment of the present disclosure;
fig. 5 is a top view of a light emitting diode chip provided by an embodiment of the present disclosure;
fig. 6 is a flowchart of a method for manufacturing a light emitting diode chip according to an embodiment of the present disclosure.
Detailed Description
To make the objects, technical solutions and advantages of the present disclosure more apparent, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.
The LED chip structure comprises a forward mounting structure, a reverse mounting structure and a vertical mounting structure. The LED chip with the forward mounting structure comprises a substrate, an N-type semiconductor layer, an active layer, a P-type semiconductor layer, an N-type electrode, a P-type electrode and a DBR. The DBR is fixed on the support, the substrate, the N-type semiconductor layer, the active layer and the P-type semiconductor layer are sequentially stacked on the DBR, a groove extending to the N-type semiconductor layer is formed in the P-type semiconductor layer, the N-type electrode is arranged on the N-type semiconductor layer in the groove, the P-type electrode is arranged on the P-type semiconductor layer, and light emitted from the side where the P-type electrode is located is used in practical application.
Light emitted from the active layer can be emitted to all directions, although the DBR can reflect the light emitted to the side of the DBR, so that the light can be emitted from the side of the P-type electrode, the DBR has different reflectivity for light with different incidence angles (the reflectivity of the DBR for light with large incidence angles is much smaller than that of the DBR for light with small incidence angles), and part of the light emitted to the side of the DBR is not reflected to the side of the P-type electrode by the DBR to be emitted. In addition, most of light rays emitted to the side surface of the chip (the surface of the chip between the side where the P-type electrode is located and the side where the DBR is located) are directly emitted, so that the front light emitting efficiency of the LED has a space for improving, and the requirement for the higher and higher brightness of the LED is met.
Based on the above situation, the embodiment of the present disclosure provides a light emitting diode chip. Fig. 1 is a schematic structural diagram of a light emitting diode chip according to an embodiment of the present disclosure. Referring to fig. 1, the light emitting diode chip includes a substrate 10, an N-type semiconductor layer 21, an active layer 22, a P-type semiconductor layer 23, an N-type electrode 31, a P-type electrode 32, and a distributed bragg reflector 40. An N-type semiconductor layer 21, an active layer 22, and a P-type semiconductor layer 23 are sequentially stacked on the first surface of the substrate 10, and a groove 20 extending to the N-type semiconductor layer 21 is formed in the P-type semiconductor layer 23. An N-type electrode 31 is disposed on the N-type semiconductor layer 21 within the recess 20, and a P-type electrode 32 is disposed on the P-type semiconductor layer 23. The distributed bragg reflector 40 is laid on a second surface of the substrate 10, the second surface being an opposite surface of the first surface. A partial region of the N-type semiconductor layer 21 is a light scattering structure 211, the light scattering structure 211 is formed of a crystal structure having crystal defects, and the light scattering structure 211 is opposite to an edge of the P-type semiconductor layer 23.
Fig. 2 is a top view of a light scattering structure provided in an embodiment of the present disclosure. Referring to fig. 2, in the embodiment of the present disclosure, the light scattering structure 211 is located in an annular region extending along an edge of the P-type semiconductor layer 23, and a length of the annular region perpendicular to the extending direction is a fixed value, such as 30 μm to 50 μm.
The crystal structure is the specific arrangement of actual mass points (atoms, ions or molecules) in the crystal, and the crystal is arranged with the most basic structural characteristics of the crystal according to the rule that the actual mass points (atoms, ions or molecules) in the crystal are periodically arranged in three dimensions. Crystal defects are the locations where the internal structural integrity of the crystal is compromised. In a crystal structure having crystal defects, the arrangement of actual particles (atoms, ions, or molecules) is irregular, and can scatter light.
The embodiment of the disclosure forms the light scattering structure in the partial region of the N-type semiconductor layer, and the light scattering structure is formed by the crystal structure with the crystal defects, so that the light scattering structure can play a role in scattering light, change the light angle emitted to the side of the DBR, change the large incident angle into the small incident angle, and is favorable for the DBR to reflect the light to the side of the P-type electrode for emission. And the edge of light scattering structure and P type semiconductor layer is relative, can also change the light angle of shooting to the chip side for some light reflects to the P type electrode place side and jets out, and some light reflects to the DBR and reflects to the P type electrode place side again and jets out, thereby increases the light that the P type electrode place side jetted out, promotes LED's positive light-emitting efficiency.
Through comparative tests, the light emitting brightness of the LED chip provided by the embodiment of the disclosure is improved by 1.6%.
In addition, the light scattering structure is formed by a crystal structure with crystal defects, belongs to a part of the N-type semiconductor layer, has better lattice matching degree with an epitaxial material, and cannot cause the reduction of the crystal quality.
Alternatively, as shown in fig. 1, the crystal defects in the light scattering structure 211 are gradually reduced in a direction from the substrate 10 to the active layer 22.
The crystal defects in the light scattering structure 211 are gradually reduced along the direction from the substrate 10 to the active layer 22, the crystal defects in the light scattering structure 211 close to the substrate 10 are large, the light angle can be greatly adjusted, the light is fully dispersed, the light with a large incident angle can be timely changed into light with a small incident angle, and the light is reflected to the side of the P-type electrode by the DBR to be emitted, so that the front light emission of the LED is increased; the crystal defects in the light scattering structure 211 close to the active layer 22 are small, and the adjustment range of the light angle is small, so that the light just irradiates to the DBR at a small angle for effective reflection, and the front light-emitting of the LED is increased.
In addition, crystal defects in the light scattering structure 211 close to the active layer 22 are small, and the crystal quality of the part, close to the active layer 22, of the N-type semiconductor layer 21 is good, so that the crystal defects in the light scattering structure 211 can be prevented from influencing the crystal quality of the active layer 22, the good crystal quality of the active layer 22 is ensured, and the light emitting efficiency of the LED is high.
Illustratively, as shown in fig. 1, the light scattering structure 211 includes two sub-layers stacked in sequence, and the crystal defects in the sub-layer near the substrate 10 are larger than those in the sub-layer near the active layer 22.
The light scattering structure 211 is formed by two sub-layers with different crystal defect sizes, so that on one hand, the crystal defects in the light scattering structure 211 are gradually reduced along the direction from the substrate 10 to the active layer 22, the front light emitting of the LED is increased, and the good crystal quality of the active layer 22 is ensured; on the other hand, the change times of the crystal defect size are less, the realization is convenient, and the cost is low.
Alternatively, as shown in fig. 1, the light scattering structure 211 is disposed spaced apart from the active layer 22.
The light scattering structure 211 and the active layer 22 are arranged at intervals, so that crystal defects in the light scattering structure 211 can be effectively prevented from influencing the crystal quality of the active layer 22, the crystal quality of the active layer 22 is ensured to be good, and the LED light-emitting efficiency is high.
Illustratively, the thickness of the light scattering structure 211 is 1 μm, and the thickness of the N-type semiconductor layer 21 is 3.5 μm.
The thickness of the light scattering structure 211 is far smaller than that of the N-type semiconductor layer 21, on one hand, the proportion of the light scattering structure 211 in the N-type semiconductor layer 21 is small, the crystal defects in the light scattering structure 211 cannot influence the crystal quality of the N-type semiconductor layer 21, on the other hand, the interval between the light scattering structure 211 and the active layer 22 is far, the crystal defects in the light scattering structure 211 cannot extend to the crystal quality of the active layer 22, and it is ensured that the arrangement of the light scattering structure 211 cannot influence the light emitting efficiency of the chip.
Optionally, as shown in fig. 1, the light emitting diode chip further includes a current blocking layer 50 and a transparent conductive layer 60. Fig. 3 is a schematic structural diagram of a current blocking layer provided in the embodiment of the present disclosure. Referring to fig. 3, the current blocking layer 50 includes a first sublayer 51, a second sublayer 52, and a third sublayer 53. The first sub-layer 51 is disposed between the edge region of the P-type electrode 32 and the P-type semiconductor layer 23, the second sub-layer 52 is disposed on the first sub-layer 51 and the P-type semiconductor layer 23 around the first sub-layer 51, the third sub-layer 53 is disposed on the second sub-layer 52 and the P-type semiconductor layer 23 around the second sub-layer 52, and the transparent conductive layer 60 is disposed on the current blocking layer 50 and the P-type semiconductor layer 23 around the current blocking layer 50.
In the related art, the current blocking layer 50 is disposed on a region of the P-type semiconductor layer 23 opposite to an edge region of the P-type electrode 32 and a region around the P-type electrode 32, and the transparent conductive layer 60 is disposed on the current blocking layer 50 and the P-type semiconductor layer 23 around the current blocking layer 50. The current blocking layer 50 can completely block the current injected from the P-type electrode 32, and the current injected from the P-type electrode 32 cannot be injected into the P-type semiconductor layer 23 through the transparent conductive layer 60 on the current blocking layer 50, and needs to flow from the transparent conductive layer 60 on the current blocking layer 50 to the transparent conductive layer 60 on the P-type semiconductor layer 23, and then to be injected into the P-type semiconductor layer 23 from the transparent conductive layer 60 on the P-type semiconductor layer 23. Since the current in the transparent conductive layer 60 on the current blocking layer 50 is accumulated in the transparent conductive layer 60 on the P-type semiconductor layer 23 and then injected into the P-type semiconductor layer 23, the current density in the region of the transparent conductive layer 60 on the P-type semiconductor layer 23 close to the current blocking layer 50 is high, which may cause the current surge to the region of the P-type semiconductor layer 23 close to the current blocking layer 50, and the LED chip may fail due to the current surge.
The current blocking layer 50 is formed by the first sublayer 51, the second sublayer 52 and the third sublayer 53, the first sublayer 51 is disposed between the edge region of the P-type electrode 32 and the P-type semiconductor layer 23, the second sublayer 52 is disposed on the first sublayer 51 and the P-type semiconductor layer 23 around the first sublayer 51, the third sublayer 53 is disposed on the second sublayer 52 and the P-type semiconductor layer 23 around the second sublayer 52, such that the thickness of the current blocking layer 50 gradually decreases in a direction away from the P-type electrode 32, the current capable of being injected into the P-type semiconductor layer 23 in the transparent conductive layer 60 on the current blocking layer 50 gradually increases in a direction away from the P-type electrode 32, the current in the transparent conductive layer 60 on the current blocking layer 50 can be gradually injected into the P-type semiconductor layer 23, current accumulation in the transparent conductive layer 60 on the current blocking layer 50 is effectively alleviated, and the current in the transparent conductive layer 60 on the current blocking layer 50 is prevented from flowing into the transparent conductive layer 23 on the P-type semiconductor layer 23 The P-type semiconductor layer 23 can be injected into the electric layer 60, so that the current density in the region, close to the current blocking layer 50, of the transparent conductive layer 60 on the P-type semiconductor layer 23 is greatly reduced, the current impact on the edge region, close to the current blocking layer 50, of the P-type semiconductor layer 23 is prevented, the reliability of the LED chip is finally improved, and the service life of the LED chip is prolonged.
Through a comparative test, the yield of the LED chip provided by the embodiment of the disclosure is improved by 5.8% under 6000V ESD (Electro-Static Discharge) current surge.
In addition, the thickness of the current blocking layer 50 formed by the first sublayer 51, the second sublayer 52 and the third sublayer 53 is gradually reduced along the direction away from the P-type electrode 32, and the current blocking layer can also play a role in scattering light, so that the light can be emitted from the side where the P-type electrode is located, and the front light-emitting efficiency of the LED chip is improved.
Alternatively, as shown in fig. 3, the second sub-layer 52 on the P-type semiconductor layer 23 around the first sub-layer 51 has a plurality of through holes 54 therein, each through hole 54 extends to the P-type semiconductor layer 23, and a partial region of the third sub-layer 53 is located on the P-type semiconductor layer 23 in the through hole 54.
The second sub-layer 52 on the P-type semiconductor layer 23 around the first sub-layer 51 has a plurality of through holes 54 therein, each through hole 54 extends to the P-type semiconductor layer 23, and a partial region of the third sub-layer 53 is located on the P-type semiconductor layer 23 in the through hole 54, so that current in the transparent conductive layer 60 on the current blocking layer 50 is directly injected into the P-type semiconductor layer 23 from the third sub-layer 53 in the through hole 54, and current accumulation in the transparent conductive layer 60 on the current blocking layer 50 is relieved. Since the plurality of through holes 54 are distributed in the partial region of the second sublayer 52, the current injected into the P-type semiconductor layer 23 from the third sublayer 53 over the entire region in the vicinity of the through holes 54 is smaller than the current injected into the P-type semiconductor layer 23 from the third sublayer 53 over the P-type semiconductor layer 23, the current that can be injected into the P-type semiconductor layer 23 in the transparent conductive layer 60 over the current blocking layer 50 is gradually increased in a direction away from the P-type electrode 32, and the current that can be injected into the transparent conductive layer 60 over the current blocking layer 50 can be gradually injected into the P-type semiconductor layer 23.
Illustratively, the cross-sectional area of the via 54 is 60% of the cross-sectional area of the second sub-layer 52 on the P-type semiconductor layer 23 around the first sub-layer 51, and the cross-sections of the via 54 and the second sub-layer 52 are perpendicular to the extending direction of the via 54.
Fig. 4 is a top view of a via provided by an embodiment of the present disclosure. Referring to fig. 4, optionally, the number of vias 54 increases gradually in a direction away from the P-type electrode 32.
The number of the through holes 54 is gradually increased in a direction away from the P-type electrode 32, and the current injected into the P-type semiconductor layer 23 from the through holes 54 is also gradually increased in a direction away from the P-type electrode 32, that is, the current capable of being injected into the P-type semiconductor layer 23 in the transparent conductive layer 60 on the current blocking layer 50 is gradually increased in a direction away from the P-type electrode 32, and the current capable of being injected into the transparent conductive layer 60 on the current blocking layer 50 is gradually injected into the P-type semiconductor layer 23.
Illustratively, the connecting lines of the centers of the plurality of through holes 54 may be two concentric circles or three concentric circles centered on the center of the P-type electrode 32.
Alternatively, as shown in fig. 4, the cross section of the via 54 is an isosceles triangle, the vertex of the isosceles triangle points to the P-type electrode 32, and the cross section of the via 54 is perpendicular to the extending direction of the via 54.
The cross section of the through hole 54 is an isosceles triangle, the vertex angle of the isosceles triangle points to the P-type electrode 32, the width of the through hole 54 gradually increases along the direction away from the P-type electrode 32, the current injected into the P-type semiconductor layer 23 from the through hole 54 also gradually increases along the direction away from the P-type electrode 32, that is, the current capable of being injected into the P-type semiconductor layer 23 in the transparent conductive layer 60 on the current blocking layer 50 gradually increases along the direction away from the P-type electrode 32, and the current in the transparent conductive layer 60 on the current blocking layer 50 can be gradually injected into the P-type semiconductor layer 23.
Illustratively, the waist length of the isosceles triangle is greater than the base length of the isosceles triangle, e.g., the waist length of the isosceles triangle is twice the base length of the isosceles triangle.
The length of the waist of the isosceles triangle is larger than the length of the bottom side of the isosceles triangle, the variation range of the width of the through hole 54 is small, and the current injected into the P-type semiconductor layer 23 from the through hole 54 is slowly increased along the direction away from the P-type electrode 32, that is, the current capable of being injected into the P-type semiconductor layer 23 in the transparent conductive layer 60 on the current blocking layer 50 is slowly increased along the direction away from the P-type electrode 32, which is beneficial to gradually injecting the current in the transparent conductive layer 60 on the current blocking layer 50 into the P-type semiconductor layer 23.
Alternatively, as shown in fig. 3, the thickness a of the first sub-layer 51 is greater than the thickness b of the second sub-layer 52, and the thickness b of the second sub-layer 52 is greater than the thickness c of the third sub-layer 53.
The thickness of the first sub-layer 51 is the largest, so that current can be effectively prevented from being injected into the P-type semiconductor layer 23 through the first sub-layer 51, and the current injected longitudinally into the P-type electrode 32 is guided to be expanded laterally; the thickness of the third sublayer 53 is the smallest, which is beneficial for injecting current into the P-type semiconductor layer 23 through the third sublayer 53 on the P-type semiconductor layer 23, and effectively prevents current in the transparent conductive layer 60 on the current blocking layer 50 from flowing into the transparent conductive layer 60 on the P-type semiconductor layer 23 and then injecting into the P-type semiconductor layer 23, thereby greatly reducing the current density in the region of the transparent conductive layer 60 on the P-type semiconductor layer 23 close to the current blocking layer 50, and preventing the region of the P-type semiconductor layer 23 close to the current blocking layer 50 from being impacted by current.
Illustratively, the first sub-layer 51 has a thickness of 1500 to 2500 angstroms, the second sub-layer 52 has a thickness of 200 to 400 angstroms, and the third sub-layer 53 has a thickness of 7 to 13 angstroms.
The thickness of the first sub-layer 51 is much greater than that of the second sub-layer 52, which can effectively prevent current from being injected into the P-type semiconductor layer 23 through the first sub-layer 51, and guide the current injected longitudinally into the P-type electrode 32 to expand laterally. The thickness of the third sublayer 53 is much smaller than that of the second sublayer 52, which can effectively prevent the current in the transparent conductive layer 60 on the current blocking layer 50 from flowing into the transparent conductive layer 60 on the P-type semiconductor layer 23 and then being injected into the P-type semiconductor layer 23, thereby greatly reducing the current density in the region of the transparent conductive layer 60 on the P-type semiconductor layer 23 close to the current blocking layer 50 and preventing the region of the P-type semiconductor layer 23 close to the current blocking layer 50 from being impacted by the current.
Alternatively, as shown in fig. 4, the length d of the first sublayer 51 in the direction away from the P-type electrode 32, the length e of the second sublayer 52 on the P-type semiconductor layer 23 in the direction away from the P-type electrode 32, and the length f of the third sublayer 53 on the P-type semiconductor layer 23 in the direction away from the P-type electrode 32 are equal.
The length d of the first sublayer 51 in the direction away from the P-type electrode 32, the length e of the second sublayer 52 on the P-type semiconductor layer 23 in the direction away from the P-type electrode 32, and the length f of the third sublayer 53 on the P-type semiconductor layer 23 in the direction away from the P-type electrode 32 are equal, and the current injected into the P-type semiconductor layer 23 from the through hole 54 increases uniformly in the direction away from the P-type electrode 32, that is, the current capable of being injected into the P-type semiconductor layer 23 in the transparent conductive layer 60 on the current blocking layer 50 increases uniformly in the direction away from the P-type electrode 32, which is beneficial for gradually injecting the current in the transparent conductive layer 60 on the current blocking layer 50 into the P-type semiconductor layer 23.
Illustratively, the material of the current blocking layer 50 is silicon oxide. The material of the transparent conductive layer 60 is ITO (Indium tin oxide) or zinc oxide, and the thickness of the transparent conductive layer 60 is 500 angstroms.
Illustratively, the material of the substrate 10 is one of sapphire, silicon carbide, aluminum oxide, zinc oxide, silicon nitride, and glass. The material of the N-type semiconductor layer 21 is N-type doped gallium nitride, and the material of the P-type semiconductor layer 23 is P-type doped gallium nitride. The active layer 22 includes quantum wells and quantum barriers alternately stacked, the material of the quantum wells is indium gallium nitride, and the material of the quantum barriers is gallium nitride.
Alternatively, as shown in fig. 1, the light emitting diode chip further includes a buffer layer 24, and the buffer layer 24 is laminated between the substrate 10 and the N-type semiconductor layer 21.
Illustratively, the material of the buffer layer 24 is aluminum nitride or gallium nitride.
Illustratively, the materials of the N-type electrode 31 and the P-type electrode 32 are Cr/Al/Cr/Ti/Al, i.e., the N-type electrode and the P-type electrode each include a Cr layer, an Al layer, a Cr layer, a Ti layer, and an Al layer, which are sequentially stacked. Among them, the thickness of the Cr layer at the bottom of the N-type electrode 31 and the P-type electrode 32 was 50 angstroms.
Fig. 5 is a top view of a light emitting diode chip provided in an embodiment of the disclosure. Referring to fig. 5, the N-type electrode 31 is composed of a pad, the P-type electrode 32 is composed of a pad 321 and an electrode line 322, one end of the electrode line 322 is connected to the pad 321, and the other end of the electrode line 322 extends toward the N-type electrode 31.
Optionally, as shown in fig. 1, the light emitting diode chip further includes a passivation protection layer 70, and the passivation protection layer 70 is laid on the side surfaces of the N-type semiconductor layer 21, the N-type electrode 31, the transparent conductive layer 60, and the P-type electrode 32.
Illustratively, the material of the passivation protection layer 70 is silicon oxide, and the thickness of the passivation protection layer 70 is 2000 angstroms.
The embodiment of the disclosure provides a manufacturing method of a light emitting diode chip, which is suitable for manufacturing the light emitting diode chip shown in fig. 1. Fig. 6 is a flowchart of a method for manufacturing a light emitting diode chip according to an embodiment of the present disclosure. Referring to fig. 6, the manufacturing method includes:
step 201: and forming a growing N-type semiconductor layer on the first surface of the substrate.
In the embodiment of the present disclosure, a partial region of the N-type semiconductor layer is a light scattering structure, and the light scattering structure is formed of a crystal structure having a crystal defect.
Optionally, the step 201 includes:
growing an N-type semiconductor layer on the first surface;
forming a protective layer in a first region of the N-type semiconductor layer;
implanting ions into a second region of the N-type semiconductor layer, wherein the second region of the N-type semiconductor layer is a region of the N-type semiconductor layer except for the first region of the N-type semiconductor layer;
corroding a second region of the N-type semiconductor layer to form a light scattering structure;
and removing the protective layer.
The second region of the N-type semiconductor layer is implanted with ions to break the connection between actual particles (atoms, ions or molecules) in the crystal and destroy the crystal structure. And then the second region of the N-type semiconductor layer is corroded, so that crystal defects can be formed in the crystal structure, and the light scattering structure is realized.
And the protective layer is formed in the first region of the N-type semiconductor layer, so that the first region of the N-type semiconductor layer can be kept unchanged by the protective layer in the process of forming the light scattering structure in the second region of the N-type semiconductor layer.
In practical application, on one hand, the difference of the sizes of crystal defects in the light scattering structure can be realized through the difference of implanted ions; on the other hand, the light scattering structure and the active layer can be arranged at intervals by growing the N-type semiconductor layer again on the N-type semiconductor layer on which the light scattering structure is formed, namely, the regrown N-type semiconductor layer covers the light scattering structure and the N-type semiconductor layer grown simultaneously with the light scattering structure.
Exemplarily, if the light scattering structure includes two sub-layers stacked in sequence, a crystal defect in the sub-layer near the substrate is larger than a crystal defect in the sub-layer near the active layer, and the light scattering structure is disposed at a distance from the active layer, the step 201 includes:
growing a first N-type semiconductor layer on the first surface;
forming a first protective layer in a first region of the first N-type semiconductor layer;
implanting first ions into a second region of the first N-type semiconductor layer, wherein the second region of the first N-type semiconductor layer is a region of the first N-type semiconductor layer except for the first region of the first N-type semiconductor layer;
corroding a second region of the first N-type semiconductor layer to form a first light scattering structure;
removing the first protective layer;
growing a second N-type semiconductor layer on the first N-type semiconductor layer;
forming a second protective layer in a first region of the second N-type semiconductor layer, the first region of the second N-type semiconductor layer being opposite to the first region of the first N-type semiconductor layer;
injecting second ions into a second region of the second N-type semiconductor layer, wherein the second region of the second N-type semiconductor layer is a region of the first N-type semiconductor layer except the first region of the first N-type semiconductor layer, and the energy of the second ions is less than that of the first ions;
corroding a second region of the second N-type semiconductor layer to form a second light scattering structure;
removing the second protective layer;
and growing a third N-type semiconductor layer on the second N-type semiconductor layer.
In the above implementation manner, the first N-type semiconductor layer, the second N-type semiconductor layer and the third N-type semiconductor layer constitute an N-type semiconductor layer, and the first light scattering structure and the second light scattering structure constitute a light scattering structure. The energy of the ions implanted when the first scattering structure is formed is greater than the energy of the ions implanted when the second scattering structure is formed, so that the crystal defects in the first scattering structure are greater than the crystal defects in the second scattering structure. The light scattering structure is spaced apart from the active layer by the third N-type semiconductor layer by growing the third N-type semiconductor layer again after the first and second scattering structures are formed.
Illustratively, the first ions are Ar ions and the second ions are B ions; the thickness of the first N-type semiconductor layer was 0.5 μm, the thickness of the second N-type semiconductor layer was 0.5 μm, and the thickness of the third N-type semiconductor layer was 2.5 μm.
In the embodiment of the present disclosure, the second region of the N-type semiconductor layer is opposite to the edge of the P-type semiconductor layer provided with the groove. In practical application, the N-type semiconductor layers of a plurality of chips are simultaneously grown on a substrate, at this time, a mark can be made on the substrate, the region of each chip is divided, and the light scattering structure is formed in the second region of the N-type semiconductor layer in the divided region of each chip.
Optionally, before step 201, the manufacturing method further includes:
cleaning the substrate;
a mark is made on the substrate.
Optionally, before step 201, the manufacturing method further includes:
a buffer layer is grown on a substrate.
Accordingly, an N-type semiconductor layer is formed on the buffer layer.
Step 202: and sequentially growing an active layer and a P-type semiconductor layer on the N-type semiconductor layer.
Optionally, this step 202 includes:
an active layer and a P-type semiconductor layer are sequentially grown on the N-type semiconductor layer by using a Metal-organic Chemical Vapor Deposition (MOCVD).
Step 203: and a groove extending to the N-type semiconductor layer is formed on the P-type semiconductor layer.
In the embodiment of the disclosure, the edge of the P-type semiconductor layer after the groove is formed is opposite to the light scattering structure.
Optionally, this step 203 comprises:
forming photoresist with a set pattern on the P-type semiconductor layer by adopting a photoetching technology;
dry etching the P-type semiconductor layer and the active layer which are not covered by the photoresist to form a groove;
and removing the photoresist.
Illustratively, the groove can be formed by utilizing an Inductively Coupled Plasma etching (ICP) device, the Plasma density is high, the etching speed is high, the photoresist loss is less, and the chip yield is favorably improved.
Step 204: an N-type electrode is arranged on the N-type semiconductor layer in the groove, and a P-type electrode is arranged on the P-type semiconductor layer.
Optionally, this step 204 comprises:
forming photoresist with a set pattern in the groove and on the P-type semiconductor layer by adopting a photoetching technology;
laying electrode materials on the photoresist, the P-type semiconductor layer and the N-type semiconductor layer which are not covered by the photoresist by adopting an evaporation technology;
and removing the photoresist and the electrode material on the photoresist, wherein the electrode material left on the P-type semiconductor layer forms a P-type electrode, and the electrode material left on the N-type semiconductor layer forms an N-type electrode.
Illustratively, the vacuum degree of the reaction chamber during evaporation is 5 x 10-6torr or more.
Optionally, before step 204, the manufacturing method further includes:
forming a first sub-layer on a region of the P-type semiconductor layer opposite to an edge region of the P-type electrode;
forming a second sublayer on the first sublayer and the P-type semiconductor layer around the first sublayer;
forming a third sublayer on the second sublayer and the P-type semiconductor layer around the second sublayer, wherein the first sublayer, the second sublayer and the third sublayer form a current blocking layer;
and forming a transparent conductive layer on the third sub-layer and the P-type semiconductor layer around the third sub-layer.
Illustratively, after forming the second sub-layer on the first sub-layer and the P-type semiconductor layer around the first sub-layer, the fabrication method further includes:
forming a patterned photoresist on the second sublayer by adopting a photoetching technology;
wet etching the second sublayer which is not covered by the photoresist, and forming a plurality of through holes in the second sublayer on the P-type semiconductor layer around the first sublayer, wherein each through hole extends from the third sublayer to the P-type semiconductor layer;
and removing the patterned photoresist.
Illustratively, forming a transparent conductive layer on the third sub-layer and the P-type semiconductor layer around the third sub-layer includes:
depositing a transparent conductive material on the current blocking layer and the P-type semiconductor layer;
forming photoresist with a set pattern on the transparent conductive material by adopting a photoetching technology;
etching the transparent conductive material which is not covered by the photoresist by a wet method, and forming a transparent conductive layer by the left transparent conductive material;
and removing the photoresist.
Illustratively, the transparent conductive material can be deposited by adopting a Magnetron Sputtering (english: magnetic Sputtering) technology, so that the formed transparent conductive layer has better compactness, better current spreading and lower working voltage of the chip. Furthermore, when the transparent conductive material is magnetron sputtered, oxygen is not introduced, the temperature is room temperature (about 25 ℃), and after the transparent conductive material is magnetron sputtered, rapid annealing is carried out, wherein the annealing environment is a dry air environment.
Optionally, after step 204, the manufacturing method further includes:
and forming a passivation protective layer on the side surfaces of the N-type semiconductor layer, the N-type electrode, the transparent conductive layer and the P-type electrode.
Step 205: a distributed bragg mirror is disposed on the second surface of the substrate.
In an embodiment of the disclosure, the second surface is an opposite surface of the first surface.
Optionally, before step 205, the manufacturing method further includes:
and thinning the substrate.
Illustratively, the thickness of the substrate after thinning is 120 μm.
Optionally, after step 205, the manufacturing method further includes:
carrying out invisible cutting on the substrate;
splitting the substrate to obtain at least two mutually independent chips;
and testing the chip.
By stealth dicing and breaking, the loss of brightness can be better reduced.
The above description is intended to be exemplary only and not to limit the present disclosure, and any modification, equivalent replacement, or improvement made without departing from the spirit and scope of the present disclosure is to be considered as the same as the present disclosure.
Claims (7)
1. A light emitting diode chip, characterized in that it comprises a substrate (10), an N-type semiconductor layer (21), an active layer (22), a P-type semiconductor layer (23), an N-type electrode (31), a P-type electrode (32), a distributed Bragg reflector (40), a current blocking layer (50) and a transparent conductive layer (60); the N-type semiconductor layer (21), the active layer (22) and the P-type semiconductor layer (23) are sequentially laminated on the first surface of the substrate (10), and a groove (20) extending to the N-type semiconductor layer (21) is formed in the P-type semiconductor layer (23); the N-type electrode (31) is arranged on the N-type semiconductor layer (21) in the groove (20), and the P-type electrode (32) is arranged on the P-type semiconductor layer (23); the distributed Bragg reflector (40) is laid on a second surface of the substrate (10), the second surface being an opposite surface of the first surface; a partial region of the N-type semiconductor layer (21) is a light scattering structure (211), the light scattering structure (211) is formed by a crystal structure with crystal defects, a part of the light scattering structure (211) is opposite to the edge of the P-type semiconductor layer (23), and the current blocking layer (50) comprises a first sub-layer (51), a second sub-layer (52) and a third sub-layer (53); the first sublayer (51) is arranged between an edge region of the P-type electrode (32) and the P-type semiconductor layer (23), the second sub-layer (52) is arranged on the first sub-layer (51) and the P-type semiconductor layer (23) around the first sub-layer (51), the third sub-layer (53) is arranged on the second sub-layer (52) and the P-type semiconductor layer (23) around the second sub-layer (52), the transparent conductive layer (60) is disposed on the current blocking layer (50) and the P-type semiconductor layer (23) around the current blocking layer (50), a plurality of through holes (54) are arranged in a second sub-layer (52) on the P-type semiconductor layer (23) around the first sub-layer (51), each through hole (54) extends to the P-type semiconductor layer (23), a partial region of the third sublayer (53) is located on the P-type semiconductor layer (23) in the through hole (54).
2. The light-emitting diode chip as claimed in claim 1, characterized in that the crystal defects in the light-scattering structures (211) decrease in a direction from the substrate (10) to the active layer (22).
3. The light-emitting diode chip as claimed in claim 2, characterized in that the light-scattering structures (211) are arranged at a distance from the active layer (22).
4. The light-emitting diode chip as claimed in claim 1, characterized in that the number of the through-holes (54) increases progressively in the direction away from the P-type electrode (32).
5. The light-emitting diode chip as claimed in claim 1, characterized in that the cross section of the through-hole (54) is an isosceles triangle, the vertex angle of the isosceles triangle pointing towards the P-type electrode (32), the cross section of the through-hole (54) being perpendicular to the extending direction of the through-hole (54).
6. A manufacturing method of a light emitting diode chip is characterized by comprising the following steps:
forming an N-type semiconductor layer on a first surface of a substrate, wherein a partial region of the N-type semiconductor layer is a light scattering structure, and the light scattering structure is formed by a crystal structure with crystal defects;
sequentially growing an active layer and a P-type semiconductor layer on the N-type semiconductor layer;
a groove extending to the N-type semiconductor layer is formed in the P-type semiconductor layer, and one part of the light scattering structure is opposite to the edge of the P-type semiconductor layer;
arranging an N-type electrode on the N-type semiconductor layer in the groove, and arranging a P-type electrode on the P-type semiconductor layer;
laying a distributed Bragg reflector on a second surface of the substrate, wherein the second surface is the opposite surface of the first surface;
forming a first sub-layer on a region of the P-type semiconductor layer opposite to an edge region of the P-type electrode;
forming a second sublayer on the first sublayer and the P-type semiconductor layer around the first sublayer;
forming a third sublayer on the second sublayer and the P-type semiconductor layer around the second sublayer, wherein the first sublayer, the second sublayer and the third sublayer constitute a current blocking layer, the second sublayer on the P-type semiconductor layer around the first sublayer is provided with a plurality of through holes therein, each through hole extends to the P-type semiconductor layer, and a partial region of the third sublayer is located on the P-type semiconductor layer in the through hole;
and forming a transparent conducting layer on the third sub-layer and the P-type semiconductor layer around the third sub-layer.
7. The method of claim 6, wherein forming an N-type semiconductor layer on the first surface of the substrate comprises:
growing an N-type semiconductor layer on the first surface;
forming a protective layer in the first region of the N-type semiconductor layer;
implanting ions into a second region of the N-type semiconductor layer, wherein the second region is a region of the N-type semiconductor layer except the first region;
corroding the second region of the N-type semiconductor layer to form a light scattering structure;
and removing the protective layer.
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