CN112260682A

CN112260682A - TSPC trigger, dual-mode prescaler and frequency divider related device

Info

Publication number: CN112260682A
Application number: CN202011155433.6A
Authority: CN
Inventors: 杨建伟
Original assignee: Calterah Semiconductor Technology Shanghai Co Ltd
Current assignee: Calterah Semiconductor Technology Shanghai Co Ltd
Priority date: 2020-10-26
Filing date: 2020-10-26
Publication date: 2021-01-22
Anticipated expiration: 2040-10-26
Also published as: CN112260682B

Abstract

The invention provides a TSPC trigger, a dual-mode prescaler and a frequency divider, which comprise a first-stage structure; the first stage structure comprises a first transistor and a second transistor, and the size of the second transistor is larger than that of the first transistor; the first end of the first transistor is connected with a power supply, the grid electrode of the first transistor is connected with a clock signal end, the second end of the first transistor is connected with the first end of the second transistor, the second end of the second transistor is grounded, and the grid electrode of the second transistor is connected with the first signal end. Because the first end of the first transistor connected with the clock signal end is connected with the power supply, compared with the prior art, the transistor connected with the clock signal end, namely the first transistor, is closer to the power supply, and after the clock signal input by the clock signal end controls the first transistor to be conducted, the power supply voltage can be transmitted to the output end of the first-stage structure more quickly, so that the working speed of the TSPC trigger, the dual-mode pre-divider and the frequency divider is improved.

Description

TSPC trigger, dual-mode prescaler and frequency divider related device

Technical Field

The invention relates to the technical field of digital circuits, in particular to a TSPC trigger, a dual-mode prescaler and a frequency divider related device.

Background

Frequency dividers are commonly used to convert a high frequency clock signal to a low frequency clock signal. A conventional frequency divider includes a plurality of cascaded dual-modulus prescalers that divide 2/3 according to a divide mode control signal selection. By separately controlling each dual-modulus prescaler in the plurality of cascaded dual-modulus prescalers to divide frequency by 2/3, a high-frequency clock signal can be converted into a low-frequency clock signal with a specified division multiple.

As shown in fig. 1, a conventional dual-mode prescaler includes 4 latches Latch1 to Latch4 AND three AND gates AND1 to AND3, where the Latch1 AND the Latch2 form a TSPC (True Single Phase Clock) flip-flop, the Latch3 AND the Latch4 form another TSPC flip-flop, CLKIN is an input Clock signal, CLKO is an output Clock signal, MoDin is an input mode control signal, moddout is an output mode control signal, AND P is a control signal. When the Modin is 0 or the Modin is 1 and P is 0, the dual-mode prescaler works in a frequency division state of 2, and the frequency of the CLKO is 1/2 of the CLKIN; when Modin is 1 and P is 1, the dual-mode prescaler operates in a frequency division state of 3, and the frequency of CLKO is 1/3 of CLKIN. However, the operation speed of the dual prescaler is low because the operation speed of the TSPC flip-flop in the dual prescaler is low.

Disclosure of Invention

In view of the above, the present invention provides a TSPC flip-flop, a dual-modulus prescaler, and a frequency divider to increase the operating speed of the TSPC flip-flop.

In order to achieve the purpose, the invention provides the following technical scheme:

a TSPC flip-flop includes a first stage structure;

the first stage structure comprises a first transistor and a second transistor, and the size of the second transistor is larger than that of the first transistor;

the first end of the first transistor is connected with a power supply, the grid electrode of the first transistor is connected with a clock signal end, the second end of the first transistor is connected with the first end of the second transistor, the second end of the second transistor is grounded, and the grid electrode of the second transistor is connected with the first signal end.

Optionally, the size of the second transistor is at least 4 times larger than the size of the first transistor.

Optionally, the first stage structure further includes a third transistor, and the second end of the first transistor is connected to the first end of the second transistor through the third transistor; a gate of the third transistor is coupled to the first signal terminal.

Optionally, a second primary structure connected to the first primary structure;

the second stage structure comprises a fourth transistor and a fifth transistor, and the size of the fourth transistor is larger than that of the fifth transistor;

the first end of the fourth transistor is connected with a power supply, the grid electrode of the fourth transistor is connected with the clock signal end, the second end of the fourth transistor is connected with the first end of the fifth transistor, the second end of the fifth transistor is grounded, and the grid electrode of the fifth transistor is connected with the common end of the second transistor and the third transistor.

Optionally, a third level structure connected to the second level structure;

the third-level structure includes a sixth transistor and a seventh transistor, and a size of the sixth transistor is larger than a size of the seventh transistor;

the first end of the sixth transistor is connected with a power supply, the second end of the sixth transistor is connected with the first end of the seventh transistor, the grid electrode of the sixth transistor is connected with the common end of the fourth transistor and the fifth transistor, the second end of the seventh transistor is grounded, and the grid electrode of the seventh transistor is connected with the clock signal end.

Optionally, the size of the fourth transistor is at least 4 times larger than the size of the fifth transistor; and/or the presence of a gas in the gas,

the size of the sixth transistor is at least 4 times larger than the size of the seventh transistor.

Optionally, the third-stage structure further includes an eighth transistor, and the second terminal of the sixth transistor is connected to the first terminal of the seventh transistor through the eighth transistor;

a first end of the eighth transistor is connected with a second end of the sixth transistor, a second end of the eighth transistor is connected with a first end of the seventh transistor, and a gate of the eighth transistor is connected with a common end of the fourth transistor and the fifth transistor.

A dual modulus prescaler comprising a first flip-flop and a second flip-flop, the first flip-flop comprising a TSPC flip-flop as described in any of the above, and/or the second flip-flop comprising a TSPC flip-flop as described in any of the above.

Optionally, the second flip-flop comprises the first transistor, the second transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor;

the dual-mode prescaler further comprises a tenth transistor and an eleventh transistor;

a first end of the tenth transistor is connected with a power supply, a second end of the tenth transistor is connected with a second end of a sixth transistor in the second trigger, and a grid electrode of the tenth transistor is connected with a second signal end;

a first end of the eleventh transistor is connected with a second end of a second transistor in the second trigger, a second end of the eleventh transistor is grounded, and a gate of the eleventh transistor is connected with a signal input end of the dual-mode frequency divider.

Optionally, the first flip-flop comprises the first transistor, the second transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor;

the dual-mode prescaler further comprises a first inverter and a ninth transistor;

the input end of the first inverter is connected with the common end of the sixth transistor and the eighth transistor; the output end of the first inverter is connected with the grid electrode of a second transistor in the second trigger;

a first end of the ninth transistor is connected with a second end of the second transistor in the first trigger, a second end of the ninth transistor is grounded, and a grid electrode of the ninth transistor is connected with an input end of the first inverter;

the grid electrode of a second transistor in the first trigger is connected with the second end of a sixth transistor in the second trigger, and the second end of the sixth transistor in the second trigger is connected with the grid electrode of the sixth transistor in the second trigger;

wherein sizes of the ninth transistor, the second transistor, and the eleventh transistor are larger than a size of the first transistor, and sizes of the tenth transistor and a sixth transistor in the second flip-flop are larger than a size of the seventh transistor.

Optionally, the dual-mode frequency divider further comprises a second inverter, an input end of the second inverter is connected to a gate of a fifth transistor in the second flip-flop, and an output end of the second inverter is a signal output end of the dual-mode frequency divider.

Optionally, a size of the ninth transistor, a size of the second transistor, and a size of the eleventh transistor is at least 4 times a size of the first transistor;

the size of the tenth transistor is at least 4 times the size of the seventh transistor, and the size of the sixth transistor in the second flip-flop is at least 4 times the size of the seventh transistor.

Optionally, the first flip-flop includes the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor;

the dual-mode prescaler further comprises a first inverter, a twelfth transistor and a thirteenth transistor;

the input end of the first inverter is connected with the common end of a sixth transistor and an eighth transistor in the first trigger; the output end of the first inverter is connected with the grid electrode of the second transistor and the grid electrode of the third transistor in the second trigger;

a first end of the twelfth transistor is connected with a first end of the second transistor, a second end of the twelfth transistor is connected with a second end of the second transistor, and a grid electrode of the twelfth transistor is connected with an input end of the first phase inverter; a first end of the thirteenth transistor is connected to the first end of the third transistor, a second end of the thirteenth transistor is grounded, and a gate of the thirteenth transistor is connected to the input end of the first inverter.

Optionally, the second flip-flop includes the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor;

the dual-mode prescaler further comprises a fourteenth transistor, a fifteenth transistor, a sixteenth transistor and a seventeenth transistor;

a first end of the fourteenth transistor is connected with a power supply, a second end of the fourteenth transistor is connected with a second end of a sixth transistor in the second trigger, and a gate of the fourteenth transistor is connected with a second signal end; a second end of a sixth transistor in the second trigger is connected with a first end of an eighth transistor, a first end of a fifteenth transistor is connected with a second end of the sixth transistor in the second trigger, a second end of the fifteenth transistor is connected with a first end of an eighth transistor in the second trigger, and a gate of the fifteenth transistor is connected with the second signal end;

a first end of the sixteenth transistor is connected with a first end of a second transistor in the second trigger, a second end of the sixteenth transistor is connected with a second end of the second transistor, and a grid electrode of the sixteenth transistor is connected with a signal input end of the dual-mode prescaler; a first end of the seventeenth transistor is connected with a second end of a seventh transistor in the second trigger, a second end of the seventeenth transistor is grounded, and the seventeenth transistor is connected with a signal input end of the dual-mode prescaler;

and the grid electrodes of the second transistor and the third transistor in the first trigger are connected with the second end of the sixth transistor in the second trigger.

Optionally, the dual-mode frequency divider further comprises a third inverter, an input end of the third inverter is connected to a gate of a fifth transistor in the second flip-flop, and an output end of the third inverter is a signal output end of the dual-mode frequency divider.

A frequency divider comprising a plurality of cascaded dual-modulus prescalers, the dual-modulus prescalers comprising a dual-modulus prescaler as described in any one of the above.

An integrated circuit, comprising:

a frequency divider as described above.

Optionally, the integrated circuit is a millimeter wave radar chip.

A radio device, comprising:

a carrier;

an integrated circuit as described above, disposed on the carrier;

an antenna disposed on the carrier or integrated in a package of the integrated circuit;

wherein, the integrated circuit is connected with the antenna and used for receiving and transmitting radio signals.

An apparatus, comprising:

an apparatus body; and

the radio device as described above provided on the apparatus body;

wherein the radio device is used for object detection and/or communication.

Compared with the prior art, the technical scheme provided by the invention has the following advantages:

according to the TSPC trigger, the dual-mode prescaler and the frequency divider provided by the invention, because the first end of the first transistor connected with the clock signal end is connected with the power supply, compared with the prior art, the transistor connected with the clock signal end, namely the first transistor, is closer to the power supply, and after the clock signal input by the clock signal end controls the first transistor to be conducted, the power supply voltage can be more quickly transmitted to the output end of the first-stage structure, namely the second end of the first transistor, so that the working speeds of the TSPC trigger, the dual-mode prescaler and the frequency divider are improved.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.

FIG. 1 is a schematic diagram of a dual-modulus prescaler of the prior art;

FIG. 2 is a schematic diagram of a TSPC flip-flop in the dual-modulus prescaler shown in FIG. 1;

fig. 3 is a schematic structural diagram of a TSPC flip-flop according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram of a TSPC flip-flop according to another embodiment of the present invention;

fig. 5 is a schematic structural diagram of a TSPC flip-flop according to another embodiment of the present invention;

fig. 6 is a schematic structural diagram of a TSPC flip-flop according to another embodiment of the present invention;

FIG. 7 is a timing diagram of a TSPC flip-flop according to an embodiment of the present invention;

FIG. 8 is a diagram illustrating a dual modulus prescaler according to an embodiment of the present invention;

FIG. 9 is a diagram illustrating a dual-modulus prescaler according to another embodiment of the present invention;

FIG. 10 is a diagram illustrating a dual modulus prescaler according to another embodiment of the present invention;

FIG. 11 is a diagram illustrating a dual modulus prescaler according to another embodiment of the present invention;

FIG. 12 is a timing diagram of the dual-mode prescaler according to one embodiment of the present invention when MoDin is high and P is high;

FIG. 13 is a timing diagram of a dual-mode prescaler according to one embodiment of the present invention when MoDin is low;

FIG. 14 is a timing diagram of the dual-mode prescaler according to one embodiment of the present invention when MoDin is high and P is low;

fig. 15 is a schematic structural diagram of a plurality of cascaded dual-modulus prescalers according to an embodiment of the present invention.

Detailed Description

As background, the operating speed of existing TSPC flip-flops is low, resulting in a low operating speed of the dual modulus prescaler and divider. As shown in fig. 2, fig. 2 is a schematic structural diagram of a TSPC flip-flop in the dual-mode prescaler shown in fig. 1, and includes transistors P1 to P9, and the inventor has found that, when CLK is 1, so that the transistor P2 is turned on, the voltage of the power supply VDD needs to be transmitted to the common terminal of the transistor P1 and the transistor P2, and then transmitted through the turned-on transistor P2, which results in a lower operating speed of the TSPC flip-flop.

Based on this, the invention provides a TSPC trigger, a dual-mode prescaler and a frequency divider to overcome the above problems in the prior art, wherein the TSPC trigger comprises a first-stage structure;

According to the TSPC trigger, the dual-mode prescaler and the frequency divider provided by the invention, because the first end of the first transistor connected with the clock signal end is connected with the power supply, compared with the prior art shown in figure 2, the transistor connected with the clock signal end, namely the first transistor, is closer to the power supply, and after the clock signal input by the clock signal end controls the first transistor to be conducted, the power supply voltage can be more quickly transmitted to the output end of the first-stage structure, namely the second end of the first transistor, so that the working speeds of the TSPC trigger, the dual-mode prescaler and the frequency divider are improved.

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, so that the above is the core idea of the present invention, and the above objects, features and advantages of the present invention can be more clearly understood. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

An embodiment of the present invention provides a TSPC flip-flop, as shown in fig. 3, including a first stage structure 11, where the first stage structure 11 includes a first transistor M1 and a second transistor M2, and a size of the second transistor M2 is larger than a size of the first transistor M1.

A first terminal of the first transistor M1 is connected to the power supply VDD, a gate of the first transistor M1 is connected to the clock signal terminal CLKIN, a second terminal of the first transistor M1 is connected to the first terminal of the second transistor M2, a second terminal of the second transistor M2 is grounded, and a gate of the second transistor M2 is connected to the first signal terminal DIN.

Since the first end of the first transistor M1 connected to the clock signal terminal CLKIN is connected to the power supply VDD, compared with the prior art shown in fig. 2, the transistor connected to the clock signal terminal CLKIN, i.e., the first transistor M1, is closer to the power supply VDD in the embodiment of the present invention, and after the clock signal input from the clock signal terminal CLKIN controls the first transistor M1 to be turned on, the voltage of the power supply VDD is faster transmitted to the output terminal of the first stage structure 11, i.e., the second end of the first transistor, thereby increasing the operating speed of the TSPC flip-flop, the dual-mode prescaler and the frequency divider.

In some embodiments of the present invention, as shown in FIG. 3, the TSPC flip-flop further comprises a second level structure 12 coupled to the first level structure 11; the second stage structure 12 includes a fourth transistor M4 and a fifth transistor M5, and the size of the fourth transistor M4 is larger than the size of the fifth transistor M5.

A first terminal of the fourth transistor M4 is connected to the power supply VDD, a gate of the fourth transistor M4 is connected to the clock signal terminal CLKIN, a second terminal of the fourth transistor M4 is connected to a first terminal of the fifth transistor M5, a second terminal of the fifth transistor M5 is grounded, and a gate of the fifth transistor M5 is connected to a common terminal of the second transistor M2 and the third transistor M3.

In some embodiments of the present invention, as shown in FIG. 3, the TSPC flip-flop further comprises a third level structure 13 coupled to the second level structure 12; the third stage structure 13 includes a sixth transistor M6 and a seventh transistor M7, and the size of the seventh transistor M7 is larger than that of the sixth transistor M6.

A first terminal of the sixth transistor M6 is connected to the power supply VDD, a second terminal of the sixth transistor M6 is connected to a first terminal of the seventh transistor M7, a gate of the sixth transistor M6 is connected to a common terminal of the fourth transistor M4 and the fifth transistor M5, a second terminal of the seventh transistor M7 is grounded, and a gate of the seventh transistor M7 is connected to the clock signal terminal CLKIN. Also, the output terminal DOUT of the TSPC flip-flop is connected to the second terminal of the sixth transistor M6 and the first terminal of the seventh transistor M7.

It should be noted that, in the embodiment of the present invention, in order to ensure that the low level at the point a is enough to control the fifth transistor M5 to turn off when the first transistor M1 and the second transistor M2 are turned on simultaneously under all process conditions, the size of the second transistor M2 is larger than that of the first transistor M1; in order to ensure that the high level at the point B is enough to control the sixth transistor M6 to turn off when the fourth transistor M4 and the fifth transistor M5 are turned on simultaneously under all process conditions, therefore, the size of the fourth transistor M4 is larger than that of the fifth transistor M5; in order to ensure that the output terminal CLKINOB output satisfies the required high level when the sixth transistor M6 and the seventh transistor M7 are simultaneously turned on under all process conditions, the size of the sixth transistor M6 is larger than that of the seventh transistor M7.

Further optionally, the size of the second transistor M2 is at least 4 times larger than the size of the first transistor M1; and/or the size of the fourth transistor M4 is at least 4 times larger than the size of the fifth transistor M5; and/or the size of the sixth transistor M6 is at least 4 times larger than the size of the seventh transistor M7.

It should be noted that the dimensions of the transistor in the embodiment of the present invention include the length and the width of the channel of the transistor. Alternatively, the size of the second transistor M2 may be at least 4 times larger than the size of the first transistor M1, such that the channel length of the second transistor M2 is the same as the channel length of the first transistor M1, the channel width of the second transistor M2 is at least 4 times larger than the channel width of the first transistor M1, such that the channel width of the second transistor M2 is the same as the channel width of the first transistor M1, the channel length of the second transistor M2 is at least 4 times larger than the channel length of the first transistor M1, the channel length of the second transistor M2 is at least 4 times larger than the channel length of the first transistor M1, and the channel width of the second transistor M2 is at least 4 times larger than the channel width of the first transistor M1. The size relationship between the fourth transistor M4 and the fifth transistor M5, and the size relationship between the sixth transistor M6 and the seventh transistor M7 are the same, and are not described in detail herein.

Simulation shows that the key factor limiting the operating speed of the flip-flop in fig. 2 is the discharge speed from the point B to the ground, and therefore, compared with the flip-flop in fig. 2, the second stage structure 12 shown in fig. 3 omits the transistor P6 in fig. 2, so that the operating speed of the flip-flop is improved on the basis of reducing power consumption.

Since the speed of discharge of the output terminal DOUT to ground is not a critical factor in limiting the operating speed of the flip-flop, the transistor P9 in fig. 2 is eliminated from the third stage 13 shown in fig. 3 to further reduce the power consumption of the flip-flop. Of course, the present invention is not limited thereto, and in other embodiments of the present invention, the transistor P9 in fig. 2 may not be removed in order to ensure the stability of the third stage structure 13.

As shown in fig. 4, the third stage structure 13 further includes an eighth transistor M8, and the second terminal of the sixth transistor M6 is connected to the first terminal of the seventh transistor M7 through the eighth transistor M8.

A first terminal of the eighth transistor M8 is connected to the second terminal of the sixth transistor M6, a second terminal of the eighth transistor M8 is connected to the first terminal of the seventh transistor M7, and a gate of the eighth transistor M8 is connected to a common terminal of the fourth transistor M4 and the fifth transistor M5.

Compared with the flip-flop shown in fig. 2, the first-stage structure 11 of the flip-flop shown in fig. 3 has the transistor P1 in fig. 2 removed, so as to further increase the operation speed of the flip-flop and reduce the power consumption of the flip-flop based on the increase of the operation speed of the flip-flop. Of course, the present invention is not limited thereto, and in other embodiments of the present invention, the transistor P1 in fig. 2 may not be removed in order to ensure the stability of the first stage structure 11.

As shown in fig. 5 and 6, the first stage structure 11 further includes a third transistor M3, and the second terminal of the first transistor M1 is connected to the first terminal of the second transistor M2 through the third transistor M3.

A first terminal of the third transistor M3 is coupled to the second terminal of the first transistor M1, a second terminal of the third transistor M3 is coupled to the first terminal of the second transistor M2, and a gate of the third transistor M3 is coupled to the first signal terminal DIN.

In some embodiments of the present invention, as shown in fig. 3 to 6, the first transistor M1, the third transistor M3, the fourth transistor M4 and the sixth transistor M6 are PMOS transistors, and the second transistor M2, the fifth transistor M5, the seventh transistor M7 and the eighth transistor M8 are NMOS transistors. Of course, the present invention is not limited thereto, and in other embodiments, the first transistor M1, the third transistor M3, the fourth transistor M4 and the sixth transistor M6 may also be NMOS transistors, and the second transistor M2, the fifth transistor M5, the seventh transistor M7 and the eighth transistor M8 may also be PMOS transistors.

The operation of the TSPC flip-flop will be described below by taking the structure shown in fig. 3 as an example.

As shown in fig. 7, when the first signal terminal DIN is at a low level and the clock signal terminal CLKIN is at a low level, the first transistor M1 is turned on, the fourth transistor M4 is turned on, the second transistor M2 is turned off, and the seventh transistor M7 is turned off, the high level of the power VDD is transmitted to the point a through the turned-on first transistor M1, so that the fifth transistor M5 is turned on. Since the fourth transistor M4 is turned on and the size of the fourth transistor M4 is larger than that of the fifth transistor M5, the turned-on fourth transistor M4 pulls the B point to a high level, so that the sixth transistor M6 is turned off, so that the high level of the B point is directly transmitted to the output terminal CLKINOB.

When the first signal terminal DIN is at a low level and the clock signal terminal CLKIN is at a high level, the first transistor M1, the second transistor M2, and the fourth transistor M4 are turned off, the seventh transistor M7 is turned on, the point a is maintained at a high level, and the fifth transistor M5 is continuously turned on, so that the point B is pulled to a low level, and the sixth transistor M6 is turned on. Since the size of the sixth transistor M6 is larger than that of the seventh transistor M7, the output terminal CLKINOB continuously outputs a high level.

When the first signal terminal DIN is at a high level and the clock signal terminal CLKIN is at a low level, the first transistor M1 is turned on, the second transistor M2 is turned on, the fourth transistor M4 is turned on, and the seventh transistor M7 is turned off. Since the size of the second transistor M2 is larger than that of the first transistor M1, the turned-on second transistor M2 pulls the point a low to a low level, so that the fifth transistor M5 is turned off. Since the fourth transistor M4 is turned on, the point B is pulled high, so that the sixth transistor M6 is turned off. Since both the sixth transistor M6 and the seventh transistor M7 are turned off, a high level of the B point is transmitted to the output terminal CLKINOB.

When the first signal terminal DIN is at a high level and the clock signal terminal CLKIN is at a high level, the first transistor M1 is turned off, the second transistor M2 is turned on, the fourth transistor M4 is turned off, and the seventh transistor M7 is turned on. The turned-on second transistor M2 keeps pulling the point a low to a low level, so that the fifth transistor M5 is turned off. Since the fourth transistor M4 and the fifth transistor M5 are turned off, the point B is maintained at a high level, so that the sixth transistor M6 is turned off. Since the seventh transistor M7 is turned on, the output terminal CLKINOB is pulled to a low level.

In the structure shown in fig. 5, the timing sequences of the first signal terminal DIN, the clock signal terminal CLKIN, the point a, the point B, and the output terminal CLKINOB are the same as the timing sequences of the structure shown in fig. 3, and the specific process is not repeated here.

In the structure shown in fig. 4, as shown in fig. 7, when the first signal terminal DIN is at a low level and the clock signal terminal CLKIN is at a low level, the first transistor M1 is turned on, the fourth transistor M4 is turned on, the second transistor M2 is turned off, the seventh transistor M7 is turned off, and the high level of the power supply VDD is transmitted to the point a through the turned-on first transistor M1, so that the fifth transistor M5 is turned on. Since the fourth transistor M4 is turned on and the size of the fourth transistor M4 is larger than that of the fifth transistor M5, the turned-on fourth transistor M4 pulls the B point to a high level, so that the sixth transistor M6 is turned off, so that the output terminal CLKINOB is maintained in an initial state.

When the first signal terminal DIN is at a low level and the clock signal terminal CLKIN is at a high level, the first transistor M1, the second transistor M2, and the fourth transistor M4 are turned off, the seventh transistor M7 is turned on, the point a is maintained at a high level, and the fifth transistor M5 is continuously turned on, so that the point B is pulled to a low level, and the sixth transistor M6 is turned on. The high level of the power supply VDD is transmitted to the output terminal CLKINOB through the turned-on sixth transistor M6.

When the first signal terminal DIN is at a high level and the clock signal terminal CLKIN is at a low level, the first transistor M1 is turned on, the second transistor M2 is turned on, the fourth transistor M4 is turned on, and the seventh transistor M7 is turned off. Since the size of the second transistor M2 is larger than that of the first transistor M1, the turned-on second transistor M2 pulls the point a low to a low level, so that the fifth transistor M5 is turned off. Since the fourth transistor M4 is turned on, the point B is pulled high, so that the sixth transistor M6 is turned off. Since both the sixth transistor M6 and the seventh transistor M7 are turned off, the output terminal CLKINOB is maintained at a high level.

When the first signal terminal DIN is at a high level and the clock signal terminal CLKIN is at a high level, the first transistor M1 is turned off, the second transistor M2 is turned on, the fourth transistor M4 is turned off, and the seventh transistor M7 is turned on. The turned-on second transistor M2 keeps pulling the point a low to a low level, so that the fifth transistor M5 is turned off. Since the fourth transistor M4 and the fifth transistor M5 are turned off, the point B is maintained at a high level, so that the sixth transistor M6 is turned off. Since both the seventh transistor M7 and the eighth transistor M8 are turned on, the output terminal CLKINOB is pulled to a low level.

In the structure shown in fig. 6, the timing of the first signal terminal DIN, the clock signal terminal CLKIN, the point a, the point B, and the output terminal CLKINOB are the same as the timing of the structure shown in fig. 4, and the specific process is not repeated here.

An embodiment of the present invention further provides a dual-modulus prescaler, which includes a first flip-flop and a second flip-flop, where the first flip-flop includes the TSPC flip-flop provided in any of the above embodiments, and/or the second flip-flop includes the TSPC flip-flop provided in any of the above embodiments.

In some embodiments of the present invention, as shown in fig. 8, the second flip-flop 2 includes a first transistor M1, a second transistor M2, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6 and a seventh transistor M7, and connection relationships of the first transistor M1, the second transistor M2, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6 and the seventh transistor M7 are the same as those of the embodiment shown in fig. 3, and are not described herein again.

In any of the above embodiments, as shown in fig. 8, the dual-modulus prescaler further includes a ninth transistor M9, a tenth transistor M10, and an eleventh transistor M11.

A first end of the ninth transistor M9 is connected to the second end of the second transistor M2 in the first flip-flop 1, a second end of the ninth transistor M9 is grounded, and a gate of the ninth transistor M9 is connected to an input terminal CLKOB of the first inverter INV 1; an output terminal CLKO of the first inverter INV1 is connected to the gate of the second transistor M2 in the second flip-flop 2.

A first terminal of the tenth transistor M10 is connected to the power source VDD, a second terminal of the tenth transistor M10 is connected to the second terminal of the sixth transistor M6 in the second flip-flop 2, and a gate of the tenth transistor M10 is connected to the second signal terminal P.

A first terminal of the eleventh transistor M11 is connected to the second terminal of the second transistor M2 in the second flip-flop 2, a second terminal of the eleventh transistor M11 is grounded, and a gate of the eleventh transistor M11 is connected to the signal input terminal MoDin of the dual-mode frequency divider.

On the basis of the above embodiments, in some embodiments of the present invention, as shown in fig. 8, the first flip-flop 1 includes a first transistor M1, a second transistor M2, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, and a first inverter INV 1; the connection relationship of the first transistor M1, the second transistor M2, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7 and the eighth transistor M8 is the same as that of the embodiment shown in fig. 4, and is not repeated herein. Further, an input terminal of the first inverter INV1 is connected to the common terminal CLKOB of the sixth transistor M6 and the eighth transistor M8 in the first flip-flop 1. The gate of the second transistor M2 in the first flip-flop 1 is connected to the second terminal of the sixth transistor M6 in the second flip-flop 2, and the second terminal of the sixth transistor M6 in the second flip-flop 2 is connected to the gate of the sixth transistor M6 in the second flip-flop 2.

It should be noted that, in the frequency divider, the first-stage dual-mode prescaler does not need to output a signal, that is, the first-stage dual-mode prescaler does not have the signal output terminal MoDout, and therefore, in some embodiments of the present invention, as shown in fig. 8, the dual-mode prescaler does not have the signal output terminal MoDout. However, since the dual-mode prescalers of other stages need to output signals to the dual-mode prescalers of the previous stage, in some embodiments of the present invention, the dual-mode prescalers have signal output terminals MoDout.

On the basis of the above embodiment, as shown in fig. 9, the dual-mode prescaler further includes a second inverter INV2, an input end of the second inverter INV2 is connected to the gate of the fifth transistor M5 in the second flip-flop 2, and an output end of the second inverter INV2 is the signal output end MoDout of the dual-mode frequency divider.

Although the first-stage dual-mode prescaler may also have a signal output end MoDout, since the dual-mode prescaler is connected to the signal output end MoDout through the inverter, and the inverter introduces additional parasitic capacitance, in some embodiments of the present invention, it is preferable that the first-stage dual-mode prescaler does not have the signal output end MoDout, and the other stages of dual-mode prescalers have the signal output end MoDout, that is, the first-stage dual-mode prescaler has the structure shown in fig. 8, and the other stages of dual-mode prescalers have the structure shown in fig. 9.

In the structures shown in fig. 8 and 9, the number of stacked transistors in the critical path is reduced, but the number of stacked transistors in the non-critical path is not reduced, so that the operating speed is increased, and the power consumption is reduced. However, in order to ensure that the structures shown in fig. 8 and 9 can stably operate under all process conditions, the sizes of the ninth transistor M9, the second transistor M2, and the eleventh transistor M11 are larger than the size of the first transistor M1, and the size of the tenth transistor M10 and the size of the sixth transistor M6 in the second flip-flop 2 are larger than the size of the seventh transistor M7.

Alternatively, the size of the ninth transistor M9, the size of the second transistor M2, and the size of the eleventh transistor M11 are at least 4 times larger than the size of the first transistor M1; the size of the tenth transistor M10 is at least 4 times larger than that of the seventh transistor M7, and the size of the sixth transistor M6 in the second flip-flop 2 is at least 4 times larger than that of the seventh transistor M7.

In some embodiments of the present invention, as shown in fig. 8 and 9, the tenth transistor M10 is a PMOS transistor, and the ninth transistor M9 and the eleventh transistor M11 are NMOS transistors, although the present invention is not limited thereto, and in other embodiments, the tenth transistor M10 may also be an NMOS transistor, and the ninth transistor M9 and the eleventh transistor M11 may also be PMOS transistors.

Of course, in other embodiments of the present invention, in order to ensure stable operation of the dual-mode prescaler, the number of stacked transistors on the critical path may also be relatively increased, as shown in fig. 10, each of the first flip-flop 1 and the second flip-flop 2 includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, and an eighth transistor M8, and connection relationships of the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 are the same as those of the embodiment shown in fig. 6, and are not described herein again.

The first flip-flop 1 further includes a first inverter INV1, an input terminal CLKOB of the first inverter INV1 is connected to a common terminal of the sixth transistor M6 and the eighth transistor M8 in the first flip-flop 1; an output end CLKO of the first inverter INV1 is connected to the gates of the second transistor M2 and the third transistor M3 in the second flip-flop 2;

the dual-mode prescaler further includes a twelfth transistor M12, a thirteenth transistor M13, a fourteenth transistor M14, a fifteenth transistor M15, a sixteenth transistor M16 and a seventeenth transistor M17;

a first terminal of the twelfth transistor M12 is connected to the first terminal of the second transistor M2 in the first flip-flop 1, a second terminal of the twelfth transistor M12 is connected to the second terminal of the second transistor M2 in the first flip-flop 1, and a gate of the twelfth transistor M12 is connected to the input terminal CLKOB of the first inverter INV 1; a first terminal of the thirteenth transistor M13 is connected to the first terminal of the third transistor M3, a second terminal of the thirteenth transistor M13 is grounded, and a gate of the thirteenth transistor M13 is connected to the input terminal CLKOB of the first inverter INV 1;

a first terminal of the fourteenth transistor M14 is connected to the power supply VDD, a second terminal of the fourteenth transistor M14 is connected to the second terminal of the sixth transistor M6 in the second flip-flop 2, and a gate of the fourteenth transistor M14 is connected to the second signal terminal P; a second terminal of the sixth transistor M6 in the second flip-flop 2 is connected to the first terminal of the eighth transistor M8, a first terminal of the fifteenth transistor M15 is connected to the second terminal of the sixth transistor M6 in the second flip-flop 2, a second terminal of the fifteenth transistor M15 is connected to the first terminal of the eighth transistor M8 in the second flip-flop 2, and a gate of the fifteenth transistor M15 is connected to the second signal terminal P;

a first end of a sixteenth transistor M16 is connected with a first end of a second transistor M2 in the second flip-flop 2, a second end of a sixteenth transistor M16 is connected with a second end of a second transistor M2 in the second flip-flop 2, and a gate of the sixteenth transistor M16 is connected with a signal input end MoDin of the dual-mode prescaler; a first end of the seventeenth transistor M17 is connected to the second end of the seventh transistor M7 in the second flip-flop 2, a second end of the seventeenth transistor M17 is grounded, and the seventeenth transistor M17 is connected to the signal input end MoDin of the dual-mode prescaler;

the gates of the second transistor M2 and the third transistor M3 in the first flip-flop 1 are both connected to the second terminal of the sixth transistor M6 in the second flip-flop 2.

Also, since the first-stage dual-mode prescaler does not need to output signals in the frequency divider, that is, the first-stage dual-mode prescaler does not have the signal output terminal MoDout, in some embodiments of the present invention, as shown in fig. 10, the dual-mode prescaler does not have the signal output terminal MoDout. However, since the dual-mode prescalers of other stages need to output signals to the dual-mode prescalers of the previous stage, in some embodiments of the present invention, the dual-mode prescalers have signal output terminals MoDout.

On the basis of the above embodiment, as shown in fig. 11, the dual-mode frequency divider further includes a third inverter INV3, an input end of the third inverter INV3 is connected to the gate of the fifth transistor M5 in the second flip-flop 2, and an output end of the third inverter INV3 is the signal output end MoDout of the dual-mode frequency divider.

Similarly, in some embodiments of the present invention, it is preferable that the first-stage dual-mode prescaler does not have the signal output terminal MoDout, and the other-stage dual-mode prescalers have the signal output terminal MoDout, that is, the first-stage dual-mode prescaler has the structure shown in fig. 10, and the other-stage dual-mode prescalers have the structure shown in fig. 11.

The following explains the operation of the dual mode by taking the structure shown in fig. 8 as an example.

As shown in fig. 12, when MoDin is high and P is high, it is assumed that CLK0 is high, when CLKIN is low, the first transistor M1, the second transistor M2 and the eleventh transistor M11 in the second flip-flop 2 are all turned on, since the sizes of the second transistor M2 and the eleventh transistor M11 are larger than the size of the first transistor M1, the a2 node is pulled down to low, the fifth transistor M5 in the second flip-flop 2 is turned off, and since the fourth transistor M4 in the second flip-flop 2 is turned on, the B2 node is pulled high, so that the second transistor M2 in the first flip-flop 1 is turned on, but since CLKOB is low, the ninth transistor M9 in the first flip-flop 1 is turned off. Since the first transistor M1 in the first flip-flop 1 is turned on, the a1 node is pulled high, so that the fifth transistor M5 in the first flip-flop 1 is turned on. Since the fourth transistor M4 and the fifth transistor M5 in the first flip-flop 1 are both turned on and the size of the fourth transistor M4 is larger than that of the fifth transistor M5, the B1 node is pulled high, so that the sixth transistor M6 is turned off, and since the seventh transistor M7 is turned off, CLKOB is kept low and CLK0 is kept high. During this process, MoDout outputs a low level.

When CLKIN goes high, the first transistor M1 in the second flip-flop 2 turns off, the second transistor M2 and the eleventh transistor M11 turn on, pulling the a2 node low to a low level continuously, and the B2 node remains at a high level because the fourth transistor M4 and the fifth transistor M5 in the second flip-flop 2 both turn off. Since the first transistor M1 and the ninth transistor M9 in the first flip-flop 1 are turned off, the a1 node is maintained at a high level and the fifth transistor M5 in the first flip-flop 1 is continuously turned on. Since the fourth transistor M4 in the first flip-flop 1 is turned off, the B1 node is pulled low to a low level, so that the sixth transistor M6 in the first flip-flop 1 is turned on, CLKOB is pulled high, so that CLK0 is low, so that the second transistor M2 in the second flip-flop 2 is turned off, so that the a2 node is kept at a low level, i.e., MoDout continuously outputs a low level.

When CLKIN goes low again, since the second transistor M2 in the second flip-flop 2 is turned off and the first transistor M1 is turned on, the a2 node is pulled high, so that the fifth transistor M5 in the second flip-flop 2 is turned on. Since both the fourth transistor M4 and the fifth transistor M5 in the second flip-flop 2 are turned on and the size of the fourth transistor M4 is larger than that of the fifth transistor M5, the B2 node continues to be at a high level. Since CLKOB is also high, the first transistor M1, the second transistor M2, and the ninth transistor M9 in the first flip-flop 1 are turned on, pulling the a1 node to a low level, so that the fifth transistor M5 in the first flip-flop 1 is turned off. Since the fourth transistor M4 in the first flip-flop 1 is turned on, the B1 node is pulled to a high level, so that the sixth transistor M6 in the first flip-flop 1 is turned off, and since the seventh transistor M7 in the first flip-flop 1 is turned off, CLKOB is maintained at a high level and CLK0 is maintained at a low level. In this process, MoDout outputs a high level.

When CLKIN goes high again, the first transistor M1 and the second transistor M2 in the second flip-flop 2 are turned off, the a2 node is kept at high level, the fifth transistor M5 in the second flip-flop 2 is continuously turned on, and since the fourth transistor M4 in the second flip-flop 2 is turned off and the seventh transistor M7 is turned on, the B2 node is pulled down to low level, so that the second transistor M2 in the first flip-flop 1 is turned off. Since the first transistor M1 in the first flip-flop 1 is turned off, the a1 node is maintained at a low level, since the fourth transistor M4 and the fifth transistor M5 in the first flip-flop 1 are both turned off, and therefore, the B1 node is maintained at a high level, since the seventh transistor M7 and the eighth transistor M8 in the first flip-flop 1 are both turned on, CLKOB is pulled to a low level, so that CLKO is at a high level, so that the second transistor M2 in the second flip-flop 2 is turned on. Since both the second transistor M2 and the eleventh transistor M11 in the second flip-flop 2 are turned on, the a2 node is pulled to a low level. During this process, MoDout outputs a low level.

When CLKIN goes low again, the same procedure as above is repeated.

That is, when MoDin is high and P is high, the frequency of MoDout is one third of the frequency of CLKIN.

When MoDin is low and P is high, as shown in fig. 13, CLK0 is high, when CLKIN is low, the first transistor M1 in the second flip-flop 2 is turned on to pull the a2 node high, and the B2 node is high because the fourth transistor M4 and the fifth transistor M5 in the second flip-flop 2 are both turned on. Since CLKOB is at a low level, the ninth transistor M9 in the first flip-flop 1 is turned off, and the first transistor M1 in the first flip-flop 1 is turned on, so the a1 node is at a high level, and since the fourth transistor M4 and the fifth transistor M5 in the first flip-flop 1 are both turned on, the B1 node is at a high level, CLKOB is maintained at a low level, and CLK0 is maintained at a high level. In this process, MoDout outputs a high level.

When CLKIN becomes high, the a2 node remains high, and the B2 node is pulled low due to the fourth transistor M4 being off, the fifth transistor M5 being on, and the seventh transistor M7 being on in the second flip-flop 2. Since the first transistor M1 and the second transistor M2 in the first flip-flop 1 are both turned off, the a1 node is maintained at a high level, and since the fourth transistor M4 in the first flip-flop 1 is turned off and the fifth transistor M5 is turned on, the B1 node is pulled to a low level, the sixth transistor M6 in the first flip-flop 1 is turned on and the eighth transistor M8 is turned off, so that CLKOB is at a high level and CLK0 is at a low level, and the a2 node is maintained at a high level. In this process, MoDout outputs a high level.

When CLKIN goes low again, the a2 node continues to be high, and since the fourth transistor M4 and the fifth transistor M5 in the second flip-flop 2 are both turned on, the B2 node continues to be high, so that the second transistor M2 in the first flip-flop 1 is turned on. Since CLKOB is at a high level, the ninth transistor M9 in the first flip-flop 1 is turned on, and the first transistor M1 in the first flip-flop 1 is also turned on, so that the a1 node is pulled to a low level, the B1 node is pulled to a high level by the turned-on fourth transistor M4 in the first flip-flop 1, the ob is maintained at a high level, and the CLK0 is maintained at a low level. In this process, MoDout outputs a high level.

When CLKIN goes high again, the a2 node stays high, the B2 is pulled low, the a1 node stays low, the B1 node stays high, CLKOB is pulled low, and CLK0 goes high. In this process, MoDout outputs a high level.

When CLKIN goes low again, the previous process is repeated, which is not described in detail herein.

That is, when MoDin is low and P is high, MoDout continues to output high.

Similarly, when MoDin is low and P is low, as shown in fig. 13, MoDout continues to output high. When MoDin is high and P is low, the frequency of MoDout is one-half of the frequency of CLKIN, as shown in fig. 14.

Under the same input conditions, the output structures of the structures shown in fig. 9 to 11 are the same as the output results of the structure shown in fig. 8, and are not described in detail here.

In some embodiments of the present invention, the logic control circuit in the dual-mode prescaler is integrated with the flip-flop to reduce the number of transistors, reduce the cost, AND increase the operation speed, as shown in fig. 8 AND 9, the second transistor M2 AND the ninth transistor M9 form a nand gate, which in turn forms an AND gate with the fourth transistor M4 AND the fifth transistor M5, that is, the second transistor M2, the fourth transistor M4, the fourth fifth transistor M5, AND the ninth transistor M9 in the first flip-flop 1 form an AND gate, the first transistor M1, the second transistor M2, the fourth transistor M4, the fourth fifth transistor M5, AND the ninth transistor M9 in the first flip-flop 1 form a Latch1, that is, the first transistor M1, the second transistor M2, the fourth transistor M4, the fourth fifth transistor M5, AND the ninth transistor M68642 in the first flip-flop 1 realize the functions of the AND gate 1 AND gate 1 in fig. 1, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, AND the first inverter INV1 in the first flip-flop 1 implement the function of the Latch2 in fig. 1, AND similarly, the first transistor M1, the second transistor M2, the eleventh transistor M11, the fourth transistor M4, AND the fifth transistor M5 in the second flip-flop 2 implement the functions of the AND gate 2 AND the Latch3 in fig. 1, AND the sixth transistor M6, the seventh transistor M7, AND the tenth transistor M10 in the second flip-flop 2 implement the functions of the AND gate 3 AND the Latch4 in fig. 1.

Of course, in other embodiments of the present invention, as shown in fig. 10 AND 11, the second transistor M2, the third transistor M3, the twelfth transistor M12 AND the thirteenth transistor M13 in the first flip-flop 1 form a nand gate, which in turn forms an AND gate with the fourth transistor M4 AND the fifth transistor M5, that is, the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the twelfth transistor M12 AND the thirteenth transistor M13 in the first flip-flop 1 implement the functions of the AND gate 1 AND the Latch1 in fig. 1, the sixth transistor M6, the seventh transistor M639, the eighth transistor M8 AND the first inverter INV1 in the first flip-flop 1 implement the functions of the Latch2 in fig. 1, AND the first transistor M1, the third transistor M2, the eighth transistor M6867, the fourth transistor M8687458 AND the fifth transistor M5 AND the fifth transistor M5 in the second flip-flop 2 implement the functions of the Latch1, The sixteenth transistor M16 AND the seventeenth transistor M17 realize functions of the AND gate AND2 AND the Latch3 in fig. 1, AND the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, the fourteenth transistor M14, AND the fifteenth transistor M15 in the second flip-flop 2 realize functions of the AND gate AND3 AND the Latch4 in fig. 1.

The embodiment of the invention also provides a frequency divider, which comprises a plurality of cascaded dual-mode prescalers, wherein the dual-mode prescalers comprise the dual-mode prescalers provided by any one of the embodiments.

As shown in fig. 15, the dual-mode prescaler includes a dual-mode prescaler 1 to a dual-mode prescaler n, a CLK0 end of a previous dual-mode prescaler is connected to a CLKIN end of a next dual-mode prescaler, for example, a CLK01 end of the dual-mode prescaler 1 is connected to a CLKIN end of the dual-mode prescaler 2, a MODOUT end of a next dual-mode prescaler is connected to a MODIN end of the previous dual-mode prescaler, for example, a MODOUT1 end of the dual-mode prescaler 2 is connected to a MODIN end of the.

When the frequency divider works, the first-stage dual-mode prescaler 1 can realize a two-frequency division mode or a three-frequency division mode under the control of signals received by the P terminal and the MoDin terminal, and based on the two-frequency division mode or the three-frequency division mode, the initial signals are subjected to frequency reduction at different frequency division ratios by setting signals of the P terminal and the MoDin terminal.

An embodiment of the present invention further provides an integrated circuit, including the frequency divider provided in any of the above embodiments. In some embodiments of the present invention, the integrated circuit may constitute a radar chip, and optionally, the integrated circuit is a millimeter wave radar chip, but the present invention is not limited thereto, and in other embodiments, the integrated circuit may also be a radar chip in other bands. In addition, the integrated circuit in the embodiment of the present invention may also constitute other communication chips, sensors, or detection devices, and the like, which are not described herein again.

Embodiments of the present invention further provide a radio device, including a carrier, an integrated circuit, and an antenna, where the integrated circuit is the integrated circuit provided in the above embodiments, and the integrated circuit is disposed on the carrier. The antenna is arranged on the carrier or integrated in the package of the integrated circuit, and the integrated circuit is connected to the antenna for transceiving antenna electrical signals.

The embodiment of the invention also provides equipment which comprises an equipment body and the radio device arranged on the equipment body, wherein the radio device is used for target detection and/or communication.

The carrier can be a vehicle (such as various types of automobiles, ships, intercity rail transit and the like), an intelligent device (such as a mobile phone, an air conditioner and the like), a security device (such as subway security inspection, airport security inspection and the like), a traffic auxiliary device (such as a barrier gate), an industrial automation device and the like.

The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A TSPC flip-flop comprising a first level of structure;

2. The TSPC flip-flop of claim 1, wherein a size of the second transistor is at least 4 times larger than a size of the first transistor.

3. The TSPC flip-flop of claim 1, wherein the first stage structure further comprises a third transistor, a second terminal of the first transistor coupled to a first terminal of the second transistor through the third transistor;

a gate of the third transistor is coupled to the first signal terminal.

4. A TSPC flip-flop according to claim 1 or 3, further comprising a second level structure connected to said first level structure;

5. A TSPC flip-flop according to claim 4, further comprising a third level structure connected to the second level structure;

6. A TSPC flip-flop according to claim 5, wherein the size of the fourth transistor is at least 4 times larger than the size of the fifth transistor; and/or the presence of a gas in the gas,

7. The TSPC flip-flop of claim 5, wherein the third stage further comprises an eighth transistor, wherein the second terminal of the sixth transistor is connected to the first terminal of the seventh transistor through the eighth transistor; and

8. A dual-modulus prescaler comprising a first flip-flop and a second flip-flop, the first flip-flop comprising the TSPC flip-flop of any one of claims 1 to 7, and/or,

the second flip-flop comprises a TSPC flip-flop of any of claims 1-7.

9. The dual-modulus prescaler of claim 8, wherein the second flip-flop comprises the first transistor, the second transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor;

a first end of the tenth transistor is connected with a power supply, a second end of the tenth transistor is connected with a second end of a sixth transistor in the second trigger, and a grid electrode of the tenth transistor is connected with a second signal end; and

10. The dual-modulus prescaler of claim 9, wherein the first flip-flop comprises the first transistor, the second transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor;

a first end of the ninth transistor is connected with a second end of the second transistor in the first trigger, a second end of the ninth transistor is grounded, and a grid electrode of the ninth transistor is connected with an input end of the first inverter; and

11. The dual-modulus prescaler of claim 10, further comprising a second inverter, wherein an input of the second inverter is connected to a gate of a fifth transistor in the second flip-flop, and an output of the second inverter is a signal output of the dual-modulus divider.

12. The dual-modulus prescaler of claim 10, wherein the size of the ninth transistor, the size of the second transistor, and the size of the eleventh transistor is at least 4 times the size of the first transistor;

13. The dual-modulus prescaler of claim 8, wherein the first flip-flop comprises the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor;

the input end of the first inverter is connected with the common end of a sixth transistor and an eighth transistor in the first trigger; the output end of the first inverter is connected with the grid electrode of the second transistor and the grid electrode of the third transistor in the second trigger; and

14. The dual-modulus prescaler of claim 13,

the second flip-flop includes the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor;

a first end of the fourteenth transistor is connected with a power supply, a second end of the fourteenth transistor is connected with a second end of a sixth transistor in the second trigger, and a gate of the fourteenth transistor is connected with a second signal end; a second end of a sixth transistor in the second trigger is connected with a first end of an eighth transistor, a first end of a fifteenth transistor is connected with a second end of the sixth transistor in the second trigger, a second end of the fifteenth transistor is connected with a first end of an eighth transistor in the second trigger, and a gate of the fifteenth transistor is connected with the second signal end; and

15. The dual-modulus prescaler of claim 14, further comprising a third inverter, wherein an input of the third inverter is connected to a gate of a fifth transistor in the second flip-flop, and an output of the third inverter is a signal output of the dual-modulus divider.

16. A frequency divider comprising a plurality of cascaded dual-modulus prescalers, the dual-modulus prescalers comprising the dual-modulus prescaler of any one of claims 8 to 15.

17. An integrated circuit, comprising:

the frequency divider of claim 16.

18. The integrated circuit of claim 17, wherein the integrated circuit is a millimeter wave radar chip.

19. A radio device, comprising:

a carrier;

the integrated circuit of claim 17 or 18, disposed on the carrier; and

20. An apparatus, comprising:

an apparatus body; and

the radio of claim 19 disposed on the equipment body;

wherein the radio device is used for object detection and/or communication.