CN112260682B - TSPC flip-flop, dual mode prescaler and divider related device - Google Patents

TSPC flip-flop, dual mode prescaler and divider related device Download PDF

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CN112260682B
CN112260682B CN202011155433.6A CN202011155433A CN112260682B CN 112260682 B CN112260682 B CN 112260682B CN 202011155433 A CN202011155433 A CN 202011155433A CN 112260682 B CN112260682 B CN 112260682B
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transistor
flop
flip
trigger
size
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CN112260682A (en
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杨建伟
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Calterah Semiconductor Technology Shanghai Co Ltd
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Calterah Semiconductor Technology Shanghai Co Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/40—Gating or clocking signals applied to all stages, i.e. synchronous counters
    • H03K23/42—Out-of-phase gating or clocking signals applied to counter stages
    • H03K23/44—Out-of-phase gating or clocking signals applied to counter stages using field-effect transistors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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Abstract

The invention provides a TSPC trigger, a dual-mode prescaler and a frequency divider, which comprise a first stage structure; the first stage structure comprises a first transistor and a second transistor, and the size of the second transistor is larger than that of the first transistor; the first end of the first transistor is connected with a power supply, the grid electrode of the first transistor is connected with a clock signal end, the second end of the first transistor is connected with the first end of the second transistor, the second end of the second transistor is grounded, and the grid electrode of the second transistor is connected with a first signal end. Compared with the prior art, the transistor connected with the clock signal end, namely the first transistor, is closer to the power supply, and after the clock signal input by the clock signal end controls the first transistor to be conducted, the power supply voltage can be transmitted to the output end of the first stage structure more quickly, so that the working speeds of the TSPC trigger, the dual-mode prescaler and the frequency divider are improved.

Description

TSPC flip-flop, dual mode prescaler and divider related device
Technical Field
The present invention relates to the field of digital circuits, and more particularly to a TSPC flip-flop, a dual mode prescaler, and a divider related device.
Background
Frequency dividers are commonly used to convert a high frequency clock signal to a low frequency clock signal. The conventional frequency divider includes a plurality of cascaded dual mode prescalers which selectively divide by 2/3 according to a frequency division mode control signal. The high frequency clock signal may be converted to a low frequency clock signal of a specified frequency division multiple by separately controlling each of the plurality of cascaded dual-mode prescalers to divide by 2/3.
As shown in fig. 1, a conventional dual-mode prescaler includes 4 latches Latch1 to Latch4 AND three AND gates AND1 to AND3, wherein the Latch1 AND the Latch2 form one TSPC (True Single Phase Clock, true single-phase clock) trigger, the Latch3 AND the Latch4 form another TSPC trigger, CLKIN is an input clock signal, CLKO is an output clock signal, moDin is an input mode control signal, moDout is an output mode control signal, AND P is a control signal. When modin=0 or modin=1, p=0, the dual-mode prescaler operates in the divide-by-2 state, and CLKO has a frequency of 1/2 of CLKIN; when modin=1, p=1, the dual mode prescaler operates in the divide-by-3 state, with CLKO having a frequency of 1/3 of CLKIN. However, since the operation speed of the TSPC flip-flop in the dual mode prescaler is low, the operation speed of the dual mode prescaler is low.
Disclosure of Invention
In view of the above, the present invention provides a TSPC flip-flop, a dual mode prescaler, and a divider to increase the operating speed of the TSPC flip-flop.
In order to achieve the above purpose, the present invention provides the following technical solutions:
a TSPC trigger comprising a first stage structure;
the first stage structure comprises a first transistor and a second transistor, and the size of the second transistor is larger than that of the first transistor;
the first end of the first transistor is connected with a power supply, the grid electrode of the first transistor is connected with a clock signal end, the second end of the first transistor is connected with the first end of the second transistor, the second end of the second transistor is grounded, and the grid electrode of the second transistor is connected with a first signal end.
Optionally, the second transistor has a size at least 4 times larger than the size of the first transistor.
Optionally, the first stage structure further includes a third transistor, and the second end of the first transistor is connected to the first end of the second transistor through the third transistor; the gate of the third transistor is connected to the first signal terminal.
Optionally, a second stage structure connected to the first stage structure;
The second-stage structure comprises a fourth transistor and a fifth transistor, wherein the size of the fourth transistor is larger than that of the fifth transistor;
the first end of the fourth transistor is connected with a power supply, the grid electrode of the fourth transistor is connected with the clock signal end, the second end of the fourth transistor is connected with the first end of the fifth transistor, the second end of the fifth transistor is grounded, and the grid electrode of the fifth transistor is connected with the common end of the second transistor and the third transistor.
Optionally, a third level structure connected to the second level structure;
the third stage structure includes a sixth transistor and a seventh transistor, the sixth transistor having a size that is larger than the size of the seventh transistor;
the first end of the sixth transistor is connected with a power supply, the second end of the sixth transistor is connected with the first end of the seventh transistor, the grid electrode of the sixth transistor is connected with the common end of the fourth transistor and the fifth transistor, the second end of the seventh transistor is grounded, and the grid electrode of the seventh transistor is connected with the clock signal end.
Optionally, the size of the fourth transistor is at least 4 times larger than the size of the fifth transistor; and/or the number of the groups of groups,
The size of the sixth transistor is at least 4 times larger than the size of the seventh transistor.
Optionally, the third stage structure further includes an eighth transistor, and the second end of the sixth transistor is connected to the first end of the seventh transistor through the eighth transistor;
the first end of the eighth transistor is connected with the second end of the sixth transistor, the second end of the eighth transistor is connected with the first end of the seventh transistor, and the grid electrode of the eighth transistor is connected with the common end of the fourth transistor and the fifth transistor.
A dual mode prescaler comprising a first flip-flop comprising the TSPC flip-flop of any of the preceding claims and/or a second flip-flop comprising the TSPC flip-flop of any of the preceding claims.
Optionally, the second flip-flop includes the first transistor, the second transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor;
the dual mode prescaler further comprises a tenth transistor and an eleventh transistor;
the first end of the tenth transistor is connected with a power supply, the second end of the tenth transistor is connected with the second end of the sixth transistor in the second trigger, and the grid electrode of the tenth transistor is connected with a second signal end;
The first end of the eleventh transistor is connected with the second end of the second transistor in the second trigger, the second end of the eleventh transistor is grounded, and the grid electrode of the eleventh transistor is connected with the signal input end of the dual-mode frequency divider.
Optionally, the first flip-flop includes the first transistor, the second transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor;
the dual-mode prescaler further comprises a first inverter and a ninth transistor;
an input end of the first inverter is connected with a common end of the sixth transistor and the eighth transistor; the output end of the first inverter is connected with the grid electrode of the second transistor in the second trigger;
a first end of the ninth transistor is connected with a second end of a second transistor in the first trigger, a second end of the ninth transistor is grounded, and a grid electrode of the ninth transistor is connected with an input end of the first inverter;
the grid electrode of the second transistor in the first trigger is connected with the second end of the sixth transistor in the second trigger, and the second end of the sixth transistor in the second trigger is connected with the grid electrode of the sixth transistor in the second trigger;
Wherein the size of the ninth transistor, the second transistor, and the eleventh transistor is larger than the size of the first transistor, and the size of the tenth transistor and the size of the sixth transistor in the second flip-flop are larger than the size of the seventh transistor.
Optionally, the circuit further comprises a second inverter, wherein the input end of the second inverter is connected with the gate electrode of the fifth transistor in the second trigger, and the output end of the second inverter is the signal output end of the dual-mode frequency divider.
Optionally, the size of the ninth transistor, the size of the second transistor, and the size of the eleventh transistor are at least 4 times the size of the first transistor;
the size of the tenth transistor is at least 4 times that of the seventh transistor, and the size of the sixth transistor in the second flip-flop is at least 4 times that of the seventh transistor.
Optionally, the first flip-flop includes the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor;
The dual mode prescaler further comprises a first inverter, a twelfth transistor, and a thirteenth transistor;
the input end of the first inverter is connected with the common end of the sixth transistor and the eighth transistor in the first trigger; the output end of the first inverter is connected with the grid electrode of the second transistor and the grid electrode of the third transistor in the second trigger;
a first end of the twelfth transistor is connected with the first end of the second transistor, a second end of the twelfth transistor is connected with the second end of the second transistor, and a grid electrode of the twelfth transistor is connected with the input end of the first inverter; a first terminal of the thirteenth transistor is connected to the first terminal of the third transistor, a second terminal of the thirteenth transistor is grounded, and a gate of the thirteenth transistor is connected to the input terminal of the first inverter.
Optionally, the second flip-flop includes the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor;
the dual mode prescaler further comprises a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, and a seventeenth transistor;
The first end of the fourteenth transistor is connected with a power supply, the second end of the fourteenth transistor is connected with the second end of the sixth transistor in the second trigger, and the grid electrode of the fourteenth transistor is connected with a second signal end; the second end of the sixth transistor in the second trigger is connected with the first end of the eighth transistor, the first end of the fifteenth transistor is connected with the second end of the sixth transistor in the second trigger, the second end of the fifteenth transistor is connected with the first end of the eighth transistor in the second trigger, and the grid electrode of the fifteenth transistor is connected with the second signal end;
the first end of the sixteenth transistor is connected with the first end of the second transistor in the second trigger, the second end of the sixteenth transistor is connected with the second end of the second transistor, and the grid electrode of the sixteenth transistor is connected with the signal input end of the dual-mode prescaler; a first end of the seventeenth transistor is connected with a second end of a seventh transistor in the second trigger, a second end of the seventeenth transistor is grounded, and the seventeenth transistor is connected with a signal input end of the dual-mode prescaler;
The gates of the second transistor and the third transistor in the first trigger are connected with the second end of the sixth transistor in the second trigger.
Optionally, the input end of the third inverter is connected with the gate electrode of the fifth transistor in the second trigger, and the output end of the third inverter is the signal output end of the dual-mode frequency divider.
A frequency divider comprising a plurality of cascaded dual mode prescalers, the dual mode prescalers comprising the dual mode prescaler of any of the preceding claims.
An integrated circuit, comprising:
such as the frequency divider described above.
Optionally, the integrated circuit is a millimeter wave radar chip.
A radio device comprising:
a carrier;
an integrated circuit as described above, disposed on the carrier;
an antenna disposed on the carrier or integrated in the package of the integrated circuit;
the integrated circuit is connected with the antenna and is used for receiving and transmitting radio signals.
An apparatus, comprising:
an equipment body; and
a radio device as described above disposed on the apparatus body;
wherein the radio device is used for target detection and/or communication.
Compared with the prior art, the technical scheme provided by the invention has the following advantages:
compared with the prior art, the TSPC trigger, the dual-mode prescaler and the frequency divider have the advantages that the first end of the first transistor connected with the clock signal end is connected with the power supply, so that the transistor connected with the clock signal end, namely the first transistor, is closer to the power supply, and after the clock signal input by the clock signal end controls the first transistor to be conducted, the power supply voltage is transmitted to the output end of the first stage structure, namely the second end of the first transistor, so that the working speed of the TSPC trigger, the dual-mode prescaler and the frequency divider is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present invention, and that other drawings can be obtained according to the provided drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a prior art dual-mode prescaler;
FIG. 2 is a schematic diagram of a TSPC flip-flop in the dual mode prescaler of FIG. 1;
FIG. 3 is a schematic diagram of a TSPC trigger according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a TSPC trigger according to another embodiment of the present invention;
fig. 5 is a schematic structural diagram of a TSPC trigger according to another embodiment of the present invention;
fig. 6 is a schematic structural diagram of a TSPC trigger according to another embodiment of the present invention;
FIG. 7 is a timing diagram of a TSPC trigger according to one embodiment of the present invention;
FIG. 8 is a schematic diagram of a dual-mode prescaler according to an embodiment of the present invention;
FIG. 9 is a schematic diagram of a dual-mode prescaler according to another embodiment of the present invention;
FIG. 10 is a schematic diagram of a dual-mode prescaler according to another embodiment of the present invention;
FIG. 11 is a schematic diagram of a dual-mode prescaler according to another embodiment of the present invention;
FIG. 12 is a timing diagram of a dual-mode prescaler according to an embodiment of the present invention when MoDin is high and P is high;
FIG. 13 is a timing diagram of a dual-mode prescaler according to an embodiment of the present invention when MoDin is low;
FIG. 14 is a timing diagram of a dual-mode prescaler according to an embodiment of the present invention when MoDin is high and P is low;
fig. 15 is a schematic diagram of a plurality of cascaded dual-mode prescalers according to an embodiment of the present invention.
Detailed Description
As background, the lower operating speed of existing TSPC flip-flops results in lower operating speeds of the dual mode prescaler and the divider. As shown in fig. 2, fig. 2 is a schematic diagram of a structure of a TSPC flip-flop in the dual-mode prescaler shown in fig. 1, including transistors P1 to P9, and the inventor has studied that when clk=1 makes transistor P2 conductive, the voltage of power supply VDD needs to be transmitted to the common terminal of transistor P1 and transistor P2 and then transmitted through the conductive transistor P2, which results in a lower operation speed of the TSPC flip-flop.
Accordingly, the present invention has been made to overcome the above-mentioned problems occurring in the prior art by providing a TSPC flip-flop, a dual mode prescaler, and a divider, the TSPC flip-flop including a first stage structure;
the first stage structure comprises a first transistor and a second transistor, and the size of the second transistor is larger than that of the first transistor;
the first end of the first transistor is connected with a power supply, the grid electrode of the first transistor is connected with a clock signal end, the second end of the first transistor is connected with the first end of the second transistor, the second end of the second transistor is grounded, and the grid electrode of the second transistor is connected with a first signal end.
Compared with the prior art shown in fig. 2, the TSPC trigger, the dual-mode prescaler and the frequency divider have the advantages that the first end of the first transistor connected with the clock signal end is connected with the power supply, so that the transistor connected with the clock signal end, namely the first transistor, is closer to the power supply, and after the clock signal input by the clock signal end controls the first transistor to be conducted, the power supply voltage is transmitted to the output end of the first stage structure, namely the second end of the first transistor, so that the working speed of the TSPC trigger, the dual-mode prescaler and the frequency divider is improved.
The foregoing is a core idea of the present invention, and in order that the above-mentioned objects, features and advantages of the present invention can be more clearly understood, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The embodiment of the invention provides a TSPC trigger, as shown in FIG. 3, which comprises a first stage structure 11, wherein the first stage structure 11 comprises a first transistor M1 and a second transistor M2, and the size of the second transistor M2 is larger than that of the first transistor M1.
The first end of the first transistor M1 is connected to the power supply VDD, the gate of the first transistor M1 is connected to the clock signal terminal CLKIN, the second end of the first transistor M1 is connected to the first end of the second transistor M2, the second end of the second transistor M2 is grounded, and the gate of the second transistor M2 is connected to the first signal terminal DIN.
Because the first end of the first transistor M1 connected to the clock signal end CLKIN is connected to the power supply VDD, compared with the prior art shown in fig. 2, the transistor connected to the clock signal end CLKIN in the embodiment of the invention, that is, the first transistor M1 is closer to the power supply VDD, and after the clock signal input by the clock signal end CLKIN controls the first transistor M1 to be turned on, the voltage of the power supply VDD is faster transmitted to the output end of the first stage structure 11, that is, the second end of the first transistor, so that the working speeds of the TSPC trigger, the dual-mode prescaler and the frequency divider are improved.
In some embodiments of the present invention, as shown in FIG. 3, the TSPC trigger further includes a second stage structure 12 coupled to the first stage structure 11; the second stage structure 12 includes a fourth transistor M4 and a fifth transistor M5, the fourth transistor M4 having a size larger than the fifth transistor M5.
The first end of the fourth transistor M4 is connected to the power supply VDD, the gate of the fourth transistor M4 is connected to the clock signal terminal CLKIN, the second end of the fourth transistor M4 is connected to the first end of the fifth transistor M5, the second end of the fifth transistor M5 is grounded, and the gate of the fifth transistor M5 is connected to the common terminal of the second transistor M2 and the third transistor M3.
In some embodiments of the present invention, as shown in FIG. 3, the TSPC trigger further includes a third stage structure 13 coupled to the second stage structure 12; the third stage structure 13 includes a sixth transistor M6 and a seventh transistor M7, the size of the seventh transistor M7 being larger than the size of the sixth transistor M6.
The first terminal of the sixth transistor M6 is connected to the power supply VDD, the second terminal of the sixth transistor M6 is connected to the first terminal of the seventh transistor M7, the gate of the sixth transistor M6 is connected to the common terminal of the fourth transistor M4 and the fifth transistor M5, the second terminal of the seventh transistor M7 is grounded, and the gate of the seventh transistor M7 is connected to the clock signal terminal CLKIN. And, the output terminal DOUT of the TSPC flip-flop is connected to the second terminal of the sixth transistor M6 and the first terminal of the seventh transistor M7.
It should be noted that, in the embodiment of the present invention, in order to ensure that when the first transistor M1 and the second transistor M2 are turned on simultaneously under all process conditions, the low level at the point a is sufficient to control the fifth transistor M5 to be turned off, so that the size of the second transistor M2 is larger than that of the first transistor M1; to ensure that the high level at point B is sufficient to control the sixth transistor M6 to turn off when the fourth transistor M4 and the fifth transistor M5 are simultaneously turned on under all process conditions, the size of the fourth transistor M4 is therefore larger than the size of the fifth transistor M5; in order to ensure that the output CLKINOB output satisfies the required high level when the sixth transistor M6 and the seventh transistor M7 are simultaneously turned on under all process conditions, the size of the sixth transistor M6 is larger than the size of the seventh transistor M7.
Further alternatively, the size of the second transistor M2 is at least 4 times larger than the size of the first transistor M1; and/or the fourth transistor M4 has a size at least 4 times larger than the size of the fifth transistor M5; and/or the size of the sixth transistor M6 is at least 4 times larger than the size of the seventh transistor M7.
It should be noted that, in the embodiment of the present invention, the dimensions of the transistor include the length and width of the transistor channel. Alternatively, the size of the second transistor M2 may be at least 4 times greater than the size of the first transistor M1, the channel width of the second transistor M2 may be at least 4 times greater than the channel width of the first transistor M1, the channel length of the second transistor M2 may be at least 4 times greater than the channel length of the first transistor M1, or the channel length of the second transistor M2 may be at least 4 times greater than the channel length of the first transistor M1, and the channel width of the second transistor M2 may be at least 4 times greater than the channel width of the first transistor M1. The dimensional relationships between the fourth transistor M4 and the fifth transistor M5 and between the sixth transistor M6 and the seventh transistor M7 are the same, and will not be described in detail here.
The simulation shows that the key factor limiting the operating speed of the flip-flop in fig. 2 is the discharge speed from point B to ground, so that the transistor P6 in fig. 2 is omitted from the second stage structure 12 in fig. 3, and the operating speed of the flip-flop is improved on the basis of reducing power consumption, compared with the flip-flop in fig. 2.
Since the discharge rate of the output DOUT to ground is not a critical factor in limiting the operation rate of the flip-flop, the transistor P9 in FIG. 2 has been omitted from the third stage structure 13 shown in FIG. 3 to further reduce the power consumption of the flip-flop. Of course, the present invention is not limited thereto, and in other embodiments of the present invention, the transistor P9 in fig. 2 may not be omitted in order to ensure the stability of the third stage structure 13.
As shown in fig. 4, the third stage 13 further includes an eighth transistor M8, and the second terminal of the sixth transistor M6 is connected to the first terminal of the seventh transistor M7 through the eighth transistor M8.
The first terminal of the eighth transistor M8 is connected to the second terminal of the sixth transistor M6, the second terminal of the eighth transistor M8 is connected to the first terminal of the seventh transistor M7, and the gate of the eighth transistor M8 is connected to the common terminal of the fourth transistor M4 and the fifth transistor M5.
Compared with the flip-flop shown in fig. 2, the transistor P1 in fig. 2 is omitted from the first stage 11 of the flip-flop shown in fig. 3, so as to further increase the operation speed of the flip-flop and reduce the power consumption of the flip-flop on the basis of increasing the operation speed of the flip-flop. Of course, the present invention is not limited thereto, and in other embodiments of the present invention, the transistor P1 in fig. 2 may not be omitted in order to ensure the stability of the first stage structure 11.
As shown in fig. 5 and 6, the first stage 11 further includes a third transistor M3, and the second terminal of the first transistor M1 is connected to the first terminal of the second transistor M2 through the third transistor M3.
The first terminal of the third transistor M3 is connected to the second terminal of the first transistor M1, the second terminal of the third transistor M3 is connected to the first terminal of the second transistor M2, and the gate of the third transistor M3 is connected to the first signal terminal DIN.
In some embodiments of the present invention, as shown in fig. 3 to 6, the first transistor M1, the third transistor M3, the fourth transistor M4 and the sixth transistor M6 are PMOS transistors, and the second transistor M2, the fifth transistor M5, the seventh transistor M7 and the eighth transistor M8 are NMOS transistors. Of course, the present invention is not limited thereto, and in other embodiments, the first transistor M1, the third transistor M3, the fourth transistor M4 and the sixth transistor M6 may be NMOS transistors, and the second transistor M2, the fifth transistor M5, the seventh transistor M7 and the eighth transistor M8 may be PMOS transistors.
The operation of the TSPC flip-flop will be described below by taking the configuration shown in fig. 3 as an example.
As shown in fig. 7, when the first signal terminal DIN is at a low level and the clock signal terminal CLKIN is at a low level, the first transistor M1 is turned on, the fourth transistor M4 is turned on, the second transistor M2 is turned off, the seventh transistor M7 is turned off, and the high level of the power supply VDD is transmitted to the point a through the turned-on first transistor M1, so that the fifth transistor M5 is turned on. Since the fourth transistor M4 is turned on and the size of the fourth transistor M4 is larger than the size of the fifth transistor M5, the turned-on fourth transistor M4 pulls the point B to the high level, so that the sixth transistor M6 is turned off, and the high level of the point B is directly transmitted to the output terminal CLKINOB.
When the first signal terminal DIN is at a low level and the clock signal terminal CLKIN is at a high level, the first transistor M1, the second transistor M2 and the fourth transistor M4 are turned off, the seventh transistor M7 is turned on, the point a is kept at a high level, the fifth transistor M5 is continuously turned on, so that the point B is pulled to a low level, and the sixth transistor M6 is turned on. Since the size of the sixth transistor M6 is larger than that of the seventh transistor M7, the output terminal CLKINOB continuously outputs a high level.
When the first signal terminal DIN is at a high level and the clock signal terminal CLKIN is at a low level, the first transistor M1 is turned on, the second transistor M2 is turned on, the fourth transistor M4 is turned on, and the seventh transistor M7 is turned off. Since the size of the second transistor M2 is larger than that of the first transistor M1, the turned-on second transistor M2 pulls the point a low to a low level, so that the fifth transistor M5 is turned off. Since the fourth transistor M4 is turned on, the point B is pulled high to a high level, so that the sixth transistor M6 is turned off. Since both the sixth transistor M6 and the seventh transistor M7 are turned off, a high level of the B point is transmitted to the output terminal CLKINOB.
When the first signal terminal DIN is at a high level and the clock signal terminal CLKIN is at a high level, the first transistor M1 is turned off, the second transistor M2 is turned on, the fourth transistor M4 is turned off, and the seventh transistor M7 is turned on. The turned-on second transistor M2 continuously pulls the point a low to a low level, so that the fifth transistor M5 is turned off. Since the fourth transistor M4 and the fifth transistor M5 are turned off, the point B is maintained at a high level, so that the sixth transistor M6 is turned off. Since the seventh transistor M7 is turned on, the output terminal CLKINOB is pulled to a low level.
In the structure shown in fig. 5, the timings of the first signal terminal DIN, the clock signal terminal CLKIN, the point a, the point B, and the output terminal CLKINOB are the same as those of the structure shown in fig. 3, and detailed processes are not repeated here.
In the structure shown in fig. 4, as shown in fig. 7, when the first signal terminal DIN is at a low level and the clock signal terminal CLKIN is at a low level, the first transistor M1 is turned on, the fourth transistor M4 is turned on, the second transistor M2 is turned off, the seventh transistor M7 is turned off, and the high level of the power supply VDD is transmitted to the point a through the turned-on first transistor M1, so that the fifth transistor M5 is turned on. Since the fourth transistor M4 is turned on and the size of the fourth transistor M4 is larger than that of the fifth transistor M5, the turned-on fourth transistor M4 pulls the point B to a high level, so that the sixth transistor M6 is turned off, so that the output terminal CLKINOB is maintained in an initial state.
When the first signal terminal DIN is at a low level and the clock signal terminal CLKIN is at a high level, the first transistor M1, the second transistor M2 and the fourth transistor M4 are turned off, the seventh transistor M7 is turned on, the point a is kept at a high level, the fifth transistor M5 is continuously turned on, so that the point B is pulled to a low level, and the sixth transistor M6 is turned on. The high level of the power supply VDD is transmitted to the output terminal CLKINOB through the turned-on sixth transistor M6.
When the first signal terminal DIN is at a high level and the clock signal terminal CLKIN is at a low level, the first transistor M1 is turned on, the second transistor M2 is turned on, the fourth transistor M4 is turned on, and the seventh transistor M7 is turned off. Since the size of the second transistor M2 is larger than that of the first transistor M1, the turned-on second transistor M2 pulls the point a low to a low level, so that the fifth transistor M5 is turned off. Since the fourth transistor M4 is turned on, the point B is pulled high to a high level, so that the sixth transistor M6 is turned off. Since both the sixth transistor M6 and the seventh transistor M7 are turned off, the output terminal CLKINOB is maintained at a high level.
When the first signal terminal DIN is at a high level and the clock signal terminal CLKIN is at a high level, the first transistor M1 is turned off, the second transistor M2 is turned on, the fourth transistor M4 is turned off, and the seventh transistor M7 is turned on. The turned-on second transistor M2 continuously pulls the point a low to a low level, so that the fifth transistor M5 is turned off. Since the fourth transistor M4 and the fifth transistor M5 are turned off, the point B is maintained at a high level, so that the sixth transistor M6 is turned off. Since both the seventh transistor M7 and the eighth transistor M8 are turned on, the output terminal CLKINOB is pulled to a low level.
In the structure shown in fig. 6, the timings of the first signal terminal DIN, the clock signal terminal CLKIN, the point a, the point B, and the output terminal CLKINOB are the same as those of the structure shown in fig. 4, and detailed processes are not repeated here.
The embodiment of the invention also provides a dual-mode prescaler, which comprises a first trigger and a second trigger, wherein the first trigger comprises the TSPC trigger provided by any embodiment, and/or the second trigger comprises the TSPC trigger provided by any embodiment.
In some embodiments of the present invention, as shown in fig. 8, the second flip-flop 2 includes a first transistor M1, a second transistor M2, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6 and a seventh transistor M7, and the connection relationship between the first transistor M1, the second transistor M2, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6 and the seventh transistor M7 is the same as that of the embodiment shown in fig. 3, and will not be repeated here.
In any of the above embodiments, as shown in fig. 8, the dual-mode prescaler further includes a ninth transistor M9, a tenth transistor M10, and an eleventh transistor M11.
A first end of the ninth transistor M9 is connected to the second end of the second transistor M2 in the first flip-flop 1, the second end of the ninth transistor M9 is grounded, and a gate of the ninth transistor M9 is connected to the input end CLKOB of the first inverter INV 1; the output terminal CLKO of the first inverter INV1 is connected to the gate of the second transistor M2 in the second flip-flop 2.
The first terminal of the tenth transistor M10 is connected to the power supply VDD, the second terminal of the tenth transistor M10 is connected to the second terminal of the sixth transistor M6 in the second flip-flop 2, and the gate of the tenth transistor M10 is connected to the second signal terminal P.
The first terminal of the eleventh transistor M11 is connected to the second terminal of the second transistor M2 in the second flip-flop 2, the second terminal of the eleventh transistor M11 is grounded, and the gate of the eleventh transistor M11 is connected to the signal input terminal MoDin of the dual-mode frequency divider.
On the basis of the above-described embodiments, in some embodiments of the present invention, as shown in fig. 8, the first flip-flop 1 includes a first transistor M1, a second transistor M2, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, and a first inverter INV1; the connection relationship of the first transistor M1, the second transistor M2, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7 and the eighth transistor M8 is the same as that of the embodiment shown in fig. 4, and will not be described again here. Further, an input terminal of the first inverter INV1 is connected to a common terminal CLKOB of the sixth transistor M6 and the eighth transistor M8 in the first flip-flop 1. The gate of the second transistor M2 in the first flip-flop 1 is connected to the second terminal of the sixth transistor M6 in the second flip-flop 2, and the second terminal of the sixth transistor M6 in the second flip-flop 2 is connected to the gate of the sixth transistor M6 in the second flip-flop 2.
It should be noted that, since the first stage dual-mode prescaler does not need to output signals, i.e., the first stage dual-mode prescaler has no signal output terminal MoDout, in some embodiments of the present invention, as shown in FIG. 8, the dual-mode prescaler has no signal output terminal MoDout. However, since the other stage dual mode prescaler needs to output a signal to the previous stage dual mode prescaler, in some embodiments of the present invention, the dual mode prescaler has a signal output MoDout.
On the basis of the above embodiment, as shown in fig. 9, the dual-mode prescaler further includes a second inverter INV2, an input end of the second inverter INV2 is connected to the gate of the fifth transistor M5 in the second flip-flop 2, and an output end of the second inverter INV2 is the signal output end madout of the dual-mode divider.
Although the first stage dual-mode prescaler may also have the signal output terminal MoDout, since the dual-mode prescaler is connected to the signal output terminal MoDout through an inverter, and the inverter introduces additional parasitic capacitance, in some embodiments of the present invention, it is preferable that the first stage dual-mode prescaler does not have the signal output terminal MoDout, and the other stages dual-mode prescaler has the signal output terminal MoDout, i.e., the first stage dual-mode prescaler has the structure shown in FIG. 8, and the other stages dual-mode prescaler has the structure shown in FIG. 9.
In the structure shown in fig. 8 and 9, by reducing the number of stacks of transistors on critical paths, without reducing the number of stacks of transistors on non-critical paths, the operating speed is increased and the power consumption is reduced. However, in order to ensure stable operation of the structure shown in fig. 8 and 9 under all process conditions, the size of the ninth transistor M9, the second transistor M2, and the eleventh transistor M11 is larger than that of the first transistor M1, and the size of the tenth transistor M10 and the size of the sixth transistor M6 in the second flip-flop 2 are larger than that of the seventh transistor M7.
Alternatively, the size of the ninth transistor M9, the size of the second transistor M2, and the size of the eleventh transistor M11 are at least 4 times larger than the size of the first transistor M1; the size of the tenth transistor M10 is at least 4 times larger than the size of the seventh transistor M7, and the size of the sixth transistor M6 in the second flip-flop 2 is at least 4 times larger than the size of the seventh transistor M7.
In some embodiments of the present invention, as shown in fig. 8 and 9, the tenth transistor M10 is a PMOS transistor, the ninth transistor M9 and the eleventh transistor M11 are NMOS transistors, and of course, the present invention is not limited thereto, and in other embodiments, the tenth transistor M10 may be an NMOS transistor, and the ninth transistor M9 and the eleventh transistor M11 may be PMOS transistors.
Of course, in other embodiments of the present invention, in order to ensure stable operation of the dual-mode prescaler, the number of stacked transistors on the critical path may be relatively increased, as shown in fig. 10, the first flip-flop 1 and the second flip-flop 2 each include a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7 and an eighth transistor M8, and the connection relationships of the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7 and the eighth transistor M8 are the same as those of the embodiment shown in fig. 6, which is not repeated herein.
The first flip-flop 1 further includes a first inverter INV1, and an input terminal CLKOB of the first inverter INV1 is connected to a common terminal of the sixth transistor M6 and the eighth transistor M8 in the first flip-flop 1; an output terminal CLKO of the first inverter INV1 is connected to a gate of the second transistor M2 and a gate of the third transistor M3 in the second flip-flop 2;
the dual mode prescaler further includes a twelfth transistor M12, a thirteenth transistor M13, a fourteenth transistor M14, a fifteenth transistor M15, a sixteenth transistor M16, and a seventeenth transistor M17;
A first terminal of the twelfth transistor M12 is connected to the first terminal of the second transistor M2 in the first flip-flop 1, a second terminal of the twelfth transistor M12 is connected to the second terminal of the second transistor M2 in the first flip-flop 1, and a gate of the twelfth transistor M12 is connected to the input terminal CLKOB of the first inverter INV 1; a first terminal of the thirteenth transistor M13 is connected to the first terminal of the third transistor M3, a second terminal of the thirteenth transistor M13 is grounded, and a gate of the thirteenth transistor M13 is connected to the input terminal CLKOB of the first inverter INV 1;
the first end of the fourteenth transistor M14 is connected to the power supply VDD, the second end of the fourteenth transistor M14 is connected to the second end of the sixth transistor M6 in the second flip-flop 2, and the gate of the fourteenth transistor M14 is connected to the second signal end P; the second end of the sixth transistor M6 in the second flip-flop 2 is connected to the first end of the eighth transistor M8, the first end of the fifteenth transistor M15 is connected to the second end of the sixth transistor M6 in the second flip-flop 2, the second end of the fifteenth transistor M15 is connected to the first end of the eighth transistor M8 in the second flip-flop 2, and the gate of the fifteenth transistor M15 is connected to the second signal end P;
a first end of the sixteenth transistor M16 is connected to the first end of the second transistor M2 in the second flip-flop 2, a second end of the sixteenth transistor M16 is connected to the second end of the second transistor M2 in the second flip-flop 2, and a gate of the sixteenth transistor M16 is connected to the signal input terminal MoDin of the dual-mode prescaler; a first terminal of the seventeenth transistor M17 is connected to the second terminal of the seventh transistor M7 in the second flip-flop 2, a second terminal of the seventeenth transistor M17 is grounded, and the seventeenth transistor M17 is connected to the signal input terminal MoDin of the dual-mode prescaler;
The gates of the second transistor M2 and the third transistor M3 in the first flip-flop 1 are connected to the second terminal of the sixth transistor M6 in the second flip-flop 2.
Also, since the first stage dual-mode prescaler does not need to output a signal, i.e., the first stage dual-mode prescaler does not have a signal output MoDout, in some embodiments of the present invention, the dual-mode prescaler does not have a signal output MoDout, as shown in FIG. 10. However, since the other stage dual mode prescaler needs to output a signal to the previous stage dual mode prescaler, in some embodiments of the present invention, the dual mode prescaler has a signal output MoDout.
On the basis of the above embodiment, as shown in fig. 11, the circuit further includes a third inverter INV3, an input end of the third inverter INV3 is connected to the gate of the fifth transistor M5 in the second flip-flop 2, and an output end of the third inverter INV3 is a signal output end madout of the dual-mode frequency divider.
Also, in some embodiments of the present invention, it is preferable that the first stage dual-mode prescaler does not have the signal output terminal MoDout, and the other stages dual-mode prescaler has the signal output terminal MoDout, that is, the first stage dual-mode prescaler has the structure shown in FIG. 10, and the other stages dual-mode prescaler has the structure shown in FIG. 11.
The operation of the dual mode will be described by taking the structure shown in fig. 8 as an example.
As shown in fig. 12, when MoDin is high and P is high, it is first assumed that CLK0 is high, and when CLKIN is low, the first transistor M1, the second transistor M2, and the eleventh transistor M11 in the second flip-flop 2 are all turned on, and since the size of the second transistor M2 and the eleventh transistor M11 is larger than that of the first transistor M1, the A2 node is pulled down to low, the fifth transistor M5 in the second flip-flop 2 is turned off, and since the fourth transistor M4 in the second flip-flop 2 is turned on, the B2 node is pulled up to high, so that the second transistor M2 in the first flip-flop 1 is turned on, but since CLKOB is low, the ninth transistor M9 in the first flip-flop 1 is turned off. Since the first transistor M1 in the first flip-flop 1 is turned on, the A1 node is pulled high so that the fifth transistor M5 in the first flip-flop 1 is turned on. Since the fourth transistor M4 and the fifth transistor M5 in the first flip-flop 1 are both turned on and the size of the fourth transistor M4 is larger than the size of the fifth transistor M5, the B1 node is pulled high so that the sixth transistor M6 is turned off, and since the seventh transistor M7 is turned off, CLKOB is kept at a low level and CLK0 is kept at a high level. In this process, moDout outputs a low level.
When CLKIN becomes high level, the first transistor M1 in the second flip-flop 2 is turned off, the second transistor M2 and the eleventh transistor M11 are turned on, and the A2 node is continuously pulled down to low level, and since the fourth transistor M4 and the fifth transistor M5 in the second flip-flop 2 are both turned off, the B2 node remains at high level. Since the first transistor M1 and the ninth transistor M9 in the first flip-flop 1 are turned off, the A1 node is maintained at a high level, and the fifth transistor M5 in the first flip-flop 1 is continuously turned on. Since the fourth transistor M4 in the first flip-flop 1 is turned off, the node B1 is pulled down to a low level, so that the sixth transistor M6 in the first flip-flop 1 is turned on, CLKOB is pulled high, CLK0 is low, the second transistor M2 in the second flip-flop 2 is turned off, so that the node A2 remains at a low level, i.e., the prodout continuously outputs a low level.
When CLKIN goes low again, since the second transistor M2 in the second flip-flop 2 is turned off and the first transistor M1 is turned on, the A2 node is pulled high so that the fifth transistor M5 in the second flip-flop 2 is turned on. Since the fourth transistor M4 and the fifth transistor M5 in the second flip-flop 2 are both turned on and the size of the fourth transistor M4 is larger than the size of the fifth transistor M5, the node B2 is continuously at the high level. Since CLKOB is also high level, the first transistor M1, the second transistor M2, and the ninth transistor M9 in the first flip-flop 1 are turned on, pulling the A1 node to low level, so that the fifth transistor M5 in the first flip-flop 1 is turned off. Since the fourth transistor M4 in the first flip-flop 1 is turned on, the node B1 is pulled high, so that the sixth transistor M6 in the first flip-flop 1 is turned off, and since the seventh transistor M7 in the first flip-flop 1 is turned off, CLKOB is maintained at a high level, and CLK0 is maintained at a low level. In this process, moDout outputs a high level.
When CLKIN again goes high, the first transistor M1 and the second transistor M2 in the second flip-flop 2 are turned off, the A2 node remains high, the fifth transistor M5 in the second flip-flop 2 is continuously turned on, and since the fourth transistor M4 in the second flip-flop 2 is turned off and the seventh transistor M7 is turned on, the B2 node is pulled down to low, so that the second transistor M2 in the first flip-flop 1 is turned off. Since the first transistor M1 in the first flip-flop 1 is turned off, the A1 node is maintained at a low level, since the fourth transistor M4 and the fifth transistor M5 in the first flip-flop 1 are both turned off, and since the seventh transistor M7 and the eighth transistor M8 in the first flip-flop 1 are both turned on, CLKOB is pulled to a low level so that CLKO is at a high level, and the second transistor M2 in the second flip-flop 2 is turned on. Since both the second transistor M2 and the eleventh transistor M11 in the second flip-flop 2 are turned on, the A2 node is pulled to a low level. In this process, moDout outputs a low level.
When CLKIN goes low again, the same procedure as described above is omitted here.
That is, when MoDin is high and P is high, the frequency of MoDout is one third of the CLKIN frequency.
When mosin is low and P is high, as shown in fig. 13, CLK0 is first assumed to be high, and when CLKIN is low, the first transistor M1 in the second flip-flop 2 is turned on, and the node A2 is pulled high, and the fourth transistor M4 and the fifth transistor M5 in the second flip-flop 2 are both turned on, so that the node B2 is high. Since CLKOB is low level, the ninth transistor M9 in the first flip-flop 1 is turned off, and the first transistor M1 in the first flip-flop 1 is turned on, and therefore, the A1 node is high level, since the fourth transistor M4 and the fifth transistor M5 in the first flip-flop 1 are both turned on, the B1 node is high level, CLKOB is kept low level, and CLK0 is kept high level. In this process, moDout outputs a high level.
When CLKIN goes high, the A2 node remains high, and the B2 node is pulled low because the fourth transistor M4 is turned off, the fifth transistor M5 is turned on, and the seventh transistor M7 is turned on in the second flip-flop 2. Since both the first transistor M1 and the second transistor M2 in the first flip-flop 1 are turned off, the A1 node is maintained at a high level, and since the fourth transistor M4 and the fifth transistor M5 in the first flip-flop 1 are turned off and turned on, the B1 node is pulled to a low level, the sixth transistor M6 and the eighth transistor M8 in the first flip-flop 1 are turned on and turned off, respectively, such that CLKOB is at a high level and CLK0 is at a low level, such that the A2 node is maintained at a high level. In this process, moDout outputs a high level.
When CLKIN goes low again, the A2 node is kept high, and since the fourth transistor M4 and the fifth transistor M5 in the second flip-flop 2 are both turned on, the B2 node is kept high, so that the second transistor M2 in the first flip-flop 1 is turned on. Since CLKOB is high level, the ninth transistor M9 in the first flip-flop 1 is turned on, and the first transistor M1 in the first flip-flop 1 is also turned on, and thus, the A1 node is pulled low level, the B1 node is pulled high level by the fourth transistor M4 in the first flip-flop 1, which is turned on, CLKOB is kept high level, and CLK0 is kept low level. In this process, moDout outputs a high level.
When CLKIN goes high again, the A2 node continues to go high, B2 is pulled low, the A1 node remains low, the B1 node remains high, CLKOB is pulled low, and CLK0 goes high. In this process, moDout outputs a high level.
When CLKIN goes low again, the previous process is repeated and will not be described again.
That is, when mosin is low and P is high, mosout continues to output high.
Similarly, when mosin is low and P is low, mosout continues to output high as shown in fig. 13. When MoDin is high and P is low, the frequency of MoDout is one half of the CLKIN frequency as shown in fig. 14.
Under the same input conditions, the output structure of the structure shown in fig. 9 to 11 is the same as the output result of the structure shown in fig. 8, and will not be described in detail here.
In some embodiments of the present invention, the logic control circuit in the dual-mode prescaler is integrated with the flip-flop to reduce the number of transistors, reduce the cost, AND increase the operation speed, as shown in fig. 8 AND 9, the second transistor M2 AND the ninth transistor M9 form an AND gate together with the fourth transistor M4 AND the fifth transistor M5, that is, the second transistor M2, the fourth transistor M4, the fourth transistor M5 AND the ninth transistor M9 in the first flip-flop 1 form an AND gate, the first transistor M1, the second transistor M2, the fourth transistor M4, the fourth transistor M5 AND the ninth transistor M9 in the first flip-flop 1 form a Latch1, that is, the first transistor M1, the second transistor M2, the fourth transistor M4, the fourth transistor M5 AND the ninth transistor M9 in the first flip-flop 1 implement the function of AND gate 1 AND flip-flop M4 in fig. 1, the first transistor M1, the fourth transistor M4 AND the seventh transistor M9 in the fourth flip-flop 1 AND the fourth transistor M4 in the fifth transistor M2 AND the fifth transistor M9 in the fifth flip-flop 1 implement the function of AND gate 1, AND the seventh transistor M1 in the fifth transistor M2 AND the fifth transistor M4 in the fifth flip-flop 1 AND the fifth transistor M2 in the fig. 1 AND the fifth transistor M2, AND the fifth transistor M9 in the fifth flip-flop 1 AND the fifth transistor M2 in the fifth flip-flop 1.
Of course, in other embodiments of the present invention, as shown in fig. 10 AND 11, the second transistor M2, the third transistor M3, the twelfth transistor M12 AND the thirteenth transistor M13 in the first flip-flop 1 form a nand gate, which in turn forms an AND gate with the fourth transistor M4 AND the fifth transistor M5, that is, the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the twelfth transistor M12 AND the thirteenth transistor M13 in the first flip-flop 1 implement the functions of the AND gate AND1 AND the Latch1 in fig. 1, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8 AND the first inverter INV1 in the first flip-flop 1 implement the functions of the Latch2 in fig. 1, AND the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the twelfth transistor M12 AND the Latch3 in the Latch2 in the first flip-flop 1 implement the functions of the AND Latch2 in fig. 6, the seventeenth transistor M7, the seventh transistor M8 AND the Latch2 in the Latch3 in the first flip-flop 1 implement the functions of the AND the Latch3 AND the seventeenth transistor M1 in fig. 1.
The embodiment of the invention also provides a frequency divider, which comprises a plurality of cascaded dual-mode prescalers, wherein the dual-mode prescalers comprise the dual-mode prescalers provided by any embodiment.
As shown in fig. 15, the dual mode prescaler 1 to the dual mode prescaler n are included, and the CLK0 terminal of the former stage dual mode prescaler is connected to the CLKIN terminal of the next stage dual mode prescaler, for example, the CLK01 terminal of the dual mode prescaler 1 is connected to the CLKIN terminal of the dual mode prescaler 2, and the MODOUT terminal of the latter stage dual mode prescaler is connected to the MODIN terminal of the former stage dual mode prescaler, for example, the MODOUT1 terminal of the dual mode prescaler 2 is connected to the MODIN terminal of the dual mode prescaler 1.
When the frequency divider works, the first-stage dual-mode prescaler 1 can realize a frequency division mode or a three-frequency division mode under the control of signals received by the P end and the MoDin end, and based on the frequency division mode or the three-frequency division mode, the initial signals can be subjected to frequency division by setting the signals of the P end and the MoDin end at different frequency division ratios.
The embodiment of the invention also provides an integrated circuit comprising the frequency divider provided by any embodiment. In some embodiments of the present invention, the integrated circuit may form a radar chip, or the like, alternatively, the integrated circuit is a millimeter wave radar chip, and of course, the present invention is not limited thereto, and in other embodiments, the integrated circuit may be a radar chip of other wavebands. In addition, the integrated circuit in the embodiment of the present invention may also form other communication chips, sensors or detection devices, and the like, which are not described herein.
The embodiment of the invention also provides a radio device which comprises a carrier, an integrated circuit and an antenna, wherein the integrated circuit is provided by the embodiment, and is arranged on the carrier. The antenna is disposed on the carrier or integrated in the package of the integrated circuit, and the integrated circuit is connected to the antenna for transceiving the antenna electrical signals.
The embodiment of the invention also provides equipment, which comprises an equipment body and the radio device arranged on the equipment body, wherein the radio device is used for target detection and/or communication.
The carrier can be a transportation means (such as various types of automobiles, ships, inter-city rail transit and the like), intelligent equipment (such as mobile phones, air conditioners and the like), security equipment (such as subway security check, airport security check and the like), traffic auxiliary equipment (such as a barrier gate), industrial automation equipment and the like.
In the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant points refer to the description of the method section.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (18)

1. A TSPC trigger comprising a first stage structure;
the first stage structure comprises a first transistor and a second transistor, and the size of the second transistor is larger than that of the first transistor;
the first end of the first transistor is connected with a power supply, the grid electrode of the first transistor is connected with a clock signal end, the second end of the first transistor is connected with the first end of the second transistor, the second end of the second transistor is grounded, and the grid electrode of the second transistor is connected with a first signal end;
the first stage structure further comprises a third transistor, and the second end of the first transistor is connected with the first end of the second transistor through the third transistor;
The grid electrode of the third transistor is connected with the first signal end;
the device further comprises a second-stage structure connected with the first-stage structure;
the second-stage structure comprises a fourth transistor and a fifth transistor, wherein the size of the fourth transistor is larger than that of the fifth transistor;
the first end of the fourth transistor is connected with a power supply, the grid electrode of the fourth transistor is connected with the clock signal end, the second end of the fourth transistor is connected with the first end of the fifth transistor, the second end of the fifth transistor is grounded, and the grid electrode of the fifth transistor is connected with the common end of the second transistor and the third transistor.
2. The TSPC flip-flop of claim 1, wherein the size of said second transistor is at least 4 times larger than the size of said first transistor.
3. The TSPC trigger of claim 1, further comprising a third level structure coupled to the second level structure;
the third stage structure includes a sixth transistor and a seventh transistor, the sixth transistor having a size that is larger than the size of the seventh transistor;
the first end of the sixth transistor is connected with a power supply, the second end of the sixth transistor is connected with the first end of the seventh transistor, the grid electrode of the sixth transistor is connected with the common end of the fourth transistor and the fifth transistor, the second end of the seventh transistor is grounded, and the grid electrode of the seventh transistor is connected with the clock signal end.
4. The TSPC flip-flop of claim 3, wherein a size of said fourth transistor is at least 4 times larger than a size of said fifth transistor; and/or the number of the groups of groups,
the size of the sixth transistor is at least 4 times larger than the size of the seventh transistor.
5. The TSPC flip-flop of claim 3, wherein said third stage structure further comprises an eighth transistor, said second terminal of said sixth transistor being coupled to said first terminal of said seventh transistor through said eighth transistor; and
the first end of the eighth transistor is connected with the second end of the sixth transistor, the second end of the eighth transistor is connected with the first end of the seventh transistor, and the grid electrode of the eighth transistor is connected with the common end of the fourth transistor and the fifth transistor.
6. A dual mode prescaler comprising a first flip-flop comprising the TSPC flip-flop of any of claims 1-2, and/or a second flip-flop,
the second trigger comprising the TSPC trigger of any of claims 1-2.
7. The dual modulus prescaler of claim 6, wherein the second flip-flop comprises the first transistor, the second transistor, the fourth transistor, the fifth transistor, a sixth transistor, and a seventh transistor;
The dual mode prescaler further comprises a tenth transistor and an eleventh transistor;
the first end of the tenth transistor is connected with a power supply, the second end of the tenth transistor is connected with the second end of the sixth transistor in the second trigger, and the grid electrode of the tenth transistor is connected with a second signal end; and
the first end of the eleventh transistor is connected with the second end of the second transistor in the second trigger, the second end of the eleventh transistor is grounded, and the grid electrode of the eleventh transistor is connected with the signal input end of the dual-mode prescaler.
8. The dual modulus prescaler of claim 7, wherein the first flip-flop comprises the first transistor, the second transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and an eighth transistor;
the dual-mode prescaler further comprises a first inverter and a ninth transistor;
an input end of the first inverter is connected with a common end of the sixth transistor and the eighth transistor; the output end of the first inverter is connected with the grid electrode of the second transistor in the second trigger;
A first end of the ninth transistor is connected with a second end of a second transistor in the first trigger, a second end of the ninth transistor is grounded, and a grid electrode of the ninth transistor is connected with an input end of the first inverter; and
the grid electrode of the second transistor in the first trigger is connected with the second end of the sixth transistor in the second trigger, and the second end of the sixth transistor in the second trigger is connected with the grid electrode of the sixth transistor in the second trigger;
wherein the size of the ninth transistor, the second transistor, and the eleventh transistor is larger than the size of the first transistor, and the size of the tenth transistor and the size of the sixth transistor in the second flip-flop are larger than the size of the seventh transistor.
9. The dual mode prescaler of claim 8, further comprising a second inverter, an input of the second inverter being coupled to a gate of a fifth transistor in the second flip-flop, an output of the second inverter being a signal output of the dual mode prescaler.
10. The dual mode prescaler of claim 8, wherein the size of the ninth transistor, the size of the second transistor, and the size of the eleventh transistor are at least 4 times the size of the first transistor;
The size of the tenth transistor is at least 4 times that of the seventh transistor, and the size of the sixth transistor in the second flip-flop is at least 4 times that of the seventh transistor.
11. The dual modulus prescaler of claim 6, wherein the first flip-flop comprises the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor;
the dual mode prescaler further comprises a first inverter, a twelfth transistor, and a thirteenth transistor;
the input end of the first inverter is connected with the common end of the sixth transistor and the eighth transistor in the first trigger; the output end of the first inverter is connected with the grid electrode of the second transistor and the grid electrode of the third transistor in the second trigger; and
a first end of the twelfth transistor is connected with the first end of the second transistor, a second end of the twelfth transistor is connected with the second end of the second transistor, and a grid electrode of the twelfth transistor is connected with the input end of the first inverter; a first terminal of the thirteenth transistor is connected to the first terminal of the third transistor, a second terminal of the thirteenth transistor is grounded, and a gate of the thirteenth transistor is connected to the input terminal of the first inverter.
12. The dual modulus prescaler of claim 11,
the second flip-flop includes the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor;
the dual mode prescaler further comprises a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, and a seventeenth transistor;
the first end of the fourteenth transistor is connected with a power supply, the second end of the fourteenth transistor is connected with the second end of the sixth transistor in the second trigger, and the grid electrode of the fourteenth transistor is connected with a second signal end; the second end of the sixth transistor in the second trigger is connected with the first end of the eighth transistor, the first end of the fifteenth transistor is connected with the second end of the sixth transistor in the second trigger, the second end of the fifteenth transistor is connected with the first end of the eighth transistor in the second trigger, and the grid electrode of the fifteenth transistor is connected with the second signal end; and
the first end of the sixteenth transistor is connected with the first end of the second transistor in the second trigger, the second end of the sixteenth transistor is connected with the second end of the second transistor, and the grid electrode of the sixteenth transistor is connected with the signal input end of the dual-mode prescaler; a first end of the seventeenth transistor is connected with a second end of a seventh transistor in the second trigger, a second end of the seventeenth transistor is grounded, and the seventeenth transistor is connected with a signal input end of the dual-mode prescaler;
And the gates of the second transistor and the third transistor in the first trigger are connected with the second end of the sixth transistor in the second trigger.
13. The dual mode prescaler of claim 12, further comprising a third inverter, an input of the third inverter being coupled to a gate of a fifth transistor in the second flip-flop, an output of the third inverter being a signal output of the dual mode prescaler.
14. A frequency divider comprising a plurality of cascaded dual mode prescalers, the dual mode prescalers comprising the dual mode prescaler of any of claims 6-13.
15. An integrated circuit, comprising:
the frequency divider of claim 14.
16. The integrated circuit of claim 15, wherein the integrated circuit is a millimeter wave radar chip.
17. A radio device, comprising:
a carrier;
an integrated circuit as claimed in claim 15 or 16, disposed on the carrier; and
an antenna disposed on the carrier or integrated in the package of the integrated circuit;
the integrated circuit is connected with the antenna and is used for receiving and transmitting radio signals.
18. A radio device, comprising:
an equipment body; and
the radio of claim 17 disposed on the device body;
wherein the radio device is used for target detection and/or communication.
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CN102497201A (en) * 2011-12-21 2012-06-13 东南大学 True Single-Phase Clock (TSPC) 2/3 dual-mode prescaler with high speed and low power consumption

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SE507550C2 (en) * 1995-10-17 1998-06-22 Forskarpatent I Linkoeping Ab Device at gates and flip-flops in the category of genuine single-phase clocked circuits
CN102739239B (en) * 2012-06-15 2014-11-05 江苏物联网研究发展中心 High-speed low power consumption true single-phase clock 2D type two-thirds dual-mode frequency divider
CN105071805B (en) * 2015-08-21 2018-06-01 东南大学 A kind of 2/3 dual-modulus prescaler of high-speed low-power-consumption
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