SE507550C2 - Device at gates and flip-flops in the category of genuine single-phase clocked circuits - Google Patents

Abstract

Speed, robustness and static performance of TSPC (True Single Phase Clocking) latches and flipflops are analysed in this paper. New latches and flipflops are proposed to upgrade the overall speed, power saving, clock slope insensitivity and static performance of TSPC. Both new single-rail and new dual-rail latches and flipflops are proposed. Among them are different dynamic, semi-static and fully-static versions. The delays are reduced by factors of 1.3, 2.1, 2.2 and 2.4 for the single-rail dynamic, the dual-rail dynamic, the semi-static and the fully-static versions respectively. In the same time, power consumptions are also reduced so the power-delay products are reduced by factors of 1.9, 3.5, 3.4 and 6.5 respectively for an average activity rate (0.25). These improvements are accompanied with less transistor counts and less clock loads. One unique type of the proposed latches uses only a single clocked transistor and only n-transistors in logic (in both n- and p-latches and in both dynamic and static versions).

Description

507 550 2 to occur, static rather than dynamic behaviors are desirable. Static TSPC circuits are also suitable for low power applications. Thus, an improvement in the performance of static TSPC circuits are very useful for several applications. 4. Since TSPC circuits normally find their application among power-intensive high-speed speed electronics, it is important that the power consumption of the circuits does not skyrocket when the speed increases. The performance measure power-delay product (Swedish power-delay product) provides a more complete picture of a circuit's performance and this measure should replace a pure delay measure given today's requirements for low power consumption. A lower power-delay product at TSPC circuits are a requirement in tomorrow's electronics.

THE INVENTION The invention consists of TSPC circuits with three substantially different modes of operation, partly dynamic. partly semi-static and partly fully static circuits. All circuits are basically dual-rail type. i.e. the circuits communicate via two complementary signals instead of just one signal. single-fail, which is the norm. However, fl era of the circuits with a small addition in hardware also adapted to single-rail behavior.

The first category of dual-rail TSPC circuits are dynamic circuits with fl your clock transistors and is named after its transistor topology cross-connected latches. Unlike the con- conventional CVSL latches [N. Weste and K. Eshraghian, "Principles of CMOS VLSl design ", Chapter 5, Addison-Wesley, 1993], the cross-linked TSPC latches are independent of transistor width ratios, which provide reliable circuits. Furthermore, it is cross-linked The p-type TSPC latch faster than the corresponding CVSL latch while cross-coupled The n-type TSPC latch is slower than the corresponding CVSL latch. To create the fastest possible rocker, it is thus appropriate to use the cross-linked TSPC latch off p-type as well as a CVSL latch of n-type.

Further improvements of a rocker containing the above circuits are possible.

By replacing the p-type TSPC latch with two SP-type TSPC steps, where the term SP is explained in EXAMPLE: Fig. 1, an even faster rocker is obtained. No one is needed 507 550 3 logical function in the two TSPC stages of SP type, a further improvement can then be implemented The SP steps can shrink in complexity, resulting in an increase in performance.

Compared to TSPC in its original form, the cross-linked latches are higher speed, lower power consumption and greater durability against long clock anchors.

The second category of dual-rail TSPC circuits are dynamic circuits with only one clock transistor per latch and is consequently called intransistor clocked latches. Two different versions of the entransistor clocked latches are included in the invention, STC-1 and STC-2, respectively, and that turns out that these complement each other well when cascade coupling of STC-1 of n-type with STC-2 of p-type provides an STCL-type rocker with very good speed and power performance. A unique property is obtained in this rocker as all logic, both in the n- and p-type latch, can be implemented only by means of n-transistors.

Like the cross-connected latches, the single-transistor clocked latches are higher speed, lower power consumption and greater durability against long clock anchors than TSPC in its original form has.

The third category of dual-rail T SPC circuits are semi-static circuits, and by this is meant that a flip-flop can keep its internal data at 0 Hz when the clock signal is either high or low (this depends on the structure of the circuit). The dynamic rockers based on an STC-1 latch n-type and two TSPC SP steps can be modified to have a semi-static behavior by replace the dynamic STC-1 latch with a static STC-1 latch. The clock signal to these flip-flops can be kept at their logically low state without the flip-flops losing their data. If instead wants to keep the clock signal at a logically high level so that the flip-flops do not lose theirs data, two separate TSPC SN steps and a static, cross-linked p-latch can be used. Finally, to keep the load on the clock signal to a minimum, semi-static STCL flip-flops can created by combining dynamic and static versions of p-type STC-Z latches and STC-1 latches of n-type. The semi-static latches have higher speed, lower power consumption and greater resistance to long clock fl anchors than semi-static TSPC circuits in their original form has.

The fourth category of dual-rail TSPC circuits are fully static circuits, and by this is meant that a flip-flop retains its internal data at 0 Hz whether the clock signal is high or low. Completely 507 550 4 static rocker can be constructed by cascading static STC-1 latches of n- and p-type, but even better from a speed point of view is to replace the p-type STC-1 latch with a cross-linked latch of p-type. Designing a fully static STCL rocker is also possible thanks although the p-type STC-2 latch can be made static. Here, too, a comparison with traditional TSPC that the new static latches and the all-static rockers are superior when it is about speed and power consumption.

EXAMPLE Fig. 1: The four basic steps of TSPC, namely the precharged p- and n-stage and the non-precharged stage The p and n steps, denoted by PP, PN, SP and SN, respectively, are shown in Fig. 1. A positive fl Anchor-triggered (Swedish flank-sensitive) rocker can be created partly in pre-charged and partly in non-pre-charged execution using the block combination PP-SP-PN-SN and SP-SP-SN-SN respectively. The the first two blocks, PP-SP and SP-SP, respectively, are called p-blocks (the configuration in Fig. 1 represents a p-latch), while the last two blocks, PN-SN and SN-SN, respectively, are called n-block (the configuration in Fig. 1 represents an n-latch). A negative fl anchor-triggered rocker obtained by replacing n- with p-block and vice versa. Logical operations can be introduced in the lashes provided that they follow the following rules; in steps PP or PN are placed the logic in transistor networks of either p- or n-type between the clock transistors, while the logic, in steps SP or SN, are placed in complementary transistor networks, one above and one below the clock transistor. A so-called pipeline can now be created by p- and n-blocks, with or without logical operations, alternate so that p-blocks follow n-blocks and n-blocks follow p-block. If a high data rate is sought through a pipeline, it is important to invest any logical operations in n-blocks and let the p-blocks remain only pure latches.

Fig. 2: D and D-INVERS created (a) in precharged p-block and (b) in static p-block.

If complementary input signals to an n-block are required, these signals must be created by one p-block. Fig. 2 shows complementary outputs from (a) a precharged β-block and (b) a non-preloaded parking block. The p-blocks in Fig. 2 thus have a delay corresponding to three steps which creates an fl ash neck in terms of speed in a pipeline. 507 556 5 Fig. 3: D and D-lNVERS created in SP steps.

A better alternative in terms of speed to Fig. 2 is to connect uncharged p-blocks, only consisting of a step of the type SP, after a precharged n-block. To the benefits of this circuit hear that the p-block has only a one-step delay when only one non-inverted output is needed, that the capacitive load on the clock signal is reduced and that its power consumption is reduced because both the number of steps and the number of precharged nodes are reduced. In addition, since the p-block consists of only one stage and is loaded only by (small) n-transistors can the p-block be small, which means that the n-block that drives the step SP is loaded minimally.

Unfortunately, this construction only works when the subsequent n-block is off pre-charged type and has a PN step whose evaluation time is less than the sum of the evaluation time for the n-block and the pull-down time (Sv. neddragningstiden) for the SP step, both in the current the construction. A second disadvantage is that both an extra inverter and an extra are required SP steps if the design is to be able to provide complementary signals; this is reported in Figs. 3.

Fig. 4: Latches.

An SN step is a 'high output latchï An SP step is a 'low output latch' The output of an SN stage and SP stage can only be locked when this is logically high resp. low, see Fig. 4. If you consider the SN step when the output is logically high, this output can thus locked during a low clock phase.

Fig. 5: Conditions for “immediate locking”.

In the case of the SN step, it can be observed that if the clock phase is logically high, it will fall provided that node a (output) has the voltage Vdd (voltage supply), node b to is charged to (Vdd-Vnth), where V'nth is the threshold voltage of the clocked n-transistor which depending on the voltage between the emitter and the substrate, so that the clocked n-transistor is at the outer edge of its off position. Assuming it is logically low the input signal is stable, the output will be locked immediately when the clock starts its for fl area from high to low, see Fig. 5. If the input is not stable but changes from low to high, node b will be discharged from (Vdd-V'nth) to ground. During this discharge the reading of the output signal is maintained as long as the Vgs of the clocked n-transistor (Vngs) is 507 550 6 less than V ”nth. If Vgs is increased above this value, the output charge will leak through it clocked the transistor to ground. A small charge leak is not the same as a serious one error, but to be on the safe side, Vngs <V ° nth should apply to a robust construction must be obtained.

The SP step can be described in a similar way to the SN step. Opposite voltage conditions apply, however, and the requirement for robust function is lVpgsl <lV'pthI.

Fig. 6: Worst case for SN-SN and SP-SP latches. (a) During locking (b) During unlocking In non-preloaded TSPC latches (SP-SP or SN-SN), the actual locking step is either the first or the second; this depends on the input signal. When a latch locks, the worst thing can happen the first step may lock because it is closest to the entrance. Fig. 6 (a) shows the worst the locking cases for an SN-SN and an SP-SP latch. Similarly, one can say that they The worst case of unlatching is when the second step is unlocked first because this gives the fastest signal change at the output and thus creates the worst possible the scenario for the subsequent latch. Fig. 6 (b) shows the worst unlock cases for one SN-SN and an SP-SP latch.

Fig. 7: Possible locking errors in TSPC preloaded latches.

In non-preloaded latches, locking errors only occur when an input signal changes during reading and thus only errors occur between two latches. However, 1 preloaded latches can have a locking error occur internally even when one input signal is stable as shown in Fig. 7. The location of the other the step in the precharged latch is similar to the placement of the first step in the uncharged the latch in Fig. 6 (a), and thus a locking error may occur. The error in the preloaded latch occurs when a high output signal from an n-latch drops to IVpthl below Vdd or when a low output from a p-latch rises to Vnth above ground; leakage then occurs in the following precharged stage p and n transistors, respectively. Simulations on pre-charged p- and n-latches of minimal size in 0.8-mm CMOS with typical process parameters shows that clock edges longer than 3.6 and 6.1 ns, respectively, gives rise to locking errors. Increases the width of the transistors marked with a point in Fig. 7 by three times, the maximum bell edge length is reduced to 1.1 and 1.2 ns, respectively. 507 ssb 7 Figs. 8 and 9: Worst case of SP-SP-SN-SN and of (PP) -SP-SN-SN respectively worst case of SN-SN-SP-SP and of (PN) -SN-SP-SP.

All cases where errors occur between two latches have been reported in previous figures, except the case with two non-pre-charged latches and the case of a pre-charged and non-pre-charged latch, where the the first output is connected to the latter's input. The worst cases occur when the first step is in its worst case of unlocking and the second step is in its worst case of locking; see Fig. 8 and Fig. 9 which show a p-n and an n-p block combination where really only blocks within the dashed rectangle are of interest.

Fig. 10: CVSL latches.

The basic CVSL steps [N. Weste and K. Eshraghian, “Principles of CMOS VLSI design ", Chapter 5, Addison-Wesley, 1993], the n- and p-latches, respectively, are shown in Fig. 10.

.The problem with these latches is that they are dependent on the transconductance ratio, and thus transistor width ratio, between the p and n transistors. Unless a suitable quota is chosen at the design, if the circuit process differs from the expected or about the temperature deviates from expectations, the latches may stop working completely or at least exhibit unexpectedly large delays. If, for example, the n-transistors are 2 μm wide (which is the smallest possible width in a 0.8-pm CMOS process), an n-type CVSL latch can never function satisfactorily; at a transistor width greater than or equal to 3.4 μm at the p-transistors stop the latch from working completely. In the parking lot, the best thing to do is to minimize the width of the n transistors; if this width is 4 μm, the p-transistors must be made 20 μm wide, giving rise to an unnecessarily large latch. Great care must therefore be taken design of CVSL latches and especially great care applies when the latches are to contain logic.

Fig. 11: Cross-connected latches.

The TSPC latches completely independent of transistor width ratios are shown in Fig. 1 1. Where and one of these is obtained by cross-coupling two identical TSPC latches. The cross-linked The p-type TSPC latch is faster than the corresponding CVSL latch while cross-coupled The n-type TSPC latch is slower than the corresponding CVSL latch.

Fig. 12: Combination of n-type CVSL latch and p-type cross-linked TSPC latch. 507 550 8 Based on the comparison between performance of CVSL- and cross-connected TSPC latches, a fast rocker should consist of n-type CVSL latches while the p-type latches should consist of cross-linked TSPC latches, see Fig. 12.

Fig. 13: Quick rocker configurations; (a) Stand-alone type; (b) Merger type Better than the rocker shown in Fig. 12 is the one shown in Fig. 13 (a). When a rocker consists of CVSL latches of n- and p-type, only one of them needs to be a complete latch. To For example, the p-latch can be replaced by two separate TSPC SP steps as shown in Fig. 13 (a). Despite that a logically high input to the SP stage immediately translates to a logically low output then the clock is in its logically high phase (locking is missing), this does not affect the CVSL latch if this already turned on. This arrangement is safe for a chain of these rockers thanks to that the pull-up delay (Swedish pull-up delay) of the rocker is longer than the pull-down the delay of the immediately preceding n-type CVSL latch.

When the p-latch in the rocker shown in Fig. 13 (a) acts only data delay without any actual logical function, it can be further simplified according to Fig. 13 (b). This arrangement works as long as subsequent blocks are an n-type CVSL latch, a cross-linked one N-type TSPC latch or a n-type TSPC latch.

For safety reasons, the transistors in Fig. 13 marked * should be minimal size. If the tilt delay of the next n-type CVSL latch is too large and they are minimal If the n-transistors are too fast, the two SP stages in Fig. 13 (a) can be redone so that they the appearance of the circuit given on the right in Fig. 13 (a). Furthermore, if a pipeline ends with the two modified SP steps given in Fig. 13, in order to obtain lockable data, cascade one SP stage for single-rail or two SP stages for dual-rail after one or two outputs.

Fig. 14: Combinations of TSPC SN steps and p-type TSPC latches. (a) Dual-rail type (b) Single-rail type By using the same principle as described in Fig. 13, two separate ones can be arranged TSPC SN step together with a p-type TSPC latch according to Fig. 14 (a). Here the delay through the n-latch is reduced so much that your logical functions can be loaded this latch despite the fact that the complementary function gives rise to a complex circuit network. 507 556 9 Finally, a third arrangement is to cascade the two SN steps in Figs. 14 (a) to obtain a single-rail behavior, as shown in Fig. 14 (b).

Fig. 15: STC-1 latches The single transistor clocked latches of STC-1 type are developed from The CVSL transistor topology and is shown in Fig. 15. The two latches, partly of p- and partly of n-type, can unfortunately not be cascaded to create a pipeline then transparency through a rocker consisting of the two latches can occur. Because the p-type STC-1 latch is a lot slower than the n-type, it is mainly the n-type that is of interest.

Fig. 16: Quick rocker based on an STC-1 latch. (a) Stand-alone type (b) Merged type in a pipeline It turns out that the n-type CVSL latch in Fig. 13 can be replaced by the n-type STC-1 latch and then the flip-flops shown in Fig. 16 are obtained. These are thus characterized by a small load on the clock signal.

Fig. 17: Dynamic STCL flip-flops: (a) Positive fl anchor-triggered rocker of dual-rail type (b) Positive kt anchor-triggered rocker of single-rail type (c) Negative fl anchor triggered section in a pipeline The flip-flops shown in Fig. 16 can be further improved. Through a combination of one A p-type STC-2 latch and an n-type STC-1 latch are available with an STCL-type rocker that only two clocked transistors, see Fig. 17 (a). Because the STC-2 latch is not sensitive to which order the input signal reverses, one can add an inverter to create a single-rail flip-flop type, see Fig. 17 (b). Both of these rockers are positively flanked.

The p-type STC-2 latch is similar in appearance to the n-type STC-1 latch, however, they are to the function radically different. The function of the p-type STC-2 latch is similar to that of the two SP steps, i.e. it transmits data during the low clock phase and blocks a low initial position during the high clock phase and blocks a high starting position during the beginning of the high the clock phase. But it differs from the two SP steps in that it contains only one clocked transistor and has its logic implemented in n-transistors. 507 550 10 To end a chain of STCL flip-flops with a p-type STC-Z latch, a termination steps as used in Fig. 17 (c).

The performance of the STCL rocker is unmatched in terms of high speed and low power consumption.

Fig. 18: Semi-static flip-flops. (a) Contextual version (b) simplified version A semi-static TSPC flip-flop is shown in Fig. 18 (a) and (b). Because the logic can be put in the n-latch The p-latch should be the static latch. There is no conflict in the rocker in (a) between n- and p-type transistor branches, while the flip-flop in (b) is admittedly at greater risk of conflict, but exhibits good performance due to its minimized load on the clock signal.

The risk of conjugation in (b) is very small if the size of the p-transistor is within the dashed line the rectangle is as small as possible.

Fig. 19: Fully static rocker based on RAM-type latches.

Fig. 19 shows a fully static rocker built up of latches of so-called RAM type [N. Wesic and K. Eshraghian, "Principles of CMOS VLSI design", Chapter 5, Addison-Wesley, 1993].

The problem with this rocker is that the construction is sensitive to deviations in the transistor width ratios and that the p-latch is slow. The transistors marked * should be of minimal size.

Fig. 20: Fully static rocker based on static STC-1 latches.

A fully static rocker consisting of a cascade coupling of static STC-1 latches of n- the respective p-type is shown in Fig. 20. This flip-flop has a smaller load on the clock signal than flip-flop in Fig. 19 harp The transistors marked * should be of minimal size.

Fig. 21: Fully static rocker based on static STC-1 latch of n-type and static, cross-coupled p-type latch.

Admittedly, both the rocker in Fig. 19 and the rocker in Fig. 20 are fully static and provided with complementary outputs, but they suffer from the fact that the p-latch is much slower than the n-latch. 507 550 ll The p-type static STC-1 latch in the rocker of Fig. 20 can be replaced with a static, cross-connected latch of p-type, which makes the rocker faster. This rocker is shown in Fig. 21.

Fig. 22: Semi-static fast rocker. (a) Stand-alone type (b) Merger type The dynamic rocker of Fig. 16, which utilizes an n-type dynamic STC-1 latch and two separate TSPC SP steps, can be made semi-static by replacing the dynamic one The n-type STC-1 latch with a n-type static STC-1 latch. This semi-static rocker is displayed in two different variants in Fig. 22. The clock signal to these flip-flops can be kept at their logically low condition without the flip-flops losing their data.

Fig.23: Semi-static flip-flops that require a high clock phase for static behavior. (a) With unmodified p-latch (b) With modified p-latch If, unlike the flip-flop in Fig. 22, one wishes to keep the clock signal at a logical high level so that the semi-static flip-flops do not lose their data, two separate TSPC SN steps can and a static, cross-linked p-latch is used, see Fig.23. In (b) a modified p-latch is used compared to the p-latch given in (a). Thus, (b) has a smaller load on the clock signal than (a) have.

Fig. 24: Fully static STCL flip-flops. (a) Positive fl anchor-triggered rocker of dual-rail type (b) Positive kt anchor-triggered rocker of single-rail type (c) Negative flank-triggered section in a pipeline Fig. 24 shows the fully static variant of the STCL flip-flop first introduced in Figs. 17. This fully static rocker has advantages such as high speed, low power consumption and small fan-in (Sv. ingreningsfaktor). The differences from the dynamic rocker in Fig. 17 are that both The STC-1 type n-latch and the STC-Z-type p-latch change from dynamic to static behavior.

Fig. 25: Semi-static STCL flip-flops. 507 550 12 (a) With static behavior at low clock phase (b) With static behavior at high clock phase Compared with the fully static STCL flip-flop in Fig. 24, the semi-static STCL flip-flop differs in Fig. 25 in that it consists of a combination of dynamic and static in terms of latches, p-type STC-1 and n-type STC-2. Just as in Fig. 24, single-rail can behave is achieved by adding an additional inverter to the circuit.

Claims (22)

507 ssó = i2> PATENTKRAV CMOS-based non-precharged circuit characterized by a combination of the following two circuit blocks: a. - circuit block 1 (cb-1) so constructed that during its unlocked phase the logic path (s) are between its output (s) and its input (s) is transparent (a) for both logically high and low output states and that during its locked phase the logic path (s) between its output (s) and its input (s) is non-transparent only for one of two states on a special output called the isolated logic state of the output (either logically low or high), where the unlocked and locked positions are determined by the two states, state 1 and state 2, respectively, which have a clock connected to cb-1; and b. circuit block 2 (cb-2) so constructed that during its unread phase, the logic path (s) between its output (s) and its relevant input (s) is transparent for only one of two states of a special input called the non-transparent logic state of the input, which must be identical to the isolated logic state at the output of cb-1 if cb-1 is connected to the input of cb-2, and that during its locked phase the logic path (s) are between output (s) and its input (s) non-transparent (a) for both logically high and low input states, where the unlocked and locked positions are determined by the two states, state 1 and state 2, respectively, as the one to both cb-1 and cb -2 connected clock has. Circuit (pdd-cb-1) according to claim 1, characterized in that it consists of: a. Two n-transistors, (n-1 and n-2), where both emitters are connected to ground, where it is first ( nl) control and collector constitute the INPUT and INVERTED OUTPUT of the circuit (pdd-cb-1) and where the other (n-2) control and collector constitute the INVERTED INPUT and OUTPUT of the circuit and of b. two p-transistors, (p- 1 and p-2), where the collector of one (pl) is connected to both the collector of the first n-transistor (n-1) and the control of the second p-transistor (p-2) and where its collector is connected to both the the collector of the second n-transistor (n-2) and the control of the first p-transistor (pl); 507 550 c. A third p-transistor (p-3) whose emitter is connected to the power supply, whose collector is connected to the emitters of both p-transistors (p-1 and p-2), and whose control consists of the CLOCK INPUT of the circuit. A fully static differential circuit according to claim 2, characterized in that it consists of: a. A circuit (pdd-cb-1) according to claim 2 which consists of two n-transistors (nl and n-2) three p-transistors (pl, p-2 and p-3) and has corresponding connections according to claim 2, with INPUT, INVERTED INPUT, OUTPUT, INVERTED OUTPUT ONE CLOCK INPUT; b. two further n-transistors, (n-3 and n-4), whose emitters constitute OUTPUT and INVERTED OUTPUT, respectively, and whose two collectors are connected to the collector of the third (p-3) of the three p-transistors; c. an inverter whose input is connected to the collector of the third (p-3) of the three p-transistors and whose output is connected to the gates of the two further n-transistors (n-3 and n-4); A dynamic differential circuit (ndd-cb-2) of n-type based on circuit block 2 (cb-2) according to claim 1, characterized in that it consists of: a. Two p-transistors, (p1 and p- 2), where both emitters are connected to the power supply, where the first (pl) control is connected to the other (p-2) collector and where the other (p-2) control is connected to the first (pl) collector; b. two n-transistors (nl and n-2) where the collector of the first (nl) is connected to the collector of the first p-transistor (pl), where the collector of the second n-transistor (n-2) is connected to the second p-transistor (p-2) collector, where the control and collector of the first n-transistor (nl) constitute the INPUT of the circuit (naden-z) and INVERTED OUTPUT, respectively, and where the control and collector of the second n-transistor (n-2) constitute the (ndd-cb-2) INVERTED INPUT AND OUTPUT; and c. a third n-transistor (n-3) whose emitter is connected to ground, whose collector is connected to the emitters of the two n-transistors (nl and n-2) and whose control is the CLOCK INPUT for the circuit (nad-ebay 507 ssó .f 5 A fully static differential circuit (nsd-cb-2) of n-type based on circuit block 2 (cb-Z), according to claim 4, characterized in that it consists of: a. A circuit (ndd-cb-2) according to claim 4, which consists of two p-transistors (p1 and p-2), three n-transistors (n-1, n-2 and n-3) and has corresponding connections according to claim 4; b. two new n-transistors (n-4 and n-5) where both emitters are connected to ground, where both the collector of the first-mentioned transistor (n-4) and the control of the second (n-5) constitute the OUTPUT and where both the the collector of others (n-5) and the board of the former (n-4) constitute INVERTED OUTPUT. A non-charged, dynamic, differential, positive fl non-sensitive flip-flop according to claim 4, characterized in that it consists of: a. A circuit (pdd-cb-1) according to claim 2, wherein its INPUT, INVERTED INPUT and CLOCK INPUT constitute flip-flops. INPUT, INVERTED INPUT rcspcktivc CLOCK INPUT; and b. a circuit (ndd-cb-Z) according to claim 4, wherein its OUTPUT, INVERTED OUTPUT and CLOCK INPUT constitute flip-flop OUTPUT, INVERTED OUTPUT rcspcittivc CLOCK INPUT and wherein öcss INPUT and INVERTED the input c- 1) OUTPUT and INVERTED OUTPUTS; A non-charged, fully static, differential, positive fl aric sensitive flip-flop according to claim 5, characterized in that it consists of: a. A circuit (psd-cb-1) according to claim 3, wherein its INPUT, INVERTED INPUT and KLQCKING INPUT constitute flip-flops INPUT, INVERTED INPUT rcspcittivc KLQCKIN INPUT; b. a circuit (nsd-cb-2) according to claim 5, wherein its OUTPUT, INVERTED OUTPUT and CLOCK INPUT constitute flip-flop OUTPUT, INVERTED OUTPUT rcspcittivc KLQCKING INPUT and where öcss INPUT and INVERTED ps -b-input requirement 3 OUTPUT and INVERTED OUTPUT, respectively. 507 550 16, - A non-pre-charged, semi-static, positive-sensitive non-sensitive rocker stationary at a logically low clock according to claim 5, characterized in that it consists of: a. A circuit (pdd-cb-1) according to claim 2, wherein its INPUT, INVERTED INPUT een CLOCK INPUT indicates the flip-flop INPUT, INVERTED INPUT and CLOCK INPUT respectively; b. a circuit (nsd-cb-2) according to claim 5, wherein its OUTPUT, INVERTED OUTPUT een CLOCK INPUT outputs the flip-flop OUTPUT, INVERTED OUTPUT and CLOCK INPUT, respectively, where its INPUT one INVERTED INPUT is EXCEPTLESS EXPENDED A non-pre-charged, semi-static, positive-sensitive non-sensitive rocker stationary at a logically high clock according to claim 4, characterized in that it consists of: ä. issues the flip-flop, INVERTED LENGTH and CLOCK LINK, respectively; n. a circuit (ndd-en-z) according to krsv 4, where its OUTPUT, INVERTED OUTPUT een KLOCKlNoÅNG outputs the flip-flop OUTPUT, INVERTED OUTPUT and CLOCK INPUT, respectively, where its INPUT een INVERTED INPUT is connected to c-ld requirement 3 OUTPUT and INVERTED OUTPUTS, respectively; 10. A dynamic. differential, terminating circuit stage (ndd-ts) of n-type, characterized in that it consists of: a. two p-transistors (p1 and p-2) where both emitters are connected to the voltage supply, where the first (p1) gate is connected to the other's (p-2) collector and where the other's (p-2) control is connected to the first (p-1) collector; b. two n-transistors (nl and n-2) where both emitters are connected to ground, where the first (nl) collector is connected to the collector of the first p-transistor (pl), where the second n-transistor (n- 2) collector is connected to the collector of the second p-transistor (p-2), where the control and collector of the first n-transistor (nl) constitute the INPUT of the circuit (ndd-ts) and sleep ssd rt INVERTED OUTPUT and where the second n- the control and collector of the transistor (n-2) constitute the INVERTED INPUT and output of the circuit (ndd-ts); A non-charged, dynamic, differential, negative flank sensitive flip-flop according to claims 1 and 10, characterized in that it consists of: n. A circuit (naden-z) according to claim 4, wherein its INPUT, INVENTED RANGE and a CLOCK CLINK outputs the flip-flop. INPUT, INVENTED INPUT AND CLOCK INPUT; n. a circuit (pddenl) according to claim z, where its INPUT een INVERTED lNGÅNo was connected to ndd-eezts OUTPUT and lNVERTED OUTPUT respectively; c. a circuit (ndd-ts) according to claim 10, wherein its OUTPUT and INVERTED OUTPUT are the output of the flip-flop and INVERTED OUTPUT, respectively, where its INPUT is an INTERNAL INPUT is inlet to the circuit (pdd-outLV) and out respectively in claim 2; A non-preloaded, differential, negative fl non-sensitive segment of a series of circuits according to claim 6 or 7 or 8 or 9, characterized in that: a. It consists of a flip-flop according to claim 6 or 7 or 8 or 9, wherein the circuit block (cb-1) (pdd-eb-1 or psd-cb-1) and cb-2 (ndd-eb-2 or nsd-eb-Z) replace each other so that cb-2zs lNGÅNG een INVERTED lNoÅNo constitutes the INPUT of the segment and INVERTED INPUTS and that cb-1'S OUTPUT and INVERTED OUTPUT constitute the segment's OUTPUT and INVERTED OUTPUT; b. it is required that the next step in the segment must be a cb-2 according to claim 1; Circuit in which the sub-circuits are reversed in Relation to claim 2 or 3 or 4 or 5, that is, ndd-cb-1 or nsd-cb-1 or pdd-cb-2 or psd-cb-2 (opposites to pdd- cb-1, psd-cb-1, ndd-cb-2 and nsd-cb-2, respectively, characterized in that it: a. is based on the original device in claim 2 or 3 or 4 or 5; b. maintains INPUT, INVERTED INPUT, OUTPUT, INVERTED OUTPUT and CLOCK INPUT from the original device; 507 550 1% c. Consists of p-transistors where the original device consists of n-transistors, consists of n-transistors where the original device consists of p-transistors, has connections to the voltage supply where the original device is connected to ground and has connections to ground where the original device is connected to the power supply; A non-pre-charged, fully static, differential, positively fl-sensitive flip-flop according to claims 1, 5 and 13, characterized in that it consists of: a. ENTRANCE respect KLOCKINGÅNG; b. an nsden-z according to krnv s, where its OUTPUT, INVERTED OUTPUT the CLOCK INPUT constitutes the OUTPUT of the flip-flop, INVERTED OUTPUT and KLQCKING INPUT ssrnr where its INPUT INVERSE INPUT nnsiUR UTSUURS now psdeuzs and psdeuzs now psdeuzs; Circuit which, in relation to the flip-flop or circuit segment in claim 6 or 7 or 8 or 9 or 11 or 12 or 14, has reversed parts, characterized in that it: a. Is based on the original device in claim 6 or 7 or 8 or 9 or 11 or 12 or 14; b. maintains INPUT, INVERTED INPUT, OUTPUT, INVERTED OUTPUT one CLOCK INPUT from the original device; c. consists of pdd-cb-1 where the original device consists of ndd-cb-1, consists of ndd-cb-1 where the original device consists of pdd-cb-1, consists of psd-cb-1 where the original the device consists of nsd-cb-1, consists of nsd-cb-1 where the original device consists of psd-cb-1, consists of pdd-cb-2 where the original device consists of ndd-cb-Z, consists of ndd-cb-Z where the original device consists of pdd-cb-Z, consists of psd-cb-2 where the original device consists of nsd-cb-2 and consists of nsd-cb-2 where the original device consists of psd-cb-2; d. has a negative-sensitive behavior where the original device has a positive-sensitive behavior and has a positive-sensitive behavior where the original device has a negative-sensitive behavior; sov sso 19 A one-way device for a flip-flop or circuit segment according to claim 6 or 7 or 8 or 9 or 11 or 12 or 14 or 15, characterized in that: a. It is based on the flip-flop or circuit segment of claim 6 or 7 or 8 or 9 or 11 or 12 or 14 or 15; b. its INPUT, OUTPUT, INVERTED OUTPUT and CLOCK INPUT are connected to INPUT, OUTPUT, INVERSED OUTPUT and CLOCK INPUT on the flip-flop or clay block, respectively; c. based on a CMOS inverter, whose input is connected to INPUT on the flip-flop or circuit segment and whose output is connected to INVERTED INPUTS on the flip-flop or circuit segment; A device, including logic, for the flip-flop or circuit segment of claim 6 or 7 or 8 or 9 or 11 or 12 or 14 or 15 or 16, characterized in that: a. Nl and n-2 in cb-1 and / or cb-2 and / or ndd-ts according to claim 1, 2, 3, 4, 5 and 10 in the flip-flop or circuit segment are replaced by n-circuit network-1 and n-circuit network-Z, respectively; b. n-circuit network-1 is a circuit network of n-transistors, with a common collector and a common emitter which are connected in the same way as the n-1's collector and emitter, respectively, with the control connected to the input vector INPUT, which leads to a set of input vectors lNGÄNGV-A and blocking the complementary set lNGÄNGV-B; c. n-circuit network-2 is another circuit network of n-transistors, with a common collector and a common emitter which are connected in the same way as the n-2's collector and emitter, respectively, with the control connected to the input vector INVERTED INPUTS, which lead in a set of input vectors INVERTED INPUTV-A and which blocks the complementary set of INVENTED INPUTVV-B; d. there may be more than one cb-1 and / or cb-2 and / or ndd-ts in the flip-flop or circuit segment with the connection arrangement according to claim 6 or 7 or 8 or 9 or 11 or 12 or 14 or 15 or 16; 507 550 .ZO- e. There may be other uncharged CMOS steps between cb-1, cb-2 and ndd-ts, however, logical inversion is between the output (outputs) on cb-1 and the input (inputs) on cb -2 illicit; A stand-alone, dynamic, differential cb-1 p-type device, ss-pdd-cb-1, which replaces pdd-cb-1 and a stand-alone, dynamic, n-type differential cb-1 device, ss- ndd-cb-1, which replaces ndd-cb-1 in the flip-flop or circuit segment of claim 6 or 8 or 11 or 12 or 15 or 16, characterized in that: a. ss-pdd-cb-1 or ss-ndd-cb -l consists of two identical steps, steps 1 and 2 of p- or MYP; b. stage 1 or 2 of p-type in ss-pdd-cb-1 consists of two p-transistors, p-1 and p-2, and an n-transistor, n-1, where the emitter of p1 is connected to the voltage supply, where pl:'s collector is connected to p-2's emitter, where p-2's collector is the output and is connected to n-1's collector. where the emitter of n-1 is connected to earth, where the control of p-2 constitutes the clock input and where both the control of p-1 and n-1 constitute the input; c. step 1 or 2 of n-type in ss-ndd-cb-1 is created by in step 1 or 2 of p-type. replace p-transistors with n-transistors, replace n-transistors with p-transistors, replace voltage supply with earth and replace earth with voltage supply; d. in both cases, the input and output in step 1 constitute INPUT and INVERTED OUTPUT, respectively, that the input and output in step 2 constitute INVERTED; INPUT and OUTPUT, respectively, and that the clock input in both steps 1 and 2 constitutes the clock input CLOCK INPUT; A dynamic, differential, single-input cb-1 p-type device, si-pdd-clæl, which replaces pdd-cb-1 and a dynamic, differential, single-input cb-1 device of n-type. si-ndd-cb-1, which replaces ndd-cb-1 in the flip-flop or circuit segment of claim 6 or 8 or 15. characterized in that: a. si-pdd-cb-1 is based on p-type steps 1 and 2 according to claim 18 and si-ndd-cb-1 based on steps 1 and 2 of n-type according to claim 18; b. in both cases, the output of the first stage is connected to the input of the second; 507 ssó * 21 c. In both cases the input on the first stage constitutes INPUT, that the output on the first stage constitutes INVERTED OUTPUTS, that the output on the second stage constitutes OUTPUT and that the clock input on both stages 1 and 2 constitutes the CLOCK INPUT; A dynamic, differential and ratio-insensitive cb-2 pb-type, ri-pdd-cb-2 device which replaces pdd-cb-2 in the flip-flop or circuit segment of claim 15 or 16. or 18 or 19, characterized in that: a. it consists of two steps, steps 1 and 2; b. step 1 consists of two p-transistors, p1 and p-2, and two n-transistors, nl and n-2, where the emitter of p-1 is connected to the voltage supply, where the collector of p-1 is connected to p-2's emitter, where p-2's collector is input and is connected to n-1's collector, where nl:'s emitter is connected to n-2's collector, where n-2's emitter is connected to earth, where the control of p-2 constitutes a clock input, where the control of n-1 constitutes input 1 and where both the control of p-1 and n-2 constitute input 2: c. step 2 is identical with step 1 except that the transistors are denoted by p-3, p-4. n-3 and n-4 instead of p-1, p-2, n-1 and n-2, respectively; d. step 1's output is connected to input 1 on step 2 and constitutes OUTPUT, step 2: 5 output is connected to input 1 on step 1 and constitutes INVERTED OUTPUT, input 2 on step 1 constitutes INVERSED INPUT, input 2 on step 2 constitutes INPUT and both clock inputs constitute CLOCK INPUT; A fully static, differential and transistor-wide cb-2 independent p-type device, ri-psd-cb-2, which replaces psd-cb-2 in the flip-flop or circuit segment of claim 15 or 16 or 18 or 19, characterized by that it consists of: a. five p-transistors, p1, p-2, p-3, p-4 and p-5, where the emitters of p1, p-4 and p-5 are connected to the voltage supply, where p-1 's collector is connected to both p-2's and p-3's emitters, where p-1's board constitutes clock input, CLOCK INPUT, where p-2's collector constitutes OUTPUT, where p-: æs' sex actuator constitutes INVERTED OUTPUT, where p-4z's connector öön p-sß control is connected to OUTPUT and where p-5's collector and p-4's control are connected to INVERTED OUTPUT; b. five n-transistors, nl, n-2, n-3, n-4 and n-5, where the emitters of n-2 and n-3 are connected to ground, where the collector of n-2z is connected to both n- 4's emitter and n-1's collector, where 507 550 2131 n-3's collector is connected to both n-5's and n-1's emitters, where n-4's collector constitutes OUTPUT, where n-5's collector constitutes INVERTED OUTPUTS, where n-1's control constitutes ueek input, KLQCIQNGÅNG, where n-zzs een p ~ 2 = s Styren constitutes INVERTED INPUT and where n-3's and p-3's control constitutes INPUT; A merged (ss-pdd-cb-1) device, mss-pdd-cb-1, which replaces ss-pdd-cb-1 in the circuit segment of claims 12, 15 and 16, characterized in that it: a. Is based on the original ss-pdd-cb-1 of claim 18; b. maintains INPUT, INVERTED INPUT, OUTPUT, INVERTED OUTPUT een CLOCK INPUT; c. lacks p-transistors connected to the voltage supply in both stages; d. has connection between the emitters of the remaining p-transistors in step 1 to INVERTED INPUT and connection between the emitters of the remaining p-transistors in step 2 now INPUT.