SE9503616D0 - Device at gates and flip-flops - Google Patents

Device at gates and flip-flops

Info

Publication number
SE9503616D0
SE9503616D0 SE9503616A SE9503616A SE9503616D0 SE 9503616 D0 SE9503616 D0 SE 9503616D0 SE 9503616 A SE9503616 A SE 9503616A SE 9503616 A SE9503616 A SE 9503616A SE 9503616 D0 SE9503616 D0 SE 9503616D0
Authority
SE
Sweden
Prior art keywords
static
latches
rail
dynamic
flipflops
Prior art date
Application number
SE9503616A
Other languages
Swedish (sv)
Other versions
SE9503616L (en
SE507550C2 (en
Inventor
Jiren Yuan
Original Assignee
Forskarpatent I Linkoeping Ab
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Forskarpatent I Linkoeping Ab filed Critical Forskarpatent I Linkoeping Ab
Priority to SE9503616A priority Critical patent/SE507550C2/en
Publication of SE9503616D0 publication Critical patent/SE9503616D0/en
Priority to PCT/SE1996/001315 priority patent/WO1997015116A2/en
Publication of SE9503616L publication Critical patent/SE9503616L/en
Publication of SE507550C2 publication Critical patent/SE507550C2/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356104—Bistable circuits using complementary field-effect transistors
    • H03K3/356113—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit
    • H03K3/356121—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit with synchronous operation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/096—Synchronous circuits, i.e. using clock signals
    • H03K19/0963—Synchronous circuits, i.e. using clock signals using transistors of complementary type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356017—Bistable circuits using additional transistors in the input circuit
    • H03K3/356026—Bistable circuits using additional transistors in the input circuit with synchronous operation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356017—Bistable circuits using additional transistors in the input circuit
    • H03K3/356034—Bistable circuits using additional transistors in the input circuit the input circuit having a differential configuration
    • H03K3/356043—Bistable circuits using additional transistors in the input circuit the input circuit having a differential configuration with synchronous operation

Landscapes

  • Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)

Abstract

Speed, robustness and static performance of TSPC (True Single Phase Clocking) latches and flipflops are analysed in this paper. New latches and flipflops are proposed to upgrade the overall speed, power saving, clock slope insensitivity and static performance of TSPC. Both new single-rail and new dual-rail latches and flipflops are proposed. Among them are different dynamic, semi-static and fully-static versions. The delays are reduced by factors of 1.3, 2.1, 2.2 and 2.4 for the single-rail dynamic, the dual-rail dynamic, the semi-static and the fully-static versions respectively. In the same time, power consumptions are also reduced so the power-delay products are reduced by factors of 1.9, 3.5, 3.4 and 6.5 respectively for an average activity rate (0.25). These improvements are accompanied with less transistor counts and less clock loads. One unique type of the proposed latches uses only a single clocked transistor and only n-transistors in logic (in both n- and p-latches and in both dynamic and static versions).
SE9503616A 1995-10-17 1995-10-17 Device at gates and flip-flops in the category of genuine single-phase clocked circuits SE507550C2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
SE9503616A SE507550C2 (en) 1995-10-17 1995-10-17 Device at gates and flip-flops in the category of genuine single-phase clocked circuits
PCT/SE1996/001315 WO1997015116A2 (en) 1995-10-17 1996-10-16 Tspc latches and flipflops

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SE9503616A SE507550C2 (en) 1995-10-17 1995-10-17 Device at gates and flip-flops in the category of genuine single-phase clocked circuits

Publications (3)

Publication Number Publication Date
SE9503616D0 true SE9503616D0 (en) 1995-10-17
SE9503616L SE9503616L (en) 1997-04-18
SE507550C2 SE507550C2 (en) 1998-06-22

Family

ID=20399844

Family Applications (1)

Application Number Title Priority Date Filing Date
SE9503616A SE507550C2 (en) 1995-10-17 1995-10-17 Device at gates and flip-flops in the category of genuine single-phase clocked circuits

Country Status (2)

Country Link
SE (1) SE507550C2 (en)
WO (1) WO1997015116A2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111027276A (en) * 2018-10-09 2020-04-17 刘保 Integrated circuit optimization system and method based on multiphase level sensitive latches

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19749521C2 (en) * 1997-11-08 1999-09-02 Temic Semiconductor Gmbh Bistable flip-flop
DE50008514D1 (en) 1999-06-07 2004-12-09 Infineon Technologies Ag FLIP FLOP CIRCUIT
US6778026B2 (en) * 2002-01-15 2004-08-17 Microtune (San Diego), Inc. High-speed phase frequency detection module
DE102004037591A1 (en) * 2004-08-03 2006-03-16 Infineon Technologies Ag Dual rail precharged flip-flop for use in intelligent chip cards has master-slave structure, master and slave each have dynamic input stage and are clocked by single-phase clock; precharge states in interior of flip-flop are high states
US9088285B2 (en) 2013-06-25 2015-07-21 Qualcomm Incorporated Dynamic divider having interlocking circuit
CN104378103B (en) * 2014-09-16 2017-08-04 哈尔滨工业大学（威海） Double track precharge logical cellular construction
CN106571825A (en) * 2016-11-07 2017-04-19 中山大学 Asynchronous clock signal generation circuit based on TSPC circuit
EP3574584B1 (en) 2017-01-24 2024-01-24 Telefonaktiebolaget LM Ericsson (publ) Variable delay circuits
US10840892B1 (en) 2019-07-16 2020-11-17 Marvell Asia Pte, Ltd. Fully digital, static, true single-phase clock (TSPC) flip-flop
CN112260682B (en) * 2020-10-26 2023-07-25 加特兰微电子科技(上海)有限公司 TSPC flip-flop, dual mode prescaler and divider related device

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59134918A (en) * 1983-01-24 1984-08-02 Toshiba Corp Latch circuit
US5311070A (en) * 1992-06-26 1994-05-10 Harris Corporation Seu-immune latch for gate array, standard cell, and other asic applications

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111027276A (en) * 2018-10-09 2020-04-17 刘保 Integrated circuit optimization system and method based on multiphase level sensitive latches

Also Published As

Publication number Publication date
WO1997015116A2 (en) 1997-04-24
WO1997015116A3 (en) 1997-05-15
SE9503616L (en) 1997-04-18
SE507550C2 (en) 1998-06-22

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