JP3178609B2 - Static type CMOS flip-flop circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ultra-high-speed CMOS flip-flop circuit operating in the GHz band, and more particularly to a low-power and ultra-high-speed prescaler IC which is a component of a frequency synthesizer used in a miniature portable telephone. It relates to a preferred circuit configuration method.

[0002]

2. Description of the Related Art With the development of the information society, automobile phones and
Demand for mobile communication devices such as mobile phones is growing rapidly. The most effective way to reduce the size and weight of these mobile communication devices is to reduce the battery volume and weight by reducing the power consumption of circuits used in frequency synthesizers such as prescalers. On the other hand, the frequency band allocated to this use is increasing in frequency due to the expansion of use of mobile communication. That is, 1.5 GHz from the conventional 800 MHz band
Bands and even the 3.0 GHz band are planned. In response to such a trend, there is an increasing demand for higher speeds of the above-described prescaler circuit and the like.

Under such circumstances, conventionally, the prescaler circuit has been constituted by a GaAs-IC or a Si bipolar IC. From the viewpoint of reducing the system cost and power consumption of mobile communication equipment, it is desirable to use a complete CMOS system, but it has been difficult for a conventional CMOS circuit to perform stable high-speed operation in the GHz band.

[0004] First, the conventional circuit technology of the CMOS flip-flop circuit, which is a component of the prescaler IC, will be outlined. Conventionally, CMOS flip-flop circuits include a dynamic type which is excellent in high-speed operation and a static type which is excellent in operation stability. 4 and 6 show typical circuit examples.

The dynamic flip-flop shown in FIG. 4 is composed of two clocked inverters, a master and a slave. In the figure, a P-channel transistor 41, an N-channel transistor 42, and a CMOS inverter 43 form a clocked inverter 44.
The P-channel transistor 45, the N-channel transistor 46, and the CMOS inverter 47 form a clocked inverter 48 and obtain an output Q. CMOS inverter 49
Constitutes a buffer circuit for obtaining an inverted output Q ′. This inverted output Q 'is fed back to the input D. The CMOS inverter 50 constitutes a buffer circuit for obtaining an inverted signal C ′ of the clock signal C for controlling each clocked inverter.

In the circuit of FIG. 4, the initial state is defined as clock signal = H (high level), output A of clocked inverter 44 = H, output Q of clocked inverter 48 = L (low level). Then, both P-channel transistor 41 and N-channel transistor 42 are turned off (non-conductive), so that clocked inverter 44 is in a non-operating state. Therefore, during the period when the clock signal is at H, the charge stored in the combined capacitance Cl (= Cj + Cg) of the source-drain junction capacitance Cj of the CMOS inverter 43 and the gate capacitance output Cg of the CMOS inverter 47 at the next stage is at the “H” level. The signal is maintained. On the other hand, since both the P-channel transistor 45 and the N-channel transistor 46 are turned on (conducting),
Clocked inverter 48 is operating. Therefore, the clocked inverter 48 receives the output A = “H” level of the clocked inverter 44 at the preceding stage, and receives “L”
Output level signal. Further, this output is inverted by the CMOS inverter 49 and becomes “H” level, and is fed back to the input D. In the period when the clock signal is at H, the combined capacitance C3 (= Cj + Cg) of the source-drain junction capacitance Cj of the CMOS inverter 49 and the gate capacitance Cg of the next-stage CMOS inverter 43 is equal to the power supply voltage VD.
It is charged at D (the same potential as the 'H' level).

Next, when the clock signal changes to the "L" level, the clocked inverter 44 is activated and the clocked inverter 48 is deactivated. As a result, the clocked inverter 44 receives the “H” level of the input D and outputs the “L” level. That is, during the period of the clock signal = L, the discharge of the combined capacitance Cl continues. On the other hand, the output Q has the “L” level signal held by the combined capacitor C2 because the clocked inverter 48 is in the inoperative state. While the signal level of the output Q is 'L' level and lower than the logic threshold value of the CMOS inverter 49,
The “H” level is fed back to input D.

Next, when the clock signal changes to the "H" level, the clocked inverter 44 becomes inactive , and
Clocked inverter 48 enters an operating state . As a result, the output A of the clocked inverter 44 is maintained at 'L' level, the signal level of the output Q changes from 'L' level to 'H' level, and the signal level of the inverted output Q 'changes from' H 'level to' H 'level. It changes to L 'level. Since the same change is repeated by the above clock signal change, the circuit operation of FIG. 4 is as shown in the waveform diagram of FIG.

The circuit shown in FIG. 4 is excellent in high-speed operation, and the inventors of the present invention have adopted a CM having a gate length of 0.2 μm class.
The above circuit is configured using the OS process, and a 3.2 GHz frequency division operation at a power supply voltage (VDD) of 2 V has been confirmed. FIG. 3 shows the power supply voltage dependence of the maximum operating frequency (literature: Y. Kado, Y. Okazaki, M. Suzuki, and T. Kobyashi; Elect).
ronics Letters, 1990, Vol. 26, No. 20, pp1684). Thereby, low power consumption, ultra-high speed CMOS,
The prospect of realizing LSI is obtained, and application to a low-power 3 GHz band frequency synthesizer used in mobile communication is expected in the future.

On the other hand, as a CMOS type static flip-flop excellent in operation stability, a flip-flop as shown in FIG. 6 has been used. In the figure, transfer gates 61, 62, 65, 66 and inverters 63, 6
Each of 4, 67, 68, 69, and 70 has a CMOS configuration including a P-channel transistor and an N-channel transistor. Inverter 64 with respect to inverter 63
The transfer gate 62 constitutes a feedback circuit, and has a function of holding a master-side signal when the transfer gate 62 is conductive. Similarly, inverter 6
7, 68 and the transfer gate 66 have a function of holding a signal on the slave side when the transfer gate 66 is conductive. The output Q on the slave side is the inverter 69
And is fed back to the input D. The CMOS inverter 70 constitutes a buffer circuit for obtaining an inverted signal C ′ of the clock signal C for controlling each transfer gate.

In the circuit of FIG. 6, the initial state is such that the clock signal = H (high level) and the output Q = L (low).
Level). Transfer gate 61 is turned on and transfer gate 62 is turned off, so that inverter 63 on the master side receives the input of the “H” level and outputs the “L” level. On the other hand, on the slave side, the transfer gate 65 is turned off,
Since the transfer gate 66 is turned on, the signal transmission path to the master side is cut off, and the output Q is kept at the low level.

Next, when the clock signal changes to the "L" level, the transfer gates 61 and 66 are turned off,
Transfer gates 62 and 65 are rendered conductive. As a result, the “L” level signal is held on the master side, and the “L” level signal is transmitted from the master side to the slave side through the transfer gate 65. Therefore, the output Q changes from 'L' level to 'H' level.

Next, when the clock signal changes to the "H" level, the transfer gates 61 and 66 are turned on and the transfer gates 62 and 65 are turned off. As a result, the “H” level signal is held on the slave side, and the “L” level signal is fed back to the input D from the slave side to the master side via the inverter 69. Since similar changes are repeated with the above clock signal changes, the circuit operation of FIG. 6 is as shown in the waveform diagram of FIG. FIG. 3 shows the power supply voltage dependency of the highest frequency division operating frequency when the above-described circuit is configured using a CMOS process having a gate length of 0.2 μm class. A 2 GHz operation can be performed at a power supply voltage of 2 V, and a flip-flop element that performs a signal holding operation is provided. Therefore, stable operation from a low frequency is possible.

[0014]

However, the conventional dynamic flip-flop shown in FIG. 4 has a problem that when the frequency of the clock signal decreases, the operation stability deteriorates. As described in the above description of the operation, the holding of the signal by the flip-flop element is performed by the CMOS.
This is performed by the electric charge stored in the combined capacitance Cl (= Cj + Cg) of the source-drain junction capacitance Cj of the inverter 43 (or 47 ) and the gate capacitance output Cg of the next-stage CMOS inverter 47 (or 49 ). However, the accumulated charge decreases with time due to leakage current at the source-drain junction and the gate oxide film, so that as the signal period increases, the signal level held decreases, and finally the logical threshold of the next-stage inverter It becomes below. as a result,
The next inverter is inverted and malfunctions. During this period, as the power supply voltage decreases, the amount of charge charged to the combined capacitance Cl (= Cj + Cg) decreases, and the period becomes more serious. As described above, the conventional CMOS dynamic flip-flop is excellent in high-speed operation, but has a problem in stable operation at a low frequency.

On the other hand, the conventional static flip-flop shown in FIG. 6 has a large number of elements and a large parasitic capacitance as compared with the dynamic flip-flop, so that the high-speed operation performance is poor as shown in FIG. Even with technology, 3G
It is difficult to apply to a frequency synthesizer of a small-sized mobile phone in the Hz band. Under such circumstances, a CMOS flip-flop circuit technology that operates in the GHz band at a low power supply voltage and operates stably independent of the operating frequency has been required.

An object of the present invention is to provide a C-type semiconductor having excellent operation stability.
While having the advantages of the MOS static flip-flop circuit, CMOS dynamic flip-flop parallel high-speed operation possible static CMOS flip off the
The present invention is to provide a flop circuit.

[0017]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention relates to a CMOS static flip-flop circuit having excellent operation stability, in which the characteristics of a transfer gate which controls the operation speed are determined. Improve
The main configuration feature is that a circuit means for reducing the load capacity of the inverter constituting the flip-flop element is provided.

[0018]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing the same embodiment in the case where a transfer gate is constituted by CMOS.
It is composed of a flip-flop circuit and a slave flip-flop circuit. That is, in the master flip-flop, the input / output terminal of the CMOS inverter 1 is a P-type channel MOS.
Through a CMOS transistor gate 3, 4 composed of a transistor and an N-type channel MOS transistor.
A flip-flop element is formed by interconnecting the input and output terminals of the MOS inverter 2. Similarly, in the slave flip-flop, the input / output terminal of the CMOS inverter 5 is connected to the CM via the CMOS transfer gates 7 and 8.
A flip-flop element is formed by interconnecting the input and output terminals of the OS inverter 6. The CM on the master side
Output signals of the OS inverters 1 and 2 are transmitted to the input sides of the CMOS inverters 5 and 6 on the slave side via the CMOS transfer gates 9 and 10, respectively. On the other hand, the output signals of the CMOS inverters 5 and 6 on the slave side are CMOS
The signal is fed back to the input terminals of the master-side CMOS inverters 1 and 2 via the transfer gates 11 and 12. The positive-phase timing pulse C is transferred to the transfer gates 7, 8,
11, 12 PMOS and transfer gate 3,
4, 9 and 10 respectively supplied to the gates of the NMOS, while
A timing pulse C ′ having a phase opposite to the above-mentioned timing pulse is generated through the CMOS inverter 15 and supplied to the PMOSs of the transfer gates 3, 4, 9, and 10 and the NMOS gates of the transfer gates 7, 8, 11, and 12, respectively. . The CMOS inverters 13 and 14 form buffer circuits for supplying outputs Q ′ and Q, respectively.

Here, in describing the circuit operation of FIG. 1,
Similar initial state as in FIG. 4, i.e. the clock signal Sunawa
A positive-phase timing pulse C = H (high level);
Output Q = L (low level). The transfer gates 3, 4, 9, and 10 are turned on, and the transfer gates 7, 8, 11, and 12 are turned off. The flip-flop element on the master side is in a signal holding state, and signals of “H” level and “L” level are sent to the CMOS inverters 5 and 6 on the slave side via the transfer gates 9 and 10 in the conductive state. Each is transmitted. Also, the CMOS inverter 5 on the slave side,
The output of 6 is fed back to the master side flip-flop element.

Next, when the clock signal C changes to the "L" level, the transfer gates 3, 4, 9, and 10 are turned off, and the transfer gates 7, 8, 11, and 12 are turned on. As a result, the flip-flop element on the slave side is in a signal holding state, and the signals of the “L” level and the “H” level are transmitted from the CMOS inverters 5 and 6 via the transfer gates 12 and 11 which are in a conductive state. The signals are fed back to the master-side CMOS inverters 2 and 1, respectively. Output Q is still at the 'L' level.

Next, when the clock signal changes to the "H" level, the transfer gates 3, 4, 9, and 10 are turned on, and the transfer gates 7, 8, 11, and 12 are turned off. The flip-flop element on the master side is in a state of holding a signal, and the transfer gates 9 and 10 which are in a conductive state from the CMOS inverters 1 and 2.
, The signals of the “L” level and the “H” level are transmitted to the CMOS inverters 5 and 6 on the slave side, respectively. As a result, the output Q is inverted to an “H” level signal. Since the same change is repeated by the above clock signal change, the circuit operation of FIG. 1 is as shown in the waveform diagram of FIG.

In the circuit shown in FIG.
The input terminal of the gate 12 is the input D in FIG. 4 or FIG.
And the input end of the transfer gate 11
D ′ (inverted input of input D). The circuit of FIG.
Since the above-described operation is performed, the inputs D and D ′ are undefined.
Even if the clock signal is input,
Q is output. The above is a brief description of the operation of the static flip-flop of the present invention. Factors that operate faster than the conventional static flip-flop shown in FIG. 6 are summarized in the following three points.

The first point is that the speed of signal transmission in the transfer gates 9, 10, 11, and 12 for transmitting signals between flip-flop elements is increased. In the circuit of the present invention, the potential difference between both ends immediately before the transfer gate changes from the non-conductive state to the conductive state (corresponding to the source-drain voltage of the MOS transistor forming the transfer gate) is almost always equal to the power supply voltage. (Corresponding to the potential difference between High level and Low level). Accordingly, a large current flows immediately after the timing pulse changes and the gate is turned on, so that the next CMOS
The gate capacity of the inverter can be charged and discharged in a short time. FIG.
Unlike the circuit of the present invention, the potential difference between both ends of the transfer gates 61 and 65 in the conventional static flip-flop circuit shown in (1) is not always ensured by the power supply voltage.

The second point is that the speed of signal propagation is increased by reducing the capacitive load of the CMOS inverters 1 and 2 constituting the flip-flop element. In the conventional static flip-flop circuit shown in FIG. 6, a gate capacitance of the CMOS inverter 64 and a junction capacitance of the transfer gate 65 exist as a capacitive load of the CMOS inverter 63. On the other hand, in the circuit of the present invention, the capacitive loads of the CMOS inverters 1 and 2 are transfer gates 9, 4, and 10, respectively.
3 is the junction capacitance. As the size of the gate oxide film becomes thinner as the transistor becomes finer, the junction capacitance becomes relatively smaller than the gate capacitance. Therefore, when a circuit is formed by transistors of the same size, the load capacitance of the circuit of the present invention is smaller.

Third, since the circuit of the present invention transmits two-phase signals in parallel between the master flip-flop and the slave flip-flop, in order to generate an inverted signal of the output Q required for the frequency division operation, There is no need to go through a CMOS inverter. As shown in FIG. 1 , the outputs of the CMOS inverters 5 and 6 are fed back to the opposite-phase signal lines. On the other hand, in the conventional circuit, the reverse phase signal is fed back via the CMOS inverter 69. In the case where the output of the transfer gate 65 is fed back, two stages of transfer gates continue in the signal path, and the operation becomes unstable and there is no driving force, so that the signal delay increases.

FIG. 3 shows the power supply voltage dependency of the highest frequency-divided operation frequency when the above-described circuit is formed using a CMOS process having a gate length of 0.2 μm class. Power supply voltage 2
At V or higher, high-speed operation performance comparable to that of the dynamic flip-flop shown in FIG. 4 is exhibited. Even at a power supply voltage of 2 V or less, it shows higher speed performance than the conventional static flip-flop shown in FIG. In addition, since a signal holding operation is involved in principle, stable performance is exhibited even at a low frequency operation.

[0027]

As described above, by using the static CMOS flip-flop circuit of the present invention, a stable operation is ensured irrespective of the operating frequency, and a high-speed frequency dividing operation of a maximum of 3 GHz with a low power supply voltage of 2V. Becomes possible.
This makes it possible to use CMOS for prescaler circuits and the like used in frequency synthesizers and the like of next-generation mobile communication devices.
Is realized, and the power consumption and cost of the system can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a signal waveform diagram for explaining the operation of the embodiment of FIG.

FIG. 3 is a power supply voltage dependence characteristic diagram of the maximum frequency-divided operation frequency of the conventional circuit and the circuit according to the present invention.

FIG. 4 is a circuit diagram showing an example of a conventional CMOS dynamic flip-flop circuit.

FIG. 5 is a signal waveform diagram for explaining the operation of the conventional example of FIG.

FIG. 6 is a circuit diagram showing an example of a conventional CMOS static flip-flop circuit.

FIG. 7 is a signal waveform diagram for explaining the operation of the conventional example of FIG.

[Explanation of symbols]

1,2,5,6 CMOS inverter 3,4,7,8,9,10,11,12 CMOS transfer gate 41,45 P-channel transistor 42,46 N-channel transistor 43,47,50 CMOS inverter 44,48, 49 Clocked Inverter 61,62,65,66 Transfer Gate 63,64,67,68,69,70 Inverter

Claims (1)

(57) [Claims] 1. An output terminal of a first CMOS inverter is connected to an input terminal of a second CMOS inverter via a first transfer gate, and an output terminal of the second CMOS inverter is connected via a second transfer gate. The first
A master flip-flop element connected to the input terminal of the CMOS inverter, and the output terminal of the third CMOS inverter connected to the input terminal of the fourth CMOS inverter via the third transfer gate. A slave flip-flop element having an output terminal of a CMOS inverter connected to an input terminal of the third CMOS inverter via a fourth transfer gate; and the first and second slave flip-flop elements of the master flip-flop element. Of the slave flip-flop element are connected to input terminals of third and fourth CMOS inverters of the slave flip-flop element via fifth and sixth transfer gates, respectively. The output signals of the third and fourth CMOS inverters are connected to the seventh and eighth transistors. The timing pulse is fed back to the input terminals of the second and first CMOS inverters of the master flip-flop element via a transfer gate, and a timing pulse is supplied to the gates of the first, second, fifth and sixth transfer gates. Then, a timing pulse having a phase opposite to that of the timing pulse is supplied to the gates of the third, fourth, seventh, and eighth transfer gates, and each of the first to eighth transfer gates is a CMOS transistor .
A transfer gate, wherein each of the first to fourth CMOS inverters and the
Each of the first to eighth transfer gates corresponds to a gate capacitance.
Comparing transistors with smaller junction capacitance
A static CMOS flip-flop circuit.