JP3178610B2 - Static CMOS flip-flop circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ultra-high-speed CMOS flip-flop circuit operating in the GHz band, and more particularly to a low-power and ultra-high-speed prescaler IC which is a component of a frequency synthesizer used in a miniature portable telephone. It relates to a preferred circuit configuration method.

[0002]

2. Description of the Related Art With the development of the information society, automobile phones and
Demand for mobile communication devices such as mobile phones is growing rapidly. The most effective way to reduce the size and weight of these mobile communication devices is to reduce the battery volume and weight by reducing the power consumption of circuits used in frequency synthesizers such as prescalers. On the other hand, the frequency band allocated to this use is increasing in frequency due to the expansion of use of mobile communication. That is, 1.5 G from the conventional 800 MHz band
The Hz band and further the 3.0 GHz band are planned. In response to such a trend, there is an increasing demand for higher speeds of the above-described prescaler circuit and the like.

Under such circumstances, conventionally, the prescaler circuit has been constituted by a GaAs-IC or a Si bipolar IC. From the viewpoint of reducing the system cost and power consumption of mobile communication equipment, it is desirable to use a complete CMOS system, but it has been difficult for a conventional CMOS circuit to perform stable high-speed operation in the GHz band.

[0004] First, the conventional circuit technology of the CMOS flip-flop circuit, which is a component of the prescaler IC, will be outlined. Conventionally, CMOS flip-flop circuits include a dynamic type which is excellent in high-speed operation and a static type which is excellent in operation stability. The dynamic circuit of clock de inverter type in which most excellent high speed in FIG. 1, showing each representative static circuit in FIG 3.

The dynamic flip-flop shown in FIG. 1 comprises two clocked inverters, a master and a slave. In FIG. 1, a P-channel transistor 1, an N-channel transistor 2, and a CMOS inverter 3 constitute a clocked inverter 4. P-channel transistor 5, N-channel transistor 6, CM
The OS inverter 7 constitutes a clocked inverter 8,
Obtain the output Q. The CMOS inverter 9 forms a buffer circuit for obtaining an inverted output Q '. This inverted output Q 'is fed back to the input D. The CMOS inverter 10 has a clock signal C for controlling each of the clocked inverters.
Of a buffer circuit for obtaining an inverted signal C ′ of the above.

In the circuit of FIG. 1, the initial state is such that the clock signal C = H (high level), the output A of the clocked inverter 4 = H, and the output Q of the clocked inverter 8
= L (low level). Then, both P-channel transistor 1 and N-channel transistor 2 are turned off (non-conductive), so that clocked inverter 4 is in a non-operating state. Therefore, the clock signal C = H
During the period, the signal at the “H” level is maintained by the charge stored in the combined capacitance Cl (= Cj + Cg) of the source-drain junction capacitance Cj of the CMOS inverter 3 and the gate capacitance output Cg of the CMOS inverter 7 in the next stage. . On the other hand, the P-channel transistor 5 and the N-channel transistor 6 are both turned on (conducting), so that the clocked inverter 8 is operating. Therefore, the clocked inverter 8 receives the output A = “H” level of the preceding clocked inverter 4 and outputs a signal of “L” level. Further, this output is inverted by the CMOS inverter 9 to become “H” level and is fed back to the input D. During the period of the clock signal C = H, the source-drain junction capacitance Cj of the CMOS inverter 9 and the next stage C
Combined capacitance C3 with gate capacitance Cg of MOS inverter 3
(= Cj + Cg) is charged with the power supply voltage VDD (the same potential as the “H” level).

Next, when the clock signal C changes to the "L" level, the clocked inverter 4 is activated and the clocked inverter 8 is deactivated. as a result,
The clocked inverter 4 receives the "H" level of the input D and outputs the "L" level. That is, the clock signal C = L
In the period, the discharge of the combined capacitance Cl continues. On the other hand, the output Q
Since the clocked inverter 8 is in an inactive state, the signal at the “L” level is generated by the combined capacitance C2 (the combined capacitance of the source-drain junction capacitance Cj of the CMOS inverter 7 and the gate capacitance Cg of the next-stage CMOS inverter 9). Is held. When the signal level of output Q is 'L'
The “H” level is fed back to the input D while it is kept below the logical threshold value of the S inverter 9.

[0008] Then the clock signal changes 'H' level, the clocked inverter 4 becomes inoperative, the clocked inverter 8 becomes operating state. As a result, the output A of the clocked inverter 4 is maintained at 'L' level, the signal level of the output Q changes from 'L' level to 'H' level, and the signal level of the inverted output Q 'changes from' H 'level to' H 'level. It changes to L 'level. Since the same change is repeated by the above clock signal change, the circuit operation of FIG.
It becomes like the waveform diagram of.

The circuit shown in FIG. 1 is excellent in high-speed operation, and the present inventors have developed a CM having a gate length of 0.2 μm class.
The above circuit is configured using the OS process, and a 3.2 GHz frequency division operation at a power supply voltage (VDD) of 2 V has been confirmed. FIG. 10 shows the power supply voltage dependence of the maximum operating frequency (references: Y. Kado, Y. Okazaki, M. Suzuki, and T. Kobayashi;
Electronics Letters, 1990, Vol. 26, No. 20, pp1684). As a result, low power consumption and ultra-high-speed CM operating in GHz band
The prospect of OS / LSI realization is obtained, and application to a low power 3 GHz band frequency synthesizer used in mobile communication is expected in the future.

On the other hand, as a CMOS type static flip-flop excellent in operation stability, a flip-flop as shown in FIG. 3 has been used. In FIG. 3, transfer gates 31, 32, 35, 36 and inverters 33, 3
Each of 4, 37, 38, 39, and 10 has a CMOS configuration including a P-channel transistor and an N-channel transistor. Inverter 34 versus inverter 34
The transfer gate 32 forms a feedback circuit, and has a function of holding a master-side signal when the transfer gate 32 is in a conductive state. Similarly, inverter 3
7, 38 and the transfer gate 36 have a function of holding a signal on the slave side when the transfer gate 36 is conductive. The output Q on the slave side is the inverter 39
And is fed back to the input D. The CMOS inverter 10 constitutes a buffer circuit for obtaining an inverted signal C 'of the clock signal C for controlling each transfer gate.

In the circuit of FIG. 3, the initial state is such that the clock signal C = H (high level) and the output Q = L (lo
w level). Transfer gate 31 is turned on, and transfer gate 32 is turned off, so that master-side inverter 33 receives the "H" level input and outputs the "L" level. On the other hand, on the slave side, the transfer gate 35 is turned off and the transfer gate 36 is turned on.
The signal transmission path to the master side is cut off, and the output Q
w level is held.

Next, when the clock signal changes to the "L" level, the transfer gates 31 and 36 are turned off,
The transfer gates 32 and 35 become conductive. As a result, the "L" level signal is held on the master side, and the "L" level signal is transmitted from the master side to the slave side through the transfer gate 35. Therefore, the output Q changes from 'L' level to 'H' level.

Next, when the clock signal changes to the "H" level, the transfer gates 31 and 36 are turned on and the transfer gates 32 and 35 are turned off. As a result, the "H" level signal is held on the slave side, and the "L" level signal is fed back to the input D from the slave side to the master side via the inverter 39. Since the same change is repeated by the above clock signal change, the circuit operation of FIG. 3 is as shown in the waveform diagram of FIG. FIG. 10 shows the power supply voltage dependency of the highest frequency division operating frequency when the above-described circuit is configured using a CMOS process having a gate length of 0.2 μm class. A 2 GHz operation can be performed at a power supply voltage of 2 V, and a flip-flop element that performs a signal holding operation is provided. Therefore, stable operation from a low frequency is possible.

[0014]

However, the conventional dynamic flip-flop shown in FIG. 1 has a problem that when the frequency of the clock signal decreases, the operation stability deteriorates. As described in the above description of the operation, the holding of the signal by the flip-flop element is performed by the CMOS.
Source-drain junction capacitance C of inverter 3 (or 7)
This is performed by the electric charge stored in the combined capacitance Cl (= Cj + Cg) of j and the gate capacitance output Cg of the next-stage CMOS inverter 7 (or 9). However, the accumulated charge decreases with time due to leakage current at the source-drain junction and the gate oxide film, so that as the signal period increases, the signal level held decreases, and finally the logical threshold of the next-stage inverter It becomes below. As a result, the next-stage inverter is inverted and malfunctions. This problem becomes more serious as the power supply voltage decreases, because the amount of charge charged to the combined capacitance Cl (= Cj + Cg) decreases. As described above, the conventional CMOS dynamic flip-flop is excellent in high-speed operation, but has a problem in stable operation at a low frequency.

On the other hand, the conventional static flip-flop shown in FIG. 3 has a large number of elements and a large parasitic capacitance as compared with the dynamic flip-flop. Therefore, as shown in FIG. Even with technology, 3
It is difficult to apply to a frequency synthesizer of a small-sized mobile phone in the GHz band. Under such circumstances, a CMOS flip-flop circuit technology that operates in the GHz band at a low power supply voltage and operates stably independent of the operating frequency has been required.

An object of the present invention is to provide a static CMOS flip-flop circuit having a signal holding operation function and operating stably even at a low frequency without impairing the high-speed performance of a conventional clocked inverter type dynamic circuit. Is to do.

[0017]

In order to achieve this object, a static CMOS flip-flop circuit according to the present invention has a clock input terminal and opens and closes with a timing pulse applied to the clock input terminal. in CMOS flip-flop circuit composed of a plurality of inverter clocked gate type to be controlled, of the plurality of inverters, the first inverter (53,
707) is connected to the second inverter (56, 708).
Of the first inverter (53, 70).
7) is connected to the input terminal of the second inverter (56, 708), and is connected to the third inverter (59, 705).
Is connected to the output terminal of the first inverter (53, 707), and the output terminal of the fourth inverter (62, 706) is connected to the output terminal of the second inverter (56, 708). , The input terminal of the fifth inverter (65, 711) is connected to the output terminal of the sixth inverter (68, 712), and the output terminal of the fifth inverter (65, 711) is connected to the sixth inverter (65, 711). 68, 712), the output terminal of the seventh inverter (71, 709) is connected to the output terminal of the fifth inverter (65, 711), and the eighth inverter (74, 710). Is connected to the output terminal of the sixth inverter (68, 712), and the input terminal of the seventh inverter (71, 709) is connected to the output terminal of the third inverter (59, 705). And the eighth The input terminal of the inverter (74, 710) is connected to the output terminal of the fourth inverter (62, 706), and the input terminal of the third inverter (59, 705) is connected to the eighth inverter (74, 710). ) is connected to the output end of the input of the fourth inverter (62,706) is connected to the output of the seventh inverter (71,709), a plurality of Lee Nba of the clocked gate type < For each of the data, a control PMOS transistor and a control NMOS transistor are used, and a first timing pulse is sent as the timing pulse to the first, second and second timing pulses.
The control NMOS transistors of the seventh and eighth inverters
Gates and the third, fourth, fifth, and sixth gates
A second timing pulse that is applied to each gate of the control PMOS transistor of the inverter and has a complementary relationship with the first timing pulse .
PMO for control of first, second, seventh and eighth inverters
Each gate and the third S transistor, fourth, fifth, and is configured to apply to the respective gates of the pre-SL system patronized NMOS transistor of the sixth inverter.

[0018]

[First Embodiment]

FIG. 5 is a circuit diagram showing a first embodiment of the present invention. This circuit comprises a master flip-flop circuit and a slave flip-flop circuit, and is configured using a clocked inverter as a basic gate. The clocked inverter circuit used in this circuit is a PMOS and an NMOS for control between a source electrode of a PMOS and a high potential side power supply and between a source electrode of an NMOS and a low potential side power supply of a CMOS inverter circuit. , And a complementary timing pulse is input to each of the gates of the control PMOS and NMOS to control the opening and closing of the gate.

In the master flip-flop circuit, the input and output terminals of the clocked inverter 53 are interconnected with the output and input terminals of the clocked inverter 56 to constitute a flip-flop element. Similarly, input of the clocked inverter 65,
The output terminal is interconnected with the output and input terminal of the clocked inverter 68 to form a flip-flop element. Output signals of master-side clocked inverters 59 and 62 are transmitted to slave-side clocked inverters 71 and 74, respectively. On the other hand, the output signals of the clocked inverters 71 and 74 on the slave side are output from the clocked inverters on the master side.
Cross feedback is provided to the input terminals of the inverters 62 and 59, respectively. The positive-phase timing pulse C is supplied to the PMOS and clocked inverters of the clocked inverters 59, 62, 65, 68.
The clocks are supplied to the gates of the NMOSs of the inverters 53, 56, 71, 74, respectively. 7
4 and the clocked inverters 59, 62,
65, 68 are supplied to the gates of the NMOS. CMO
S inverters 75 and 76 constitute buffer circuits for supplying output Q and inverted output Q ', respectively.

Here, in describing the circuit operation of FIG. 5,
An initial state similar to that of FIG. 1 , that is, a positive-phase clock signal (CLK), that is, a positive-phase timing pulse C 2 = H (h
(high level) and output Q = L (low level). Clocked inverters 53, 56, 71 and 74 are turned on, and clocked inverters 59, 62,
65 and 68 become non-conductive. The flip-flop element on the master side is in the state of holding the signal, and at the same time, the signals of the “H” level and “L” level are transmitted to the input gates of the clocked inverters 71 and 74 on the slave side which are in the conductive state. Then, each signal is inverted and input to the gates of the inverters 75 and 76 of the output buffer, and at the same time, is fed back to the master side.

Next, when the clock signal changes to "L" level, the clocked inverters 53, 56, 71, 74
Become non-conductive, and clocked inverters 59, 6
2, 65 and 68 are in a conductive state. As a result, the flip-flop element on the slave side holds a signal, and the clocked inverters 59 and 62 on the master side, which have become conductive, transmit the returned "H" level and "L" level signals. Then, each signal is inverted and transmitted to the input gates of the clocked inverters 71 and 74 on the slave side. During this time, the clocked inverter 7
The output Q is still at the “L” level because the devices 1 and 74 are not conducting.

Next, when the clock signal changes to "H" level, the clocked inverters 53, 56, 71, 74
Become conductive, and clocked inverters 59, 6
2, 65, 68 are in a non-conductive state. At the same time as the flip-flop element on the master side is in the state of holding a signal, the input gates of the clocked inverters 71 and 74 on the slave side which are in the conductive state are set to the “L” level and the “H” level.
A level signal is transmitted. Each signal is inverted,
It is transmitted to inverters 75 and 76 of the output buffer. As a result, the output Q is inverted to an “H” level signal. Since the same change is repeated by the above clock signal change, the circuit operation of FIG. 5 is as shown in the waveform diagram of FIG.

The above is a brief description of the operation of the static flip-flop of the present invention. This circuit is basically configured based on the clocked inverter type dynamic circuit shown in FIG. That is, the signal holding function is realized by arranging the two circuits shown in FIG. 1 in parallel and connecting the output terminals of the corresponding clocked inverters by cross-coupled clocked inverters. The clocked inverter in this circuit is two times smaller than the circuit shown in FIG.
Since the load is doubled, there is a disadvantage in high speed. However, since Q and Q 'can be output in parallel, the inverter for Q' output required for the dynamic frequency divider can be removed from the critical path. It can be eliminated and the speed can be increased accordingly.
As a result, almost the same high-speed performance can be realized as a static circuit.

FIG. 10 shows the power supply voltage dependency of the highest frequency division operating frequency when the above circuit is formed using a CMOS process having a gate length of 0.2 μm class. The static flip-flop according to the present invention exhibits the same high-speed operation performance as the dynamic flip-flop shown in FIG. 1, and shows higher high-speed performance than the conventional static flip-flop shown in FIG. In addition, since a signal holding operation is involved in principle, stable performance is exhibited even at a low frequency operation.

[0025] The second and third embodiments of the present invention illustrated in Figure 7
An example of a circuit for performing this will be described. The clocked inverter used in the present circuit example (in FIG. 7, a portion surrounded by a dotted line corresponds to the clocked inverter) is the same as the configuration used in the first embodiment (see FIG. 1). It is the same, but the input points of the signal and the timing pulse are different. That is, in FIG. 7, a signal is input to the gate electrodes of the outer PMOS transistor 701 and the NMOS transistor 704, and the complementary timing pulse is applied to the inner PM transistor.
OS transistor 702 and NMOS transistor 703
Are input to the respective gate electrodes. Clocked inverters 705, 706, 707, and 708 constitute a master flip-flop element.
9, 710, 711 and 712 constitute a slave flip-flop element. Inverters 75 and 76 are output buffers, and inverter 10 generates timing pulses of opposite phases. Here, in describing the circuit operation of FIG.
An initial state similar to that of FIG. 5, that is, a positive-phase clock signal (CLK) = H (high level) and an output Q = L (lo)
(W level), a waveform of the output (Q) similar to that in FIG. 6 can be obtained. The configuration of the clocked inverter (portion surrounded by a dotted line) in this circuit example is the same as that of the first embodiment, but by changing the configuration, the number of elements is reduced to configure a flip-flop having similar performance. be able to. An example in that case will be described below.

[Second Embodiment] FIG. 8 shows a configuration example of a clocked inverter 84 employed in a second embodiment of the present invention. In this embodiment, a signal is input to the gate electrode of the NMOS transistor 82,
An output is taken from the drain electrode of the MOS transistor 82. Complementary timing pulses are input to the gate electrodes of the PMOS transistor 81 and the NMOS transistor 83, respectively. In this circuit, it is necessary to optimize the gate width ratio of the PMOS and the NMOS so that the noise margin of the logic threshold can be increased. By replacing the clocked inverter shown by the dotted line in FIG. 7 with the clocked inverter 84 shown in FIG. 8, an operation waveform similar to that of FIG. 6 can be obtained. However, clocked inverters 707, 708, 709, 71 shown by dotted lines in FIG.
For 0, the timing pulse is input in the opposite direction to that in FIG. The flip-flop circuit of the present embodiment
Signal to clocked inverter is NMOS transistor
Input to the gate electrode of the
Input compared to the circuit of Figure 5 input to the inverter gate
Operate faster because of the small gate capacitance.

Third Embodiment FIG. 9 shows a configuration example of a clocked inverter 94 employed in a third embodiment of the present invention. In the present embodiment, a signal is input to the gate electrode of the PMOS transistor 92,
An output is taken from the drain electrode of the MOS transistor 92. Complementary timing pulses are input to the gate electrodes of the PMOS transistor 91 and the NMOS transistor 93, respectively. In this circuit, it is necessary to optimize the gate width ratio of the PMOS and the NMOS so that the noise margin of the logic threshold can be increased. By replacing the clocked inverter shown by the dotted line in FIG. 7 with the clocked inverter 94 shown in FIG. 9, an operation waveform similar to that of FIG. 6 can be obtained. However, clocked inverters 707, 708, 709, and 710 shown by dotted lines in FIG.
, The timing pulse is input in the opposite direction to that in FIG. The flip-flop circuit of the present embodiment
The signal to the locked inverter is a PMOS transistor
92 is input to a single gate electrode,
Compared to the circuit of FIG.
Since the gate capacitance is small, it operates at higher speed.

As described in the above embodiments, various configurations of clocked inverters can be employed in configuring the static flip-flop of the present invention. In the above embodiment, the CMO with low power consumption during standby is used.
An example in which an SMO circuit is used has been described.
Of course, it is also possible to configure only with S. Furthermore, it is also possible to configure by mixing these circuits.

[0029]

As described above, by using the static CMOS flip-flop circuit of the present invention, a stable operation can be ensured irrespective of the operating frequency, and a high-speed frequency division operation comparable to that of the dynamic type can be realized. Become. This makes it possible to use a CMOS for a prescaler circuit or the like used in a frequency synthesizer or the like of a next-generation mobile communication device, thereby realizing a complete CMOS for an IC used in such a device, thereby reducing system consumption. Power consumption and cost reduction can be achieved.

[Brief description of the drawings]

FIG. 1 is a conventional clocked inverter type CMOS dynamic flip-flop circuit diagram.

FIG. 2 is a signal waveform diagram for explaining an operation of the circuit of FIG. 1;

FIG. 3 is a conventional CMOS static flip-flop circuit diagram.

FIG. 4 is a signal waveform diagram for explaining an operation of the circuit of FIG. 3;

FIG. 5 is a circuit diagram showing a first embodiment of the present invention.

FIG. 6 is a signal waveform diagram for explaining the operation of the embodiment of FIG.

FIG. 7 is a circuit diagram for explaining second and third embodiments of the present invention.

FIG. 8 shows a clocked clock employed in the second embodiment of the present invention.
FIG. 3 is a circuit diagram illustrating a configuration example of an inverter.

FIG. 9 shows a clocked clock employed in a third embodiment of the present invention.
FIG. 3 is a circuit diagram illustrating a configuration example of an inverter.

FIG. 10 is a power supply voltage dependence characteristic diagram of the highest frequency division operating frequency of the conventional circuit and the circuit of the present invention.

[Explanation of symbols]

1,5 P-channel transistor 2,6 N-channel transistor 3,7,9,10,75,76 CMOS inverter 4,8,53,56,59,62,65,68,71,
74, 705, 706707, 708, 709, 71
0,711,712 clocked inverters 31, 32, 35, 36 transfer gate 33,34,37,38,39 inverter 81,91,92, 701, 702 PMOS transistor 82,83,93,703, 704 NMOS transistor

Claims (3)

(57) [Claims] 1. A CMOS flip-flop circuit having a clock input terminal and comprising a plurality of clocked gate type inverters whose opening and closing are controlled by a timing pulse applied to the clock input terminal, among the plurality of inverters of the gate type, the input terminal of the first inverter (3) is connected to the output terminal of the second inverter (5 6), the first inverter (5
The output terminal of 3) is connected to the input of the inverter second (5 6), the output terminal of the third inverter (5 9) is connected to the output terminal of said first inverter (3), fourth output terminal of the inverter (6 2) is connected to the output of the second inverter (5 6), the input terminal of the fifth inverter (6 5) the output of the inverter (6 8) of the sixth And the fifth inverter (6
The output terminal of the 5) is connected to the input terminal of the inverter of the sixth (6 8), the output end of the seventh inverter (71) is connected to the output terminal of said fifth inverter (6 5), the output terminal of the eighth inverter (7 4) the sixth inverter connected to an output terminal (6 8), the seventh input terminal of the inverter (71) of said third inverter (5 9) And an input terminal of the eighth inverter (74 ) is connected to an output terminal of the fourth inverter (6).
Is connected to the output terminal of 2), the third input terminal of the inverter (5 9) is connected to the output terminal of said eighth inverter (7 4), the input terminal of the fourth inverter (6 2) Is the seventh inverter (7
Each of the plurality of clocked gate type inverters is connected to the output terminal of 1) , and a control PMOS transistor is inserted between the source electrode of the PMOS transistor of the CMOS inverter circuit and the high potential side power supply. N of CMOS inverter circuit
A control NMOS transistor is inserted between a source electrode of the MOS transistor and a low-potential-side power supply, wherein a first timing pulse is used as the timing pulse and the first, second, seventh, and eighth inverters are used. The gates of the control NMOS transistor and the third
The second timing pulse, which is applied to each gate of the control PMOS transistor of the fourth, fifth, and sixth inverters and is complementary to the first timing pulse, is supplied to the first, second, and second inverters. The gates of the control PMOS transistors of the seventh and eighth inverters and the control N of the third, fourth, fifth and sixth inverters
A static CMOS flip-flop circuit characterized in that the voltage is applied to each gate of a MOS transistor. 2. A CMOS flip-flop circuit having a clock input terminal and comprising a plurality of clocked gate type inverters whose opening and closing are controlled by a timing pulse applied to the clock input terminal, among the plurality of inverters of the gate type, the input terminal of the first inverter (707) is connected to the output terminal of the second inverter (7 08), said first inverter
The output end of the (7 07) is connected to the input terminal of the second inverter (7 08), an output terminal of the third inverter (7 05) is connected to the output of said first inverter (707) The output of the fourth inverter ( 706) is connected to the second inverter ( 706).
8), the input terminal of the fifth inverter ( 711) is connected to the output terminal of the sixth inverter ( 712), and the fifth inverter ( 711) is connected to the output terminal of the sixth inverter ( 712).
The output end of the (7 11) is connected to the input terminal of the inverter (7 12) of the sixth, the output terminal of the inverter (7 09) of the seventh connected to the output of said fifth inverter (7 11) The output terminal of the eighth inverter ( 710) is connected to the sixth inverter ( 71).
2) The input terminal of the seventh inverter ( 709) is connected to the output terminal of the third inverter ( 705), and the input terminal of the eighth inverter ( 710). Is the fourth inverter
( 706), the input terminal of the third inverter ( 705) is connected to the output terminal of the eighth inverter ( 710), and the output terminal of the fourth inverter ( 706). The input terminal is the seventh inverter
( 709), wherein each of the plurality of clocked gate type inverters comprises: a drain electrode of an NMOS transistor which inputs a signal to a gate electrode and outputs a signal from the drain electrode; And a control NMOS transistor is inserted between the source electrode of the NMOS transistor and the low-potential-side power supply. A first timing pulse is used as the timing pulse. The gates of the control NMOS transistors of the first, second, seventh, and eighth inverters and the third
The second timing pulse, which is applied to each gate of the control PMOS transistor of the fourth, fifth, and sixth inverters and is complementary to the first timing pulse, is supplied to the first, second, and second inverters. The gates of the control PMOS transistors of the seventh and eighth inverters and the control N of the third, fourth, fifth and sixth inverters
A static CMOS flip-flop circuit characterized in that the voltage is applied to each gate of a MOS transistor. 3. A CMOS flip-flop circuit having a clock input terminal and comprising a plurality of clocked gate type inverters whose opening and closing are controlled by a timing pulse applied to the clock input terminal, among the plurality of inverters of the gate type, the input terminal of the first inverter (707) is connected to the output terminal of the second inverter (7 08), said first inverter
The output end of the (7 07) is connected to the input terminal of the second inverter (7 08), an output terminal of the third inverter (7 05) is connected to the output of said first inverter (707) The output of the fourth inverter ( 706) is connected to the second inverter ( 706).
8), the input terminal of the fifth inverter ( 711) is connected to the output terminal of the sixth inverter ( 712), and the fifth inverter ( 711) is connected to the output terminal of the sixth inverter ( 712).
The output end of the (7 11) is connected to the input terminal of the inverter (7 12) of the sixth, the output terminal of the inverter (7 09) of the seventh connected to the output of said fifth inverter (7 11) The output terminal of the eighth inverter ( 710) is connected to the sixth inverter ( 71).
2) The input terminal of the seventh inverter ( 709) is connected to the output terminal of the third inverter ( 705), and the input terminal of the eighth inverter ( 710). Is the fourth inverter
( 706), the input terminal of the third inverter ( 705) is connected to the output terminal of the eighth inverter ( 710), and the output terminal of the fourth inverter ( 706). The input terminal is the seventh inverter
Each of the plurality of clocked gate type inverters is connected to an output terminal of ( 709) and is connected between a source electrode of a PMOS transistor that inputs a signal to a gate electrode and outputs a signal from a drain electrode and a high potential side power supply. A control PMOS transistor is inserted in between,
NMO for control between the drain electrode and the low potential side power supply
A first timing pulse as the timing pulse, and a gate of the control NMOS transistor of the first, second, seventh and eighth inverters and the third and third transistors;
The second timing pulse, which is applied to each gate of the control PMOS transistor of the fourth, fifth, and sixth inverters and is complementary to the first timing pulse, is supplied to the first, second, and second inverters. The gates of the control PMOS transistors of the seventh and eighth inverters and the control N of the third, fourth, fifth and sixth inverters
A static CMOS flip-flop circuit characterized in that the voltage is applied to each gate of a MOS transistor.