JPH04258012A - Static cmos flip-flop circuit - Google Patents

Abstract

PURPOSE:To stably operate the flip-flop circuit even at a low frequency by arranging two clocked inverter dynamic circuits in parallel and connecting an output terminal of a relevant inverter to cross-coupled inverters. CONSTITUTION:The flip-flop circuit consists of a master flip-flop circuit and a slave flip-flop circuit and a clocked inverter is adopted for a basic gate. An input output terminal of the clocked inverter 53 of the master flip-flop circuit is interconnected to an output input terminal of a clocked inverter 56 to form a flip-flop element and similarly an input output terminal of the clocked inverter 65 of the slave flip-flop circuit is interconnected to an output/input terminal of a clocked inverter 68 to form a flip-flop element. Thus, the signal latch function is realized without losing the high speed performance of the clocked inverter dynamic circuit.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to ultra-high-speed CMOS flip-flop circuits that operate in the GHz band, and in particular to low-power, ultra-high-speed prescaler ICs that are components of frequency synthesizers used in ultra-compact mobile phones and the like. The present invention relates to a preferred circuit configuration method.

0002

[Background Art] With the advancement of the information society, car telephones and
Demand for mobile communication devices such as mobile phones is rapidly increasing. The most effective way to reduce the size and weight of these mobile communication devices is to reduce battery volume and weight by reducing the power consumption of circuits used in frequency synthesizers such as prescalers. On the other hand, with the expansion of the use of mobile communications, the frequency bands allocated for this purpose are becoming increasingly high-frequency. In other words, 1.5G from the conventional 800MHz band
Hz band and even 3.0 GHz band are planned. In response to these trends, there is an increasing demand for faster speeds for the above-mentioned prescaler circuits and the like.

Under these circumstances, conventional prescaler circuits have been constructed of GaAs-ICs or Si bipolar ICs. From the viewpoint of reducing system cost and power consumption of mobile communication equipment, it is desirable to make the entire system completely CMOS, but it has been difficult for conventional CMOS circuits to operate stably and at high speed in the GHz band.

[0004] First, the conventional circuit technology for CMOS flip-flop circuits, which are the constituent elements of prescaler ICs, will be reviewed. Conventionally, there are two types of CMOS flip-flop circuits: a dynamic type that has excellent high-speed operation, and a static type that has excellent operational stability. FIG. 1 shows a Clod inverter type dynamic circuit, which has the highest speed performance, and FIG. 3 shows a typical static circuit.

The dynamic flip-flop shown in FIG. 1 is composed of two clocked inverters, a master and a slave. In FIG. 1, a P-channel transistor 1, an N-channel transistor 2, and a CMOS inverter 3 constitute a clocked inverter 4. P-channel transistor 5, N-channel transistor 6, CM
The OS inverter 7 constitutes a clocked inverter 8,
Obtain output Q. CMOS inverter 9 constitutes a buffer circuit that obtains an inverted output Q'. This inverted output Q' is fed back to the input D. The CMOS inverter 10 receives a clock signal C for controlling each of the clocked inverters described above.
A buffer circuit for obtaining an inverted signal C' is constructed.

In the circuit shown in FIG. 1, the initial state is as follows: clock signal = H (high level), output A of clocked inverter 4 = H, output Q of clocked inverter 8 =
It is defined as L (low level). Then, P-channel transistor 1 and N-channel transistor 2 are both turned off (
Since the clocked inverter 4 is in a non-conducting state, the clocked inverter 4 is in an inoperative state. Therefore, during the period when the clock signal = H, the source-drain junction capacitance Cj of the CMOS inverter 3 and the gate capacitance output C of the next stage CMOS inverter 7
The 'H' level signal is maintained by the charge stored in the combined capacitance Cl (=Cj+Cg) of g. On the other hand, P
Since channel transistor 5 and N-channel transistor 6 are both in an on (conductive) state, clocked inverter 8 is in an operating state. Therefore, the clocked inverter 8 outputs the output A=' of the clocked inverter 4 in the previous stage.
Upon receiving the H' level, it outputs a 'L' level signal. Furthermore, this output is inverted by the CMOS inverter 9 to become an 'H' level and fed back to the input D. During the period when the clock signal = H, the source-drain junction capacitance Cj of the CMOS inverter 9 and the CMOS of the next stage are
Combined capacitance C3 (=C
j+Cg) is the power supply voltage VDD (same potential as 'H' level)
will be charged.

Next, when the clock signal changes to 'L' level, clocked inverter 4 becomes active and clocked inverter 8 becomes inactive. As a result, the clocked inverter 4 receives the 'H' level of the input D and outputs the 'L' level. That is, during the period when the clock signal=L, the combined capacitance Cl continues to be discharged. On the other hand, since the clocked inverter 8 is inactive, the output Q is a composite capacitance C2 (source-drain junction capacitance Cj of the CMOS inverter 7 and gate capacitance C of the next stage CMOS inverter 9).
The 'L' level signal is held by the combined capacitance with g. While the signal level of the output Q is kept at 'L' level and below the logic threshold of the CMOS inverter 9, '
The H' level is fed back to input D.

Next, when the clock signal changes to 'H' level, clocked inverter 4 becomes active and clocked inverter 8 becomes inactive. As a result, the output A of the clocked inverter 4 is maintained at the 'L' level, the signal level of the output Q changes from the 'L' level to the 'H' level, and the signal level of the inverted output Q' changes from the 'H' level to the 'H' level.
Changes to L' level. Since similar changes are repeated due to changes in the clock signal as described above, the circuit operation of FIG. 1 becomes as shown in the waveform diagram of FIG. 2.

The circuit shown in FIG. 1 has excellent high-speed operation, and the inventors of the present application have developed a circuit with a gate length of 0.2 μm class.
The above circuit is constructed using a MOS process, and frequency division operation of 3.2 GHz has been confirmed at a power supply voltage (VDD) of 2 V. Figure 10 shows the power supply voltage dependence of the maximum operating frequency (
Literature: Y. Kado, Y. Okazaki, M. Suz
uki, and T. Kobayashi; Elect
ronics Letters, 1990, Vol. 2
6, No. 20, pp1684). As a result, G.H.
The results provide prospects for the realization of low power consumption, ultra-high speed CMOS LSIs that operate in the Z band, and are expected to be applied to low power, 3 GHz band frequency synthesizers used in mobile communications in the future.

On the other hand, as a CMOS-structured static flip-flop with excellent operational stability, the one shown in FIG. 3 has been used. In FIG. 3, transfer gates 31, 32, 35, 36 and inverters 33, 3
4, 37, 38, 39, and 10 all have a CMOS configuration consisting of a P channel transistor and an N channel transistor. Inverter 34 versus inverter 33
The transfer gate 32 and the transfer gate 32 constitute a feedback circuit, and have a function of holding a signal on the master side when the transfer gate 32 is in a conductive state. Similarly, inverter 3
7, 38 and the transfer gate 36 have a function of holding a signal on the slave side when the transfer gate 36 is in a conductive state. Output Q on the slave side is inverter 39
is inverted and fed back to input D. The CMOS inverter 10 constitutes a buffer circuit for obtaining an inverted signal C' of the clock signal C for controlling each of the transfer gates.

In the circuit shown in FIG. 3, the initial state is as follows: clock signal = H (high level), output Q = L (low level).
level). Since the transfer gate 31 is in a conductive state and the transfer gate 32 is in a non-conductive state, the inverter 33 on the master side receives an input at an 'H' level and outputs an 'L' level. On the other hand, on the slave side, the transfer gate 35 is in a non-conductive state,
Since the transfer gate 36 becomes conductive, the signal transmission path with the master side is cut off, and the output Q is maintained at a low level.

Next, when the clock signal changes to the 'L' level, the transfer gates 31 and 36 become non-conductive;
Transfer gates 32 and 35 become conductive. As a result, the 'L' level signal is held on the master side, and the transfer gate 3 is transferred from the master side to the slave side.
5, an 'L' level signal is transmitted. Therefore,
Output Q changes from 'L' level to 'H' level.

Next, when the clock signal changes to ``H'' level, transfer gates 31 and 36 become conductive and transfer gates 32 and 35 become non-conductive. As a result, the 'H' level signal is held on the slave side, and the 'L' level signal is fed back to the input D from the slave side to the master side via the inverter 39. In order to repeat the same change due to the above clock signal change, as shown in Figure 3.
The circuit operation is as shown in the waveform diagram of FIG. FIG. 10 shows the dependence of the maximum divided operating frequency on the power supply voltage when the above circuit is constructed using a CMOS process having a gate length of 0.2 μm class. It is possible to operate at 2 GHz with a power supply voltage of 2 V, and because it has a flip-flop element that performs a signal holding operation, stable operation is possible from low frequencies.

[0014]

However, the conventional dynamic flip-flop shown in FIG. 1 has a problem in that the stability of its operation deteriorates as the frequency of the clock signal decreases. As described in the operation description above, the signal is held by the flip-flop element due to the source-drain junction capacitance Cj of the CMOS inverter 3 (or 7).
and the charge stored in the composite capacitance Cl (=Cj+Cg) of the gate capacitance output Cg of the CMOS inverter 7 (or 9) at the next stage. However, the accumulated charge is
Since it decreases over time due to leakage current in the drain junction and gate oxide film, as the signal period becomes longer, the signal level held decreases until it falls below the logic threshold of the next stage inverter. As a result, the inverter at the next stage is inverted and malfunctions. This problem becomes more serious as the power supply voltage decreases because the amount of charge charged to the composite capacitance Cl (=Cj+Cg) decreases. As described above, the conventional CMOS dynamic flip-flop has excellent high speed performance, but has a problem in stable operation at low frequencies.

On the other hand, the conventional static type flip-flop shown in FIG. 3 has a larger number of elements and an increased parasitic capacitance than the dynamic type, and therefore has poor high-speed operation performance as shown in FIG. Even with technology, 3
It is difficult to apply it to frequency synthesizers of GHz band small mobile phones, etc. Under these circumstances, there has been a need for CMOS flip-flop circuit technology that operates in the GHz band with a low power supply voltage and operates stably without depending on the operating frequency.

An object of the present invention is to provide a static CMOS flip-flop circuit that has a signal holding function and operates stably even at low frequencies without impairing the high speed of conventional clocked inverter type dynamic circuits. It's about doing.

[0017]

[Means for Solving the Problems] In order to achieve this object, a static CMOS flip-flop circuit according to the present invention has a clock input terminal and is opened and closed by a timing pulse applied to the clock input terminal. In a CMOS flip-flop circuit composed of a plurality of clocked gate type inverters controlled by
Among the plurality of inverters, the first inverter (53
, 707) is connected to the second inverter (56, 708).
), and the first inverter (53, 7
The output terminal of 07) is the second inverter (56, 708)
is connected to the input terminal of the third inverter (59,705
) is connected to the output end of the first inverter (53, 707), and the output end of the fourth inverter (62, 706)
The output terminal of is connected to the output terminal of the second inverter (56, 708), the input terminal of the fifth inverter (65, 711) is connected to the output terminal of the sixth inverter (68, 712), The output terminal of the fifth inverter (65, 711) is connected to the input terminal of the sixth inverter (68, 712), and the output terminal of the seventh inverter (71, 709) is connected to the input terminal of the fifth inverter (68, 712). The output terminal of the eighth inverter (74, 710) is connected to the output terminal of the sixth inverter (68, 712), and the output terminal of the seventh inverter (71, 709) is connected to the output terminal of the sixth inverter (68, 712). ) is connected to the output end of the third inverter (59, 705), and the input end of the eighth inverter (74, 710) is connected to the output end of the fourth inverter (62, 706). The input terminal of the third inverter (59, 705) is connected to the output terminal of the eighth inverter (74, 710), and the input terminal of the fourth inverter (62, 706) is connected to the output terminal of the fourth inverter (62, 706). 7 inverters (71, 709), and applies a first timing pulse as the timing pulse to the clock input terminals of the first, second, seventh, and eighth inverters; A second timing pulse complementary to the first timing pulse is applied to the clock input terminals of the third, fourth, fifth, and sixth inverters.

[0018]

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings. [First Embodiment] FIG. 5 is a circuit diagram showing a first embodiment of the present invention. This circuit consists of a master flip-flop circuit and a slave flip-flop circuit, and is constructed using a clocked inverter as the basic gate. The clocked inverter circuit used in this circuit is a CMOS inverter circuit with a control PMOS and NMOS between the PMOS source electrode and the high potential side power supply and between the NMOS source electrode and the low potential side power supply. and complementary timing pulses to these control PMOS
This is a basic gate circuit that controls opening and closing of the gates by inputting them to the gates of the NMOS and NMOS.

In the master flip-flop circuit, the input and output terminals of the clocked inverter 53 are connected to the output and input terminals of the clocked inverter 56 to form a flip-flop element, and also in the slave flip-flop circuit. , Similarly, the input of the clocked inverter 65,
The output end of the clocked inverter 68 is interconnected with the output end and the input end of the clocked inverter 68 to form a flip-flop element. The output signals of clocked inverters 59 and 62 on the master side are transmitted to clocked inverters 71 and 74 on the slave side, respectively. On the other hand, the output signals of the clocked inverters 71 and 74 on the slave side are the clocked inverters 71 and 74 on the master side.
Cross feedback is provided to the input terminals of inverters 62 and 59, respectively. A timing pulse C of positive phase is supplied to the gates of PMOS of clocked inverters 59, 62, 65, 68 and NMOS of clocked inverters 53, 56, 71, 74, respectively, while a timing pulse C of opposite phase to the timing pulse The timing pulse C' is generated via the CMOS inverter 10, and the clocked inverters 53, 56, 71, 74
PMOS and clocked inverters 59, 62, 6
5 and 68 NMOS gates, respectively. CMOS
Inverters 75 and 76 have an output Q and an inverted output Q, respectively.
A buffer circuit is configured to supply each of '.

In explaining the circuit operation of FIG. 5,
The initial state is the same as in the case of FIG. 5, that is, the positive phase clock signal (CLK) = H (high level), the output Q =
w level). Clocked inverter 53,5
6, 71, and 74 become conductive, and clocked inverters 59, 62, 65, and 68 become non-conductive. The flip-flop element on the master side is in a signal holding state, and at the same time, 'H' level and 'L' level signals are transmitted to the input gates of the clocked inverters 71 and 74 on the slave side, which are in a conductive state. Each signal is inverted and input to the gates of inverters 75 and 76 of the output buffer, and simultaneously fed back to the master side.

Next, when the clock signal changes to 'L' level, the clocked inverters 53, 56, 71, 74
becomes non-conductive, and the clocked inverters 59, 6
2, 65, and 68 become conductive. As a result, the flip-flop elements on the slave side enter a signal holding state, and the clocked inverters 59 and 62 on the master side, which have become conductive, receive the fed back 'H' level and '
Upon receiving the L' level signal, each signal is inverted and transmitted to the input gates of clocked inverters 71 and 74 on the slave side. During this time, the clocked inverter 71
, 74 are non-conducting, so the output Q is still '
It is at L' level.

Next, when the clock signal changes to 'H' level, the clocked inverters 53, 56, 71, 74
becomes conductive, and the clocked inverters 59, 62
, 65, 68 become non-conductive. At the same time, the flip-flop element on the master side enters a signal holding state, and at the same time, 'L' level and 'H' level signals are transmitted to the input gates of the clocked inverters 71 and 74 on the slave side, which are in a conductive state. . Each signal is inverted and transmitted to inverters 75 and 76 of the output buffer. As a result, the output Q is inverted to an 'H' level signal. In order to repeat the same change due to the above clock signal change,
The circuit operation of FIG. 5 is as shown in the waveform diagram of FIG. 6.

The above is a brief explanation of the operation of the static flip-flop of the present invention, and this circuit is basically constructed on the clocked inverter type dynamic circuit shown in FIG. That is, the signal holding function is realized by arranging two circuits shown in FIG. 1 in parallel and connecting the output ends of the corresponding clocked inverters with cross-coupled clocked inverters. The clocked inverter in this circuit is 2 times smaller than the circuit shown in Figure 1.
Since it carries twice the load, there is a disadvantage in high speed, but since Q and Q' can be output in parallel, the inverter for Q' output, which was necessary for the dynamic frequency divider, can be removed from the critical path. This can be removed and the speed can be increased accordingly. As a result, almost the same high-speed performance can be achieved as a static circuit.

CMOS with gate length of 0.2 μm class
FIG. 10 shows the dependence of the maximum divided operating frequency on the power supply voltage when the above circuit is constructed using the process. The static flip-flop of the present invention exhibits high-speed operation performance comparable to that of the dynamic flip-flop shown in FIG. 1, and higher high-speed performance than the conventional static flip-flop shown in FIG. In addition, since it involves a signal holding operation in principle, it exhibits stable performance even during low frequency operation.

[Second Embodiment] FIG. 7 shows a second embodiment of the present invention. The clocked inverter used in this embodiment (the part surrounded by the dotted line in FIG. 7 corresponds to the clocked inverter) has the same configuration as that used in the first embodiment (see FIG. 1). They are the same, but the signal and timing pulse input points are different. That is, FIG.
, a signal is input to the gate electrodes of the outer PMOS transistor 701 and NMOS transistor 704,
Complementary timing pulses are input to the gate electrodes of inner PMOS transistor 702 and NMOS transistor 703, respectively. Clocked inverter 705, 70
6,707,708 constitute master flip-flop elements, and clocked inverters 709,710,7
11,712 constitutes a slave flip-flop element. Inverters 75 and 76 are output buffers, and inverter 10 generates timing pulses of opposite phase. Here, in explaining the circuit operation of FIG. 7, the initial state similar to that of FIG. 5, that is, the positive phase clock signal (CLK) = H
(high level) and output Q=L (low level), it is possible to obtain a waveform of the output (Q) similar to that shown in FIG. The configuration of the clocked inverter (the part surrounded by the dotted line) in this example was the same as in the first example, but by changing the configuration, the number of elements was reduced to configure a flip-flop with similar performance. be able to. An example is shown below.

[Third Embodiment] FIG. 8 shows an example of the configuration of a clocked inverter employed in a third embodiment of the present invention. In this embodiment, the signal is transferred to the NMOS transistor 82.
The input signal is input to the gate electrode of the NMOS transistor 82, and the output is taken out from the drain electrode of the NMOS transistor 82. Complementary timing pulses are input to the gate electrodes of PMOS transistor 81 and NMOS transistor 83, respectively. In this circuit, in order to have a large noise margin for the logic threshold,
It is necessary to optimize the gate width ratio of PMOS and NMOS. By replacing the clocked inverter shown by the dotted line in FIG. 7 with the clocked inverter shown in FIG. 8, operating waveforms similar to those shown in FIG. 6 can be obtained. However, the clocked inverter 70 shown by the dotted line in FIG.
7, 708, 709, and 710, the timing pulses are input in the opposite direction to that in the case of FIG.

[Fourth Embodiment] FIG. 9 shows an example of the configuration of a clocked inverter employed in a fourth embodiment of the present invention. In this embodiment, the signal is transmitted to the PMOS transistor 92.
The input signal is input to the gate electrode of the PMOS transistor 92, and the output is taken out from the drain electrode of the PMOS transistor 92. Complementary timing pulses are input to the gate electrodes of PMOS transistor 91 and NMOS transistor 93, respectively. In this circuit, P
It is necessary to optimize the gate width ratio of MOS and NMOS. Figure 9 shows the clocked inverter shown by the dotted line in Figure 7.
By replacing it with the clocked inverter shown in FIG. 9, operating waveforms similar to those shown in FIG. 9 can be obtained. however,
Clocked inverter 707, 7 shown in dotted line in FIG.
Regarding 08, 709, and 710, the timing pulses are input in the opposite direction to that in the case of FIG.

As described in the above embodiments, various configurations of clocked inverters can be employed in constructing the static flip-flop of the present invention. In the above embodiment, a CMO with low power consumption during standby
Although we have described an example of an S circuit, NMO, which has excellent high-speed performance,
Of course, it is also possible to configure it with only S. Furthermore, it is also possible to configure a mixture of these circuits.

[0029]

[Effects of the Invention] As explained above, by using the static type CMOS flip-flop circuit of the present invention, stable operation is ensured regardless of the operating frequency, and high-speed frequency division operation comparable to that of the dynamic type is possible. Become. This will make it possible to use CMOS for the prescaler circuits used in frequency synthesizers, etc. of next-generation mobile communication equipment, making it possible to completely convert the ICs used in these devices to CMOS, resulting in lower system consumption. Electricity and cost reduction can be achieved.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a conventional clocked inverter type CMOS dynamic flip-flop.

FIG. 2 is a signal waveform diagram for explaining the operation of the circuit in FIG. 1;

FIG. 3 is a conventional CMOS static flip-flop circuit diagram.

FIG. 4 is a signal waveform diagram for explaining the operation of the circuit in FIG. 3;

FIG. 5 is a circuit diagram showing a first embodiment of the present invention.

FIG. 6 is a signal waveform diagram for explaining the operation of the embodiment of FIG. 5;

FIG. 7 is a circuit diagram showing a second embodiment of the present invention.

FIG. 8 is a clocked system adopted in the third embodiment of the present invention.
FIG. 2 is a circuit diagram showing a configuration example of an inverter.

FIG. 9 is a clocked clock adopted in the fourth embodiment of the present invention.
FIG. 2 is a circuit diagram showing a configuration example of an inverter.

FIG. 10 is a power supply voltage dependence characteristic diagram of the maximum frequency division operating frequency of the conventional circuit and the circuit of the present invention.

[Explanation of symbols]

1,5 P channel transistor 2,6 N-channel transistor

Claims (1)

[Claims] 1. A CMOS flip-flop circuit comprising a plurality of clocked gate type inverters having a clock input terminal and whose opening and closing are controlled by timing pulses applied to the clock input terminal,
Among the plurality of inverters, the first inverter (53
, 707) is connected to the second inverter (56, 708).
), and the first inverter (53, 7
The output terminal of 07) is the second inverter (56, 708)
is connected to the input terminal of the third inverter (59,705
) is connected to the output end of the first inverter (53, 707), and the output end of the fourth inverter (62, 706)
The output terminal of is connected to the output terminal of the second inverter (56, 708), the input terminal of the fifth inverter (65, 711) is connected to the output terminal of the sixth inverter (68, 712), The output terminal of the fifth inverter (65, 711) is connected to the input terminal of the sixth inverter (68, 712), and the output terminal of the seventh inverter (71, 709) is connected to the input terminal of the fifth inverter (68, 712). The output terminal of the eighth inverter (74, 710) is connected to the output terminal of the sixth inverter (68, 712), and the output terminal of the seventh inverter (71, 709) is connected to the output terminal of the sixth inverter (68, 712). ) is connected to the output end of the third inverter (59, 705), and the input end of the eighth inverter (74, 710) is connected to the output end of the fourth inverter (62, 706). The input terminal of the third inverter (59, 705) is connected to the output terminal of the eighth inverter (74, 710), and the input terminal of the fourth inverter (62, 706) is connected to the output terminal of the fourth inverter (62, 706). 7 inverters (71, 709), and applies a first timing pulse as the timing pulse to the clock input terminals of the first, second, seventh, and eighth inverters; The inverter is configured to apply a second timing pulse complementary to the first timing pulse to the clock input terminals of the third, fourth, fifth, and sixth inverters. Static type CMOS flip-flop circuit.