CN112259554A - Thin film transistor array substrate and manufacturing method thereof - Google Patents
Thin film transistor array substrate and manufacturing method thereof Download PDFInfo
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- CN112259554A CN112259554A CN202011084353.6A CN202011084353A CN112259554A CN 112259554 A CN112259554 A CN 112259554A CN 202011084353 A CN202011084353 A CN 202011084353A CN 112259554 A CN112259554 A CN 112259554A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1296—Multistep manufacturing methods adapted to increase the uniformity of device parameters
Abstract
The invention provides a thin film transistor array substrate and a method for manufacturing the same, wherein a prism structure and a first contact hole are formed on a first insulating layer, wherein the first insulating layer comprises a first insulating film layer and a second insulating film layer which covers the first insulating film layer and has a higher etching rate than the first insulating film layer, when the first insulating layer is etched, because the etching rates of the first insulating film layer at the lower part and the second insulating film layer at the upper part of the first insulating layer are different, the prism structure finally formed can present a good taper angle through the guidance of the second insulating film layer with a larger etching rate, the light scattering capability is improved, and the hole wall of the first contact hole is also covered with the second insulating layer, so that the condition of undercut caused by simultaneously etching the first insulating layer and the second insulating layer corresponding to the first contact hole is avoided, and the risk of wire breakage of the pixel electrode filled into the contact hole subsequently is avoided.
Description
Technical Field
The invention relates to the technical field of liquid crystal display, in particular to a thin film transistor array substrate and a manufacturing method thereof.
Background
With the development of Display technology, Liquid Crystal Display (LCD) panels are becoming more popular because of their advantages of portability, low radiation, etc. The liquid crystal display panel includes opposing Color Filter substrates (CF) and thin film transistor array substrates (TFT array) and a liquid crystal layer (LC layer) interposed therebetween.
The brightness and contrast of the TFT-LCD products in the current market can be rapidly attenuated along with the increase of the viewing angle, so that the display effect of large-viewing-angle pictures is poor. Therefore, in order to improve the brightness and contrast of the product, a prism (Lens) technology is introduced to the TFT to scatter the incident light entering the TFT array substrate from the backlight module.
In the manufacturing process of the conventional thin film transistor array substrate, there are the following ways of forming prisms: for example, the prism structure is manufactured on the gate insulating layer and the first insulating layer above the gate insulating layer through the RIE etching mode, since the film quality of the first insulating layer basically presents uniformity (without modifying the film quality), there is a risk of excessive lateral erosion between the first insulating layer and the gate insulating layer, and the cross-sectional shape of the prism structure after etching is in two trapezoids and contains sharp corners, which easily causes the disconnection of subsequent films.
Aiming at the situation, the applicant finds that the prism structure has no effect by adjusting etching parameters such as etching gas flow rate (gas flow) and etching vacuum cavity pressure (EQ pressure) and the like, and the prism structure is still double-trapezoid and has a sharp corner in the optimization process; and etching the first insulating layer by step, namely etching away the first insulating layer by using an RIE etching mode, and etching away part of the gate insulating layer by using an ECCP mode, wherein the cross section of the prism structure is in a trapezoid shape, the sharp angle is improved, and the cross section similar to an arch shape is obtained, but the light scattering effect is still insufficient. It should be noted that, because openings (through holes) need to be simultaneously formed in the first insulating layer (the insulating layer covering the source and the drain) and the second insulating layer (the insulating layer between the pixel electrode and the common electrode) to connect and conduct the pixel electrode and the source/drain, in order to avoid undercutting (undercut) phenomenon due to the fact that the first insulating layer adopts a taper (taper) film, the etching rate difference between the first insulating layer and the second insulating layer is too large, that is, the etching rate of the lower insulating layer is greater than that of the upper insulating layer, and the first insulating layer cannot adopt a taper (taper) film.
From the above, under the influence of the current design structure and etching process, the prism cross section is usually trapezoidal or arched, so that the triangular cross section shape cannot be realized, and the light scattering effect of the prism is greatly reduced.
Disclosure of Invention
The invention aims to provide a thin film transistor array substrate and a manufacturing method thereof, which can improve the light scattering capability of a prism structure and avoid the undercut condition.
The invention provides a manufacturing method of a thin film transistor array substrate, which comprises the following steps:
providing a substrate;
forming a plurality of TFTs arranged in an array on the substrate;
forming a first insulating layer covering a plurality of the TFTs, patterning the first insulating layer, forming a prism structure corresponding to an opening region of the substrate, the prism structure being used for scattering transmitted light, and forming a first contact hole penetrating through the first insulating layer corresponding to a non-opening region of the substrate to expose one conductive electrode of each TFT therebelow, wherein the first insulating layer comprises a first insulating film layer and a second insulating film layer covering the first insulating film layer, and an etching rate of the second insulating film layer is greater than that of the first insulating film layer;
forming a second insulating layer on the substrate, wherein the second insulating layer is positioned above the first insulating layer and is filled into the first contact hole;
forming a common electrode on the substrate, the common electrode being located over the first insulating layer;
forming a third insulating layer covering the second insulating layer and the common electrode, removing the third insulating layer and the second insulating layer at a position corresponding to the first contact hole, and forming a second contact hole penetrating through the second insulating layer to expose one conductive electrode of each of the underlying TFTs, wherein the second insulating layer covers a hole wall of the first insulating layer at a position corresponding to the first contact hole;
and forming a pixel electrode on the third insulating layer, wherein the pixel electrode is filled in the second contact hole and is electrically connected with one conductive electrode of the corresponding TFT.
The invention also provides a manufacturing method of the thin film transistor array substrate, which comprises the following steps:
providing a substrate;
forming a plurality of TFTs arranged in an array on the substrate;
forming a first insulating layer covering a plurality of the TFTs, patterning the first insulating layer, forming a prism structure corresponding to an opening region of the substrate, the prism structure being used for scattering transmitted light, and forming a first contact hole penetrating through the first insulating layer corresponding to a non-opening region of the substrate to expose one conductive electrode of each TFT therebelow, wherein the first insulating layer comprises a first insulating film layer and a second insulating film layer covering the first insulating film layer, and an etching rate of the second insulating film layer is greater than that of the first insulating film layer;
forming an etching barrier layer made of a conductive material on the first insulating layer, wherein the etching barrier layer is filled in the first contact hole and covers the hole wall of the first insulating layer at a position corresponding to the first contact hole, and the etching barrier layer is electrically connected with one conductive electrode of each TFT;
forming a second insulating layer on the substrate, wherein the second insulating layer is positioned above the etching barrier layer and is filled into the first contact hole;
forming a common electrode on the substrate, the common electrode being located over the first insulating layer;
forming a third insulating layer covering the second insulating layer and the common electrode, removing the third insulating layer and the second insulating layer at a position corresponding to the first contact hole, and forming a second contact hole penetrating through the second insulating layer to expose the etching barrier layer below, wherein the second insulating layer covers the hole wall of the first insulating layer at a position corresponding to the first contact hole;
and forming a pixel electrode on the third insulating layer, wherein the pixel electrode is filled in the second contact hole and is electrically connected with one corresponding conductive electrode of the TFT through the etching barrier layer.
Further, the TFT comprises a grid electrode formed on the substrate, a grid electrode insulating layer covering the grid electrode, a semiconductor layer located on the grid electrode insulating layer and a source electrode/drain electrode in contact with the semiconductor layer, and the prism structure is located above the grid electrode insulating layer and formed by etching the first insulating layer.
Further, the TFT comprises a grid electrode formed on the substrate, a grid electrode insulating layer covering the grid electrode, a semiconductor layer located on the grid electrode insulating layer and a source electrode/drain electrode in contact with the semiconductor layer, and the prism structure is formed by jointly etching the first insulating layer and the grid electrode insulating layer.
Further, the first insulating layer and the gate insulating layer are etched by the same photomask process to form the prism structure.
Further, the prism structure includes a plurality of prism columns that separate each other and are parallel, the prism column includes bottom surface, first prism face, second prism face and inclined plane, the bottom surface with the surface parallel arrangement of substrate, first prism face with the second prism face becomes the contained angle setting each other, the inclined plane connect in first prism face with between second prism face and the bottom surface.
Further, the manufacturing method of the thin film transistor array substrate further comprises the step of forming a flat layer covering the prism structure, the second insulating layer is formed on the flat layer, and the common electrode is formed on the second insulating layer.
Further, the second insulating layer is formed on the planarization layer, and the step of forming the common electrode on the second insulating layer includes: forming the entire second insulating layer on the planarization layer, forming a first transparent conductive film covering the entire second insulating layer, patterning the first transparent conductive film to form the common electrode, the common electrode being stacked on the second insulating layer.
Furthermore, the second contact hole is formed by etching the third insulating layer and the second insulating layer in the same photomask process.
The invention also provides a thin film transistor array substrate which is formed by the manufacturing method of the thin film transistor array substrate.
The invention provides a thin film transistor array substrate and a manufacturing method thereof, a prism structure and a first contact hole are formed on a first insulating layer, wherein the first insulating layer comprises a first insulating film layer and a second insulating film layer which covers the first insulating film layer and has a higher etching rate than the first insulating film layer, when the first insulating layer is etched, because the etching rates of the first insulating film layer at the lower part and the second insulating film layer at the upper part of the first insulating layer are different, the prism structure finally formed can present a good taper angle through the guidance of the second insulating film layer with a larger etching rate, the light scattering capability is improved, and the hole wall of the first contact hole is also covered with the second insulating layer, so that the condition of undercut caused by simultaneously etching the first insulating layer and the second insulating layer corresponding to the first contact hole is avoided, and the risk of wire breakage of the pixel electrode filled into the contact hole subsequently is avoided.
Drawings
Fig. 1 is a schematic view of a prism structure of a tft array substrate according to an embodiment;
fig. 2a to fig. 2g are schematic views illustrating a manufacturing process of a thin film transistor array substrate according to an embodiment;
FIG. 3 is a schematic view of a first insulating layer of a TFT array substrate according to one embodiment;
FIG. 4 is a schematic view of another prism structure of the TFT array substrate according to the first embodiment;
fig. 5 is a schematic structural diagram of a thin film transistor array substrate according to a second embodiment.
Detailed Description
The following detailed description of embodiments of the present invention is provided in connection with the accompanying drawings and examples. The following examples are intended to illustrate the invention but are not intended to limit the scope of the invention.
Example one
As shown in fig. 1, the method for manufacturing a thin film transistor array substrate provided in the embodiment of the present invention includes: a substrate 11 is provided, the substrate 11 comprising an open area that is light transmissive and a non-open area that is not light transmissive, the substrate 11 may be a glass substrate or a plastic substrate.
A plurality of TFTs 12 are formed on the substrate 11 in an array arrangement, and each TFT12 includes a gate electrode 121, a semiconductor layer 123, a source electrode 124, and a drain electrode 125. Specifically, a first metal layer (not shown) is formed on the substrate 11, and the first metal layer is patterned to form a scan line (not shown) and the gate electrode 121 of the TFT12, where the scan line is connected to the gate electrode 121; forming a gate insulating layer 122 on the substrate 11, the gate insulating layer 122 covering the scan lines and the gate electrode 121; depositing a semiconductor thin film on the gate insulating layer 122, patterning the semiconductor thin film to form a semiconductor layer 123, where the semiconductor layer 123 may be amorphous silicon (a-Si), polysilicon (p-Si), a metal oxide semiconductor (e.g., IGZO, ITZO), or the like; a second metal layer (not shown) is formed on the gate insulating layer 122, and the second metal layer is patterned to form a source electrode 124, a drain electrode 125, and a data line (not shown), wherein the source electrode 124 and the drain electrode 125 are in contact with the semiconductor layer 123.
As shown in fig. 2a and 3, a first insulating layer 13 covering the plurality of TFTs 12 is formed, the first insulating layer 13 includes a first insulating film layer 13a and a second insulating film layer 13b covering the first insulating film layer 13a, and the etching rate of the second insulating film layer 13b is greater than that of the first insulating film layer 13a, that is, the etching rate of the upper portion film layer of the first insulating layer 13 is greater than that of the lower portion, thereby forming the first insulating layer 13 having a trimming film quality. Preferably, the first insulating layer 13 is silicon nitride (SiNx), but the present invention is not limited thereto.
Specifically, when the first insulating layer 13 is formed, the film formation rate or the flow rate of the film formation gas is controlled so that the first insulating layer 13 having different upper and lower etching rates is realized, for example, the first insulating film layer 13a is formed in a high-speed film formation manner in a lower region of the first insulating layer 13, and the second insulating film layer 13b is formed in a low-speed film formation manner in an upper region.
As shown in fig. 2b, the first insulating layer 13 is patterned to form the prism structure 130 corresponding to the opening region of the substrate 11, but in this embodiment, the prism structure 130 is etched through the original insulating layer of the thin film transistor array substrate to form the prism structure 130 without separately manufacturing the prism structure 130. The prism structure 130 is used for refracting the transmitted light to form a scattering light path, and since the etching rates of the first insulating film layer 13a at the lower part of the first insulating layer 13 and the second insulating film layer 13b at the upper part of the first insulating layer 13 are different, the finally formed prism structure 130 can present a good taper angle through the guidance of the second insulating film layer 13b with a larger etching rate, and the light scattering capability is improved.
Optionally, the prism structure 130 is located above the gate insulating layer 122 and is formed by etching the first insulating layer 13, as shown in fig. 1; or the prism structure 130 is located above the substrate 11 and includes the gate insulating layer 122 and the first insulating layer 13 that are stacked sequentially from bottom to top after patterning, that is, the prism structure 130 is formed by etching the gate insulating layer 122 and the first insulating layer 13 together, as shown in fig. 4. The specific film layer of the prism structure 130 is selected according to actual conditions, for example, when the first insulating layer 13 is thicker and the prism structure 130 in a triangular prism shape can be etched, the prism structure 130 is formed by etching the first insulating layer 13, when the thickness of the first insulating layer 13 does not reach the thickness of the prism structure 130 etched into a triangular prism shape alone, after the first insulating layer 13 is etched, the gate insulating layer 122 needs to be continuously etched downwards to finally present an ideal prism structure 130 shape, at this time, the prism structure 130 is formed by etching the gate insulating layer 122 and the first insulating layer 13 together, and since the refractive indexes of the gate insulating layer 122 and the passivation layer are close, the prism structure 130 can be set together.
When the prism structure 130 is formed by etching the gate insulating layer 122 and the first insulating layer 13 together, the first insulating layer 13 and the gate insulating layer 122 may be etched to form the prism structure 130 through the same etching process, for example, a RIE mode is used to perform a single step etching, which avoids the prior art that the RIE and ECCP step etching are used to obtain the first insulating layer 13 and the gate insulating layer 122 with a better taper angle.
In the present embodiment, the prism structure 130 is formed on the first insulating layer 13 as an example.
Further, the prism structure 130 includes a plurality of prism columns 131 spaced apart from and parallel to each other, each prism column 131 includes a bottom surface 131a, a first prism surface 131b, a second prism surface 131c, and an inclined surface (not shown), the bottom surface 131a is disposed parallel to the surface of the substrate 11, the first prism surface 131b and the second prism surface 131c are disposed at an angle to each other, the inclined surface is connected between the first prism surface 131b, the second prism surface 131c, and the bottom surface 131a, and the first prism surface 131b and the second prism surface 131c are located in the length direction of the prism structure 130.
Specifically, the step of patterning the prism structure 130 includes: the first insulating layer 13 is exposed, developed and etched by using a mask, a plurality of grooves are etched on the first insulating layer 13, the non-patterned area between two adjacent grooves forms a prism column 131, the cross-sectional pattern of the grooves may be an inverted triangle or an inverted trapezoid, so that the cross-section of the prism column 131 is triangular (i.e., the prism column 131 is a triangular prism), and the width of the cross-section of the prism column 131 decreases from bottom to top. Preferably, the prism columns 131 are shaped like an isosceles triangle in cross section, and the base of the isosceles triangle is located at the lowermost position.
Further, a first contact hole 132 is formed through the first insulating layer 13 corresponding to the non-opening region of the substrate 11 to expose one conductive electrode (source electrode 124 or drain electrode 125) of each TFT12 therebelow, and the first contact hole 132 and the prism structure 130 are etched at the same time.
As shown in fig. 2c, a planarization layer 15 covering the prism structure 130 is formed, the trench on the surface of the first insulating layer 13 is planarized, and the planarization layer 15 is removed, for example, using a photosensitive resin, at a position corresponding to the first contact hole 132 to expose one of the conductive electrodes of the TFT12 therebelow. The light rays are refracted between the prism structure 130 of the first insulating layer 13 and the planarization layer 15, achieving the light diffusion effect. Preferably, the refractive index of the prism structure 130 is greater than the refractive index of the planarization layer 15.
As shown in fig. 2d, the entire second insulating layer 16 is formed on the planarization layer 15, and the second insulating layer 16 is filled in the first contact hole 132, and the second insulating layer 16 is not patterned.
The entire first transparent conductive film 170 is formed on the entire second insulating layer 16, as shown in fig. 2e, the common electrode 17 is formed by patterning the first transparent conductive film 170, the common electrode 17 and the second insulating layer 16 are overlapped up and down, and the method for manufacturing the common electrode 17 is referred to in the prior art and is not described herein again. Since wet etching of the first transparent conductive film 170 is required to form the common electrode 17, in order to protect the drain electrode 125 of the TFT12 from being corroded by the etching solution used to etch the common electrode 17, the second insulating layer 16 is formed to fill the first contact hole 132 and cover the drain electrode 125 under the first contact hole 132, and then the common electrode 17 is formed on the second insulating layer 16.
Further, as shown in fig. 2f, a third insulating layer 18 is formed to cover the second insulating layer 16 and the common electrode 17, and as shown in fig. 2g, the third insulating layer 18 and the second insulating layer 16 are etched away at positions corresponding to the first contact holes 132, and via holes penetrating the second insulating layer 16 and the third insulating layer 18 are formed to expose the drain electrodes 125 of the underlying TFTs 12. A via hole penetrating the second insulating layer 16 is defined as a second contact hole 161, and the drain electrode 125 is positioned under the second contact hole 161. Wherein the step of forming the first contact hole 132 and the second contact hole 161 is step etching; the step of forming the second contact hole 161 is to etch the third insulating layer 18 and the second insulating layer 16 in the same mask process, which saves the mask process.
It should be noted that the position of the second insulating layer 16 corresponding to the first contact hole 132 covers the hole wall of the first insulating layer 13, that is, the aperture of the second contact hole 161 of the second insulating layer 16 is smaller than the aperture of the first contact hole 132 of the first insulating layer 13, so that the first insulating layer 13 is not etched in the process of etching the second insulating layer 16 to form the second contact hole 161, and an undercut (undercut) condition caused by etching the first insulating layer 13 and the second insulating layer 16 simultaneously corresponding to the first contact hole 132 is avoided, so that the pixel electrode 19 subsequently filled into the contact hole avoids the risk of wire breakage, and the yield of the thin film transistor array substrate is improved. Preferably, the axes of the first contact hole 132 and the second contact hole 161 coincide.
A second transparent conductive film (not shown) is formed on the third insulating layer 18, the second transparent conductive film is patterned to form a pixel electrode 19, the pixel electrode 19 is filled in the second contact hole 161 and electrically connected to the corresponding drain electrode 125, and a manufacturing method of the pixel electrode 19 is please refer to the prior art, which is not repeated herein.
The embodiment of the invention also provides a thin film transistor array substrate which is formed by the manufacturing method of the thin film transistor array substrate.
Example two
The present embodiment provides a method for manufacturing a thin film transistor array substrate, which is partially the same as the first embodiment, and the same parts are not described herein again, except that:
referring to fig. 5, after the first insulating layer 13 is patterned, the etching stop layer 14 made of a conductive material is formed, the etching stop layer 14 fills the first contact hole 132 and covers the hole wall of the first insulating layer 13 at a position corresponding to the first contact hole 132, and the etching stop layer 14 is electrically connected to one conductive electrode of each TFT 12. The etch-barrier layer 14 is made of a metal or a transparent conductive metal oxide such as ITO (indium tin oxide), for example, the etch-barrier layer 14 may be aluminum, or may be ITO.
A planarization layer 15 is formed covering the etch stop layer 14 and the first insulating layer 13.
A second insulating layer 16 is formed on the planarization layer 15, the second insulating layer 16 is located above the etch stop layer 14, and the second insulating layer 16 fills the first contact hole 132, while the second insulating layer 16 is not patterned.
The entire first transparent conductive film 170 is formed on the entire second insulating layer 16, the common electrode 17 is formed by patterning the first transparent conductive film 170, the common electrode 17 and the second insulating layer 16 are overlapped up and down, and a method for manufacturing the common electrode 17 is please refer to the prior art, which is not described herein again.
Further, a third insulating layer 18 is formed to cover the second insulating layer 16 and the common electrode 17, the third insulating layer 18 and the second insulating layer 16 are etched and removed at a position corresponding to the first contact hole 132, and a via hole penetrating the second insulating layer 16 and the third insulating layer 18 is formed to expose the etching stopper layer 14 below. A via hole penetrating the second insulating layer 16 is defined as a second contact hole 161, and the etch stopper layer 14 is located under the second contact hole 161. Due to the blocking effect of the etching barrier layer 14, the first insulating layer 13 is not etched in the process of etching the second insulating layer 16 to form the second contact hole 161, so that the undercut of the first insulating layer 13 is avoided. In this embodiment, compared to the first embodiment, the aperture of the second contact hole 161 can be larger, and the etching process is simpler.
In the next process, for example, the pixel electrode 19 is formed on the third insulating layer 18, and the pixel electrode 19 fills the second contact hole 161 and is electrically connected to a corresponding one of the conductive electrodes of the TFT12 through the etching stop layer 14.
In summary, the thin film transistor array substrate and the method for fabricating the same according to the present invention form the prism structure 130 and the first contact hole 132 on the first insulating layer 13, wherein the first insulating layer 13 includes the first insulating film layer 13a and the second insulating film layer 13b covering the first insulating film layer 13a and having an etching rate greater than that of the first insulating film layer 13a, when the first insulating layer 13 is etched, the prism structure 130 finally formed may have a good taper angle due to the different etching rates of the first insulating film layer 13a at the lower portion of the first insulating layer 13 and the second insulating film layer 13b at the upper portion of the first insulating layer 13, thereby improving the light scattering capability, and the wall of the first contact hole 132 is covered with the second insulating layer 16, thereby avoiding the undercut caused by etching the first insulating layer 13 and the second insulating layer 16 simultaneously corresponding to the first contact hole 132, so that the pixel electrode 19 subsequently filled into the contact hole avoids the risk of wire breakage.
As used herein, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, including not only those elements listed, but also other elements not expressly listed.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (10)
1. A manufacturing method of a thin film transistor array substrate is characterized by comprising the following steps:
providing a substrate;
forming a plurality of TFTs arranged in an array on the substrate;
forming a first insulating layer covering a plurality of the TFTs, patterning the first insulating layer, forming a prism structure corresponding to an opening region of the substrate, the prism structure being used for scattering transmitted light, and forming a first contact hole penetrating through the first insulating layer corresponding to a non-opening region of the substrate to expose one conductive electrode of each TFT therebelow, wherein the first insulating layer comprises a first insulating film layer and a second insulating film layer covering the first insulating film layer, and an etching rate of the second insulating film layer is greater than that of the first insulating film layer;
forming a second insulating layer on the substrate, wherein the second insulating layer is positioned above the first insulating layer and is filled into the first contact hole;
forming a common electrode on the substrate, the common electrode being located over the first insulating layer;
forming a third insulating layer covering the second insulating layer and the common electrode, removing the third insulating layer and the second insulating layer at a position corresponding to the first contact hole, and forming a second contact hole penetrating through the second insulating layer to expose one conductive electrode of each of the underlying TFTs, wherein the second insulating layer covers a hole wall of the first insulating layer at a position corresponding to the first contact hole;
and forming a pixel electrode on the third insulating layer, wherein the pixel electrode is filled in the second contact hole and is electrically connected with one conductive electrode of the corresponding TFT.
2. A manufacturing method of a thin film transistor array substrate is characterized by comprising the following steps:
providing a substrate;
forming a plurality of TFTs arranged in an array on the substrate;
forming a first insulating layer covering a plurality of the TFTs, patterning the first insulating layer, forming a prism structure corresponding to an opening region of the substrate, the prism structure being used for scattering transmitted light, and forming a first contact hole penetrating through the first insulating layer corresponding to a non-opening region of the substrate to expose one conductive electrode of each TFT therebelow, wherein the first insulating layer comprises a first insulating film layer and a second insulating film layer covering the first insulating film layer, and an etching rate of the second insulating film layer is greater than that of the first insulating film layer;
forming an etching barrier layer made of a conductive material on the first insulating layer, wherein the etching barrier layer is filled in the first contact hole and covers the hole wall of the first insulating layer at a position corresponding to the first contact hole, and the etching barrier layer is electrically connected with one conductive electrode of each TFT;
forming a second insulating layer on the substrate, wherein the second insulating layer is positioned above the etching barrier layer and is filled into the first contact hole;
forming a common electrode on the substrate, the common electrode being located over the first insulating layer;
forming a third insulating layer covering the second insulating layer and the common electrode, removing the third insulating layer and the second insulating layer at a position corresponding to the first contact hole, and forming a second contact hole penetrating through the second insulating layer to expose the etching barrier layer below, wherein the second insulating layer covers the hole wall of the first insulating layer at a position corresponding to the first contact hole;
and forming a pixel electrode on the third insulating layer, wherein the pixel electrode is filled in the second contact hole and is electrically connected with one corresponding conductive electrode of the TFT through the etching barrier layer.
3. The method of manufacturing the thin film transistor array substrate of claim 1 or 2, wherein the TFT includes a gate electrode formed on the substrate, a gate insulating layer covering the gate electrode, a semiconductor layer on the gate insulating layer, and source/drain electrodes in contact with the semiconductor layer, and the prism structure is located over the gate insulating layer and etched from the first insulating layer.
4. The method of manufacturing the thin film transistor array substrate of claim 1 or 2, wherein the TFT includes a gate electrode formed on the substrate, a gate insulating layer covering the gate electrode, a semiconductor layer on the gate insulating layer, and source/drain electrodes in contact with the semiconductor layer, and the prism structure is formed by co-etching the first insulating layer and the gate insulating layer.
5. The method of claim 4, wherein the first insulating layer and the gate insulating layer are etched by a same masking process to form the prism structure.
6. The method of claim 1 or 2, wherein the prism structure comprises a plurality of prism columns spaced apart from and parallel to each other, the prism columns comprise a bottom surface, a first prism surface, a second prism surface, and an inclined surface, the bottom surface is parallel to the surface of the substrate, the first prism surface and the second prism surface are disposed at an angle to each other, and the inclined surface is connected between the first prism surface and the second prism surface and the bottom surface.
7. The method of fabricating a thin film transistor array substrate of claim 6, further comprising forming a planarization layer covering the prism structure, the second insulating layer being formed on the planarization layer, and the common electrode being formed on the second insulating layer.
8. The method of manufacturing the thin film transistor array substrate of claim 7, wherein the second insulating layer is formed on the planarization layer, and the step of forming the common electrode on the second insulating layer comprises: forming the entire second insulating layer on the planarization layer, forming a first transparent conductive film covering the entire second insulating layer, patterning the first transparent conductive film to form the common electrode, the common electrode being stacked on the second insulating layer.
9. The method of claim 8, wherein the second contact hole is formed by etching the third insulating layer and the second insulating layer in a same mask process.
10. A thin film transistor array substrate, wherein the thin film transistor array substrate is manufactured by the method for manufacturing a thin film transistor array substrate according to any one of claims 1 to 9.
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