CN112838052A - Thin film transistor array substrate and manufacturing method thereof - Google Patents
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- 239000002184 metal Substances 0.000 claims abstract description 120
- 238000002161 passivation Methods 0.000 claims abstract description 107
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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Abstract
The invention provides a thin film transistor array substrate and a manufacturing method thereof, wherein the manufacturing method comprises the following steps: providing a substrate base plate; forming a first insulating layer on the substrate base plate; forming a passivation layer film on the first insulating layer, and etching the passivation layer film to form a first passivation layer with a prism structure; forming a planarization layer covering the first passivation layer on the first insulating layer; forming a second insulating layer on the planarization layer; forming a first metal film on the second insulating layer, and etching the first metal film to manufacture a first metal layer, wherein the first metal layer comprises a grid and a scanning line; and etching the second insulating layer to expose part of the planarization layer. The invention can well solve the problems of serious bad bubbles, reduced opening rate, bad Moire and uneven display brightness.
Description
Technical Field
The invention relates to the technical field of display, in particular to a thin film transistor array substrate and a manufacturing method thereof.
Background
With the continuous development of technology, display technology has been rapidly developed, thin Film transistor tft (thin Film transistor) technology is developed from the original a-Si (amorphous silicon) thin Film transistor to the present LTPS (low temperature polysilicon) thin Film transistor, Oxide thin Film transistor, etc., and the thin Film transistor of the compound semiconductor active layer material represented by metal Oxide has the advantages of high mobility, simple manufacturing process, good large area uniformity, low manufacturing cost, etc.
In the prior art, in order to strive for a high competitive product with a wide and narrow viewing angle switching function (HVA) for a small-sized product, structure optimization and architecture adjustment are performed on the existing TFT.
Generally, a thin film transistor array substrate includes a display region and a peripheral region (the peripheral region is also referred to as a non-display region or a bonding region, i.e., a position where a TFT electrically connects with an external circuit). Fig. 1a and 1b are schematic cross-sectional views of a tft array substrate in the prior art, where fig. 1a is a schematic cross-sectional view of a display region of the tft array substrate in the prior art, and fig. 1b is a schematic cross-sectional view of a peripheral region of the tft array substrate in the prior art. As shown in fig. 1a, the structure of the display region includes a substrate 31, a metal layer 32, a first passivation layer 33, a planarization layer 34, a second passivation layer 35, a first gate insulating layer 36, a gate electrode 37, a second gate insulating layer 38, an active layer 39, a pixel electrode 40, a source electrode 41, a drain electrode 42, a third passivation layer 43, and a common electrode 44; as shown in fig. 1b, the structure of the peripheral region includes a substrate 31, a first passivation layer 33, a planarization layer 34, a second passivation layer 35, a common electrode wiring layer 45, a first gate insulating layer 36, a second gate insulating layer 38, a third passivation layer 43, and a common electrode 44, and the common electrode 44 is connected to the common electrode wiring layer 45 through a through hole etched above the common electrode wiring layer 45. The manufacturing sequence of each part of the thin film transistor array substrate is generally as follows: the substrate base plate 31 → the metal layer 32 → the first passivation layer 33 → the planarization layer 34 → the second passivation layer 35 → the common electrode wiring layer 45 → the first gate insulating layer 36 → the gate electrode 37 → the second gate insulating layer 38 → the active layer 39 → the pixel electrode 40 → the source and drain electrodes 41 and 42 → the third passivation layer 43 → the common electrode 44.
However, the above-mentioned thin film transistor array substrate may have serious bubble defect, reduced aperture ratio, poor moire, non-uniform display brightness, and poor contact of conductive particles during the manufacturing process, and the specific analysis is as follows:
1. the metal layer 32 (the material of the metal layer 32 is generally aluminum, copper, etc.) is provided to form a grating, and the metal layer 32 is made of a metal material, so that the metal layer can reduce the aperture ratio;
2. in fabricating the first passivation layer 33, it is necessary to perform prismatic etching on the first passivation layer 33 to obtain the first passivation layer 33 having a prism structure (the cross section of the prism may be a triangle or a trapezoid, etc.), so as to improve scattering of light, thereby increasing an aperture ratio and reducing brightness non-uniformity. However, when the first passivation layer 33 is etched in a prism manner, due to the non-uniformity of etching, the metal layer 32 may be damaged (the metal layer 32 has defects such as notches, etc., so that the metal layer 32 has irregular shape, and thus the metal layer 32 has abnormal reflection, diffraction, etc. to light), and even the substrate 31 may be damaged, and meanwhile, the prism gap is not clean (there are etching residues), so that the conditions such as poor moire, reduced aperture ratio, and non-uniform brightness (abnormal mura) are caused, and the condition of abnormal mura is not significantly improved by performing a pressure reduction process;
3. bubbles (bubbles) are generated in the planarization layer 34 during the process of fabricating the planarization layer 34, but since the process of releasing (i.e., de-bubbling) the bubbles is slow (i.e., it takes a certain time to completely de-bubble), the bubbles cannot be released after the planarization layer 34 is fabricated, i.e., the planarization layer 34 is covered with the second passivation layer 35 and other layer materials. Meanwhile, the processes of high-pressure baking and pressure defoaming are carried out under the condition of serious poor bubbles, which is not obviously improved;
4. in the bonding, the peripheral circuit and the common electrode wiring layer 45 are generally electrically connected by an ACF (anisotropic conductive film), and after the ACF is attached to the common electrode wiring layer 45, the conductive particle ends (metal balls) of the ACF are broken by pressing the ACF and conductive particles in the conductive particle ends of the ACF are released, so that the electrical connection between the ACF and the common electrode wiring layer 45 is realized. However, in the above process, since the common electrode wiring layer 45 is located above the second passivation layer 35 and the planarization layer 34, and the planarization layer 34 is made of a soft material, when the ACF is pressed, the conductive particle ends of the ACF are easily sunk into the planarization layer 34 and are not easily broken, so that the conductive particles cannot be released, and the conductive between the ACF and the common electrode wiring layer 45 is poor.
Disclosure of Invention
In order to solve the above technical problems, the present invention provides a thin film transistor array substrate and a method for fabricating the same, which can solve the problems of serious bubble defect, reduced aperture ratio, poor moire, non-uniform display brightness, and poor contact of conductive particles.
The invention provides a manufacturing method of a thin film transistor array substrate, which comprises the following steps:
providing a substrate base plate;
forming a first insulating layer on the substrate base plate;
forming a passivation layer film on the first insulating layer, and etching the passivation layer film to form a first passivation layer with a prism structure;
forming a planarization layer covering the first passivation layer on the first insulating layer;
forming a second insulating layer on the planarization layer;
forming a first metal film on the second insulating layer;
coating a photoresist on the first metal film, exposing and developing the photoresist, etching the first metal film by using the remained photoresist as a mask to manufacture a first metal layer, and continuously covering the first metal layer with the photoresist;
continuously etching the second insulating layer by using the photoresist as a mask to remove the second insulating layer which is not covered by the photoresist so as to expose the planarization layer which is not covered by the photoresist;
and removing the photoresist to expose the first metal layer, wherein the first metal layer comprises a grid and a scanning line.
Further, the manufacturing method further comprises the following steps:
forming a gate insulating layer covering the gate electrode and the scan line on the exposed planarization layer;
forming an active layer film on the gate insulating layer, and etching the active layer film to manufacture an active layer;
forming a first oxide conducting layer on the grid insulating layer, and etching the first oxide conducting layer to manufacture a pixel electrode;
and forming a second metal film on the gate insulating layer, etching the second metal film to manufacture a second metal layer, wherein the second metal layer comprises a source electrode, a drain electrode and a data line, the source electrode and the drain electrode are respectively connected with the active layer, the source electrode is connected with the data line, and the drain electrode is connected with the pixel electrode.
Further, the manufacturing method further comprises the following steps:
forming a second passivation layer on the gate insulating layer to cover the second metal layer, the pixel electrode, and the active layer;
and forming a second oxide conducting layer on the second passivation layer, and etching the second oxide conducting layer to manufacture a common electrode.
Further, the manufacturing method further comprises the following steps:
before forming the first insulating layer on the substrate base plate, forming a peripheral circuit metal film on the substrate base plate, and etching the peripheral circuit metal film to manufacture a peripheral circuit metal layer, wherein the peripheral circuit metal layer comprises a common electrode wiring layer;
after the second passivation layer is formed on the gate insulating layer, a through hole is formed in an upper region of the common electrode wiring layer through etching, the second oxide conductive layer is formed on the second passivation layer, the second oxide conductive layer is etched to manufacture the common electrode, and the common electrode is filled in the through hole and connected with the common electrode wiring layer.
Furthermore, the first insulating layer is made of silicon oxynitride or silicon oxide, and the first passivation layer is made of silicon nitride.
The present invention also provides a thin film transistor array substrate, comprising:
a substrate base plate;
a first insulating layer formed on the base substrate;
a first passivation layer formed on the first insulating layer, the first passivation layer having a prism structure;
a planarization layer formed on the first insulating layer and covering the first passivation layer;
a second insulating layer formed on the planarization layer;
and a first metal layer formed on the second insulating layer, wherein the first metal layer includes a gate electrode and a scan line, and the second insulating layer and the first metal layer have the same patterned structure and are stacked one on another.
Further, the thin film transistor array substrate further includes:
a gate insulating layer formed on the planarization layer and covering the gate electrode and the scan line;
an active layer formed on the gate insulating layer;
a pixel electrode formed on the gate insulating layer;
a second metal layer formed on the gate insulating layer, wherein the second metal layer includes a source electrode, a drain electrode, and a data line, the source electrode and the drain electrode are respectively connected to the active layer, the source electrode is connected to the data line, and the drain electrode is connected to the pixel electrode;
a second passivation layer formed on the gate insulating layer, wherein the second passivation layer covers the source electrode, the drain electrode, the data line, the pixel electrode, and the active layer.
Further, the thin film transistor array substrate further includes:
a common electrode wiring layer formed on the substrate, wherein a through hole is formed in an upper region of the common electrode wiring layer, and penetrates through the gate insulating layer and the second passivation layer;
and the common electrode is formed on the second passivation layer, is filled in the through hole and is connected with the common electrode wiring layer.
Furthermore, the first insulating layer is made of silicon oxynitride or silicon oxide, and the first passivation layer is made of silicon nitride.
Further, the thickness of the first insulating layer is
The thickness of the first passivation layer is
According to the manufacturing method of the thin film transistor array substrate, the metal layer of the original scheme is replaced by the first insulating layer on the whole surface, the etching rate of the first passivation layer is larger than that of the first insulating layer (the first insulating layer is generally made of materials such as silicon oxynitride or silicon oxide with a small etching rate, and the first passivation layer is generally made of silicon nitride with a larger etching rate than that of the first insulating layer), so that when the first passivation layer is formed by prism etching of the passivation layer film, the etching amount of the first insulating layer is small, the prism gap of the first passivation layer is smooth and clean, the uniformity of the etched prism is better, the condition of uneven brightness (abnormal mura) is reduced, no moire is generated, and the first passivation layer is not required to be damaged on the substrate and the first insulating layer during long-time prism etching. Meanwhile, the light transmittance of the first insulating layer is better than that of the metal layer, so that the aperture opening ratio can be improved, and the first insulating layer is used as the substrate, so that chromatic aberration cannot be generated.
Meanwhile, when the second insulating layer is formed on the planarization layer, secondary gas can be released from the planarization layer by using a high-temperature atmosphere (formed by depositing the second insulating layer at a high temperature) during the formation of the second insulating layer, so that the occurrence of poor bubbles is reduced; meanwhile, the second insulating layer is etched to expose a large-area planarization layer, so that third-time gas release can be performed on the planarization layer, and the occurrence of poor bubbles is further reduced. After the first metal layer (including the gate and the scan line) is manufactured, the remaining photoresist is continuously covered on the first metal layer (including the gate and the scan line), so that damage to the first metal layer (including the gate and the scan line) during etching of the second insulating layer can be avoided, and undercut (undercut) damage to the first metal layer (including the gate and the scan line) can be avoided.
Drawings
Fig. 1a is a schematic cross-sectional view of a display region of a tft array substrate in the prior art.
Fig. 1b is a schematic cross-sectional view of a peripheral region of a tft array substrate in the prior art.
Fig. 2a is a schematic cross-sectional view of a display region of a thin film transistor array substrate according to an embodiment of the invention.
Fig. 2b is a schematic cross-sectional view of the periphery region of the tft array substrate according to an embodiment of the present invention.
Fig. 3 to 17b are schematic views illustrating a manufacturing process of the thin film transistor array substrate according to the embodiment of the invention.
Detailed Description
The following detailed description of embodiments of the present invention is provided in connection with the accompanying drawings and examples. The following examples are intended to illustrate the invention but are not intended to limit the scope of the invention.
The terms "first," "second," "third," "fourth," and the like in the description and in the claims, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order.
The terms of orientation, up, down, left, right, front, back, top, bottom, and the like (if any) referred to in the specification and claims of the present invention are defined by the positions of structures in the drawings and the positions of the structures relative to each other, only for the sake of clarity and convenience in describing the technical solutions. It is to be understood that the use of the directional terms should not be taken to limit the scope of the claims.
As shown in fig. 2a and 2b, an embodiment of the present invention provides a Thin Film Transistor (TFT) array substrate, which includes a display region (i.e., a region where a TFT is located) and a peripheral region (the peripheral region is also referred to as a non-display region or a bonding region, i.e., a region where the TFT is electrically connected to an external circuit). Fig. 2a is a schematic cross-sectional view of a display region of the thin film transistor array substrate, and fig. 2b is a schematic cross-sectional view of a peripheral region of the thin film transistor array substrate.
As shown in fig. 2a, the structure of the display region of the thin film transistor array substrate includes:
a substrate base plate 11;
a first insulating layer 13 formed on the base substrate 11;
a first passivation layer 14 formed on the first insulating layer 13, the first passivation layer 14 having a prism structure (a cross section of the prism 141 may be triangular or trapezoidal), an etching rate of the first passivation layer 14 being greater than an etching rate of the first insulating layer 13;
a planarization layer 15 formed on the first insulating layer 13 and covering the first passivation layer 14;
a second insulating layer 16 formed on the planarization layer 15;
a first metal layer formed on the second insulating layer 16, wherein the first metal layer includes a gate electrode 17 and a scan line (not shown), and the second insulating layer 16 and the first metal layer have the same patterned structure and are stacked one on another;
a gate insulating layer 18 formed on the planarization layer 15 while covering the second insulating layer 16, the gate electrode 17, and the scan line;
an active layer 19 formed on the gate insulating layer 18 and the active layer 19 is correspondingly located above the gate electrode 17;
a pixel electrode 20 formed on the gate insulating layer 18;
a second metal layer formed on the gate insulating layer 18, wherein the second metal layer includes a source electrode 211, a drain electrode 212, and a data line (not shown), the source electrode 211 and the drain electrode 212 are respectively connected to the active layer 19, the source electrode 211 is connected to the data line, and the drain electrode 212 is connected to the pixel electrode 20;
a second passivation layer 22 formed on the gate insulating layer 18, and the second passivation layer 22 simultaneously covers the source electrode 211, the drain electrode 212, the data line, the pixel electrode 20, and the active layer 19;
and a common electrode 23 formed on the second passivation layer 22.
As shown in fig. 2b, the structure of the peripheral region of the thin film transistor array substrate includes:
a substrate base plate 11;
a common electrode wiring layer 12 formed on the substrate 11;
a gate insulating layer 18 formed on the base substrate 11 and covering the common electrode wiring layer 12;
a second passivation layer 22 formed on the gate insulating layer 18;
a common electrode 23 formed on the second passivation layer 22, a through hole 181 formed by etching in an upper region of the common electrode wiring layer 12, the through hole 181 penetrating the gate insulating layer 18 and the second passivation layer 22, the common electrode 23 filling the through hole 181 and connected to the common electrode wiring layer 12, and the common electrode 23 in the peripheral region and the common electrode 23 in the display region being of an integral structure.
Further, the material of the first insulating layer 13 is silicon oxynitride or silicon oxide, and the material of the first passivation layer 14 is silicon nitride.
Further, the thickness of the first insulating layer 13 is
The thickness of the first passivation layer 14 is
Specifically, the manufacturing method of the thin film transistor array substrate comprises the following steps:
providing a substrate base plate 11;
forming a first insulating layer 13 on the base substrate 11;
forming a passivation layer film 140 on the first insulating layer 13, and etching the passivation layer film 140 to form a first passivation layer 14 having a prism structure, wherein an etching rate of the first passivation layer 14 is greater than that of the first insulating layer 13;
forming a planarization layer 15 covering the first passivation layer 14 on the first insulating layer 13;
forming a second insulating layer 16 on the planarization layer 15;
forming a first metal film on the second insulating layer 16;
coating a photoresist 24 on the first metal film, exposing and developing the photoresist 24, etching the first metal film by using the remained photoresist 24 as a mask to manufacture a first metal layer, and continuously covering the photoresist 24 on the first metal layer;
continuing to etch the second insulating layer 16 by using the photoresist 24 as a mask (the remaining photoresist 24 plays a role of protecting the first metal layer when etching the second insulating layer 16) to remove the second insulating layer 16 not covered by the photoresist 24, so as to expose the planarization layer 15 not covered by the photoresist 24;
the photoresist 24 is removed to expose the first metal layer, wherein the first metal layer includes the gate 17 and the scan line.
Further, the manufacturing method further comprises the following steps:
forming a gate insulating layer 18 covering the gate electrode 17, the second insulating layer 16, and the scan line on the exposed planarization layer 15;
forming an active layer thin film on the gate insulating layer 18, and etching the active layer thin film to form an active layer 19;
forming a first oxide conductive layer over the gate insulating layer 18, and etching the first oxide conductive layer to form a pixel electrode 20;
a second metal film is formed on the gate insulating layer 18, and the second metal film is etched to form a second metal layer, where the second metal layer includes a source 211, a drain 212, and a data line, the source 211 and the drain 212 are respectively connected to the active layer 19, the source 211 is connected to the data line, and the drain 212 is connected to the pixel electrode 20.
Further, the manufacturing method further comprises the following steps:
forming a second passivation layer 22 on the gate insulating layer 18 to cover the second metal layer, the pixel electrode 20, and the active layer 19;
a second oxide conductive layer is formed on the second passivation layer 22, and the second oxide conductive layer is etched to form a common electrode 23.
Further, the manufacturing method further comprises the following steps:
before forming the first insulating layer 13 on the substrate 11, forming a peripheral circuit metal film on the substrate 11, and etching the peripheral circuit metal film to form a peripheral circuit metal layer, wherein the peripheral circuit metal layer includes a common electrode wiring layer 12;
after forming the second passivation layer 22 on the gate insulating layer 18, a through hole 181 is formed by etching in an upper region of the common electrode wiring layer 12, a second oxide conductive layer is formed on the second passivation layer 22, and the second oxide conductive layer is etched to form the common electrode 23, wherein the common electrode 23 is filled in the through hole 181 and connected to the common electrode wiring layer 12.
The following describes the manufacturing method of the thin film transistor array substrate in detail:
1. as shown in fig. 3, fig. 3 is a schematic cross-sectional view of the peripheral region of the thin film transistor array substrate. Forming a peripheral circuit metal film on a substrate 11, and performing mask etching on the peripheral circuit metal film to form a peripheral circuit metal layer, wherein the peripheral circuit metal layer comprises a common electrode wiring layer 12 and other peripheral circuit patterns; the common electrode wiring layer 12 is subsequently connected to the common electrode 23, and the common electrode 23 is connected to an external circuit through the common electrode wiring layer 12. The common electrode wiring layer 12 may be made of a metal or alloy such as Cr, W, Ti, Ta, Mo, Al, or Cu, or may be a composite thin film composed of a plurality of metal thin films.
2. As shown in fig. 4a and 4b, fig. 4a is a schematic cross-sectional view of the display region of the thin film transistor array substrate, and fig. 4b is a schematic cross-sectional view of the peripheral region of the thin film transistor array substrate. A first insulating layer 13 covering the common electrode wiring layer 12 is formed on the base substrate 11. The material of the first insulating layer 13 may be silicon oxynitride or silicon oxide.
Specifically, referring to fig. 1 and fig. 2, the first insulating layer 13 is used to replace the metal layer 32 in the prior art, and the transmittance of the first insulating layer 13 is better than that of the metal layer 32, so that the aperture ratio can be increased.
3. As shown in fig. 5a to 6b, fig. 5a and 6a are schematic cross-sectional views of a display region of the thin film transistor array substrate, and fig. 5b and 6b are schematic cross-sectional views of a peripheral region of the thin film transistor array substrate. A passivation layer thin film 140 is formed on the first insulating layer 13, the passivation layer thin film 140 is etched to fabricate a first passivation layer 14 having a prism structure, and the passivation layer thin film 140 of the vicinity region above the common electrode wiring layer 12 is etched away. The first passivation layer 14 is made of silicon nitride.
Specifically, after the passivation layer film 140 is formed on the first insulating layer 13, the first passivation layer 14 is formed by coating a photoresist, exposing, developing, and dry etching, and the photoresist is removed after the etching is completed, where the first passivation layer 14 has a prism structure (the cross section of the prism 141 may be a triangle or a trapezoid, etc.), and the first insulating layer 13 and the first passivation layer 14 may be completed at one time by the same machine. In this embodiment, the first passivation layer 14 is made of a silicon nitride material, and the first insulating layer 13 is made of a silicon oxynitride or silicon oxide material with a smaller etching rate, so as to reduce damage to the first insulating layer 13 when the first passivation layer 14 is formed by etching. Meanwhile, since the etching rate of the first insulating layer 13 is much lower than that of the first passivation layer 14, there is no need to worry about the first insulating layer 13 being etched and remained in the gap between the prisms 141 when the first passivation layer 14 is etched to form the prisms 141 (referring to fig. 1a, in the prior art, when the planarization layer 34 is formed by etching, the metal layer 32 may be damaged, so that the prism gap is not clean, and the moire pattern and the brightness are not uniform), and a higher and better prism 141 can be obtained, and the gap between the prisms 141 is clean and flat, and the defects of serious brightness non-uniformity (mura) and moire pattern are not caused.
4. As shown in fig. 7a and 7b, fig. 7a is a schematic cross-sectional view of the display region of the thin film transistor array substrate, and fig. 7b is a schematic cross-sectional view of the peripheral region of the thin film transistor array substrate. A planarization layer 15 covering the first passivation layer 14 is formed on the first insulation layer 13, and the planarization layer 15 of the upper vicinity region of the common electrode wiring layer 12 is removed by exposure and development, and the first insulation layer 13 of the upper vicinity region of the common electrode wiring layer 12 is exposed, and the planarization layer 15 in the display region remains and covers the prisms 141 of the first passivation layer 14.
Specifically, the planarization layer 15 is typically made of an organic material like photoresist, and can be removed by exposure and development. Since the planarization layer 15 in the peripheral region is not needed, the planarization layer 15 in the peripheral region is removed in advance in this step to facilitate the subsequent fabrication of the via 181 (see fig. 2b for the structure and location of the via 181). Meanwhile, when the planarization layer 15 is manufactured, bubbles are generated in the planarization layer 15, which causes a defect of serious bubble defect in the thin film transistor array substrate, so that the bubbles in the planarization layer 15 can be easily removed through a baking process after the planarization layer 15 is manufactured.
5. As shown in fig. 8a and 8b, fig. 8a is a schematic cross-sectional view of the display region of the tft array substrate, and fig. 8b is a schematic cross-sectional view of the peripheral region of the tft array substrate. A second insulating layer 16 is formed on the planarization layer 15 and on the first insulating layer 13 in the vicinity above the common electrode wiring layer 12.
Specifically, in this step, the material of the second insulating layer 16 is silicon oxynitride, silicon oxide or silicon nitride, so that the second insulating layer 16 is formed by a high temperature process, and the bubbles in the planarization layer 15 can be removed again by using the high temperature atmosphere of the process.
6. As shown in fig. 9a and 9b, fig. 9a is a schematic cross-sectional view of the display region of the thin film transistor array substrate, and fig. 9b is a schematic cross-sectional view of the peripheral region of the thin film transistor array substrate. A first metal film is formed on the second insulating layer 16, and a mask etching process is performed on the first metal film to form a first metal layer, which includes the gate electrode 17 and the scan lines (not shown).
The method comprises the following steps: a first metal film is formed on the second insulating layer 16, a photoresist 24 is coated on the first metal film, the photoresist 24 is exposed and developed by using a mask (not shown), and then the first metal film is etched by wet etching using the remaining photoresist 24 as a mask to form a first metal layer on the second insulating layer 16, and the remaining photoresist 24 is continuously covered on the first metal layer.
7. As shown in fig. 10a to 11b, fig. 10a and 11a are schematic cross-sectional views of a display region of the thin film transistor array substrate, and fig. 10b and 11b are schematic cross-sectional views of a peripheral region of the thin film transistor array substrate. As shown in fig. 10a and 10b, the second insulating layer 16 is continuously dry etched using the remaining photoresist 24 as a mask, the second insulating layer 16, which is not blocked by the photoresist 24 in the display region and the peripheral region, is removed, so that the planarization layer 15 in the display region is exposed in a large area, and the etching is continuously performed after the second insulating layer 16 in the peripheral region is removed until the first insulating layer 13 below the second insulating layer 16 in the peripheral region is also removed, that is, the first insulating layer 13 and the second insulating layer 16 in the peripheral region in the vicinity of the upper portion of the common electrode wiring layer 12 are both etched away, so that the substrate 11 in the vicinity of the common electrode wiring layer 12 is exposed. Since the material of the first insulating layer 13 is silicon oxynitride or silicon oxide, and the material of the second insulating layer 16 is silicon nitride, the first insulating layer 13 and the second insulating layer 16 are not easily etched, so the first insulating layer 13 and the second insulating layer 16 in the vicinity area above the common electrode wiring layer 12 are etched in advance, so as to facilitate the subsequent fabrication of the through hole 181 (see fig. 2b for the structure and position of the through hole 181). After the etching is completed, the remaining photoresist 24 is removed to expose the first metal layer (including the gate electrode 17 and the scan line), as shown in fig. 11 a.
Specifically, after the first metal layer (including the gate electrode 17 and the scan line) is fabricated, since the photoresist 24 is left to continuously cover the first metal layer (including the gate electrode 17 and the scan line), damage to the first metal layer (including the gate electrode 17 and the scan line) during etching of the second insulating layer 16 and the first insulating layer 13 can be avoided, and undercut (undercut) damage to the first metal layer (including the gate electrode 17 and the scan line) can be avoided. Meanwhile, in this step, since the second insulating layer 16 is etched away, the large-area planarization layer 15 is exposed, so that the bubbles in the planarization layer 15 can be released for the third time and fully released.
8. As shown in fig. 12a and 12b, fig. 12a is a schematic cross-sectional view of the display region of the thin film transistor array substrate, and fig. 12b is a schematic cross-sectional view of the peripheral region of the thin film transistor array substrate. A gate insulating layer 18 covering the gate electrode 17, the scanning lines, the common electrode wiring layer 12, and the second insulating layer 16 is formed on the planarizing layer 15 and on the substrate 11 in the vicinity of the common electrode wiring layer 12. Meanwhile, when the gate insulating layer 18 is manufactured, the bubbles in the planarization layer 15 can be removed for the fourth time by using the high-temperature atmosphere of the manufacturing process, so that the bubbles in the planarization layer 15 are fully released, and the generation of bubbles (bubbles) after the box formation is effectively avoided. The gate insulating layer 18 is made of silicon nitride.
9. As shown in fig. 13a and 13b, fig. 13a is a schematic cross-sectional view of the display region of the thin film transistor array substrate, and fig. 13b is a schematic cross-sectional view of the peripheral region of the thin film transistor array substrate. An active layer film is formed on the gate insulating layer 18, and the active layer film is subjected to mask etching to produce an active layer 19.
Specifically, the active layer may be made of amorphous silicon (a-si), polysilicon (p-si), metal oxide semiconductor (e.g., IGZO, ITZO), or the like.
10. As shown in fig. 14a and 14b, fig. 14a is a schematic cross-sectional view of the display region of the thin film transistor array substrate, and fig. 14b is a schematic cross-sectional view of the peripheral region of the thin film transistor array substrate. A first oxide conductive layer is formed over the gate insulating layer 18, and the first oxide conductive layer is subjected to mask etching to fabricate a pixel electrode 20.
Specifically, the pixel electrode 20 may be made of a transparent conductive material, such as Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), or aluminum zinc oxide (alzno).
11. As shown in fig. 15a and 15b, fig. 15a is a schematic cross-sectional view of the display region of the thin film transistor array substrate, and fig. 15b is a schematic cross-sectional view of the peripheral region of the thin film transistor array substrate. A second metal film is formed on the gate insulating layer 18, and a mask etching process is performed on the second metal film to form a second metal layer, where the second metal layer includes a source 211, a drain 212, and a data line (not shown), the source 211 and the drain 212 are respectively connected to the active layer 19, the source 211 is connected to the data line, and the drain 212 is connected to the pixel electrode 20.
Specifically, the gate electrode 17, the source electrode 211, and the drain electrode 212 may be made of a metal or an alloy such as Cr, W, Ti, Ta, Mo, Al, or Cu, or may be a composite film formed by a plurality of metal films.
12. As shown in fig. 16a and 16b, fig. 16a is a schematic cross-sectional view of the display region of the thin film transistor array substrate, and fig. 16b is a schematic cross-sectional view of the peripheral region of the thin film transistor array substrate. A second passivation layer 22 covering the second metal layer, the pixel electrode 20 and the active layer 19 is formed on the gate insulating layer 18, and then the gate insulating layer 18 and the second passivation layer 22 in the vicinity region above the common electrode wiring layer 12 are simultaneously subjected to mask etching, so that a through hole 181 penetrating the gate insulating layer 18 and the second passivation layer 22 is formed in the vicinity region above the common electrode wiring layer 12. The material of the second passivation layer 22 may be silicon oxynitride, silicon oxide or silicon nitride.
13. As shown in fig. 17a and 17b, fig. 17a is a schematic cross-sectional view of the display region of the thin film transistor array substrate, and fig. 17b is a schematic cross-sectional view of the peripheral region of the thin film transistor array substrate. A second oxide conductive layer is formed on the second passivation layer 22, the second oxide conductive layer is subjected to mask etching to form a common electrode 23, and the common electrode 23 is filled in the through hole 181 in the peripheral region and connected to the common electrode wiring layer 12. The common electrode 23 may be made of a transparent conductive material, such as Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), or aluminum zinc oxide.
Specifically, since the common electrode wiring layer 12 is provided on the substrate 11, and the substrate 11 is generally made of a hard material such as a glass substrate or a plastic substrate, when electrical connection bonding is performed between the peripheral circuit and the common electrode wiring layer 12 by an ACF (anisotropic conductive film), after the ACF is bonded to the common electrode wiring layer 12, the conductive particle ends of the ACF are broken by pressing the ACF and the conductive particles in the conductive particle ends of the ACF are released (since the substrate 1 is made of a hard base, the conductive particle ends of the ACF are easily broken by pressing the ACF), thereby achieving electrical connection between the ACF and the common electrode wiring layer 45 and effectively solving the problem of poor contact of the conductive particles during bonding. Referring to fig. 1b, in the prior art, since the common electrode wiring layer 45 is located above the second passivation layer 35 and the planarization layer 34, and the planarization layer 34 is made of a soft material, when the ACF is pressed, the conductive particle ends of the ACF are easily sunk into the planarization layer 34 and are not easily broken, so that the conductive particles cannot be released, and the ACF and the common electrode wiring layer 45 are poor in conductivity.
The thin film transistor array substrate and the manufacturing method thereof provided by the embodiment of the invention have the advantages that:
1. the metal layer 32 of the original scheme is replaced by the whole first insulating layer 13, the first insulating layer 13 is made of silicon oxynitride or silicon oxide with a small etching rate, so when the first passivation layer 14 is formed by prism etching of the passivation layer film 140, the etching amount of the first insulating layer 13 is little or even negligible, the gap of the prism 141 of the first passivation layer 14 is smooth and clean, the uniformity of the prism 141 after etching is better, the condition of uneven brightness (abnormal mura) is reduced, no moire is generated, and the first passivation layer 14 does not need to be worried about damaging the substrate 11 and the first insulating layer 13 when long-time prism etching is carried out.
2. Since the first insulating layer 13 has better light transmittance than the metal layer 32, the aperture ratio can be increased, and no color difference is generated when the first insulating layer 13 is used as a substrate.
3. In the step 4, after the planarization layer 15 is manufactured, the air bubbles in the planarization layer 15 are favorably removed through baking; in the step 5, the second insulating layer 16 is formed by a high temperature process, and the bubbles in the planarization layer 15 can be removed again by using the high temperature atmosphere of the process; in step 7, after the second insulating layer 16 is etched, the large-area planarization layer 15 is in an exposed state, so that the bubbles in the planarization layer 15 can be removed for the third time and released sufficiently; in step 8, the bubbles in the planarization layer 15 can be removed for the fourth time by using the high temperature atmosphere of the process during the fabrication of the gate insulating layer 18, so that the bubbles in the planarization layer 15 can be fully released. By removing the bubbles in the planarization layer 15 for many times, bubbles (bubbles) are effectively prevented from being generated after the box is formed.
4. In the above steps 6 and 7, after the first metal layer (including the gate electrode 17 and the scan line) is manufactured, the remaining photoresist 24 is continuously covered on the first metal layer (including the gate electrode 17 and the scan line), so that damage to the first metal layer (including the gate electrode 17 and the scan line) during etching the second insulating layer 16 and the first insulating layer 13 can be avoided, and damage to an undercut (undercut) of the first metal layer (including the gate electrode 17 and the scan line) can be avoided.
5. Since the common electrode wiring layer 12 is provided on the substrate 11, and the substrate 11 is generally made of a hard material such as a glass substrate or a plastic substrate, when electrical connection bonding is performed between the peripheral circuit and the common electrode wiring layer 12 by an ACF (anisotropic conductive film), after the ACF is bonded to the common electrode wiring layer 12, the conductive particle ends of the ACF are broken by pressing the ACF and the conductive particles in the conductive particle ends of the ACF are released (since the substrate 1 is a hard substrate, the conductive particle ends of the ACF are easily broken by pressing the ACF), thereby achieving electrical connection between the ACF and the common electrode wiring layer 45 and effectively solving the problem of poor contact of the conductive particles during bonding.
6. Compared with the background technical scheme, the embodiment of the invention not only reduces the layer number of the thin film transistor array substrate, thereby reducing the thickness of the thin film transistor array substrate, but also saves the production cost, reduces the process flow (including the flow of coating photoresist twice, exposing and developing, dry etching once, wet etching once, removing the photoresist once and the like), and can shorten the production period of about four days.
7. The manufacturing method of the thin film transistor array substrate provided by the embodiment of the invention can be used for producing an excellent TFT array substrate with a wide and narrow viewing angle switching function (HVA type).
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (10)
1. A manufacturing method of a thin film transistor array substrate is characterized by comprising the following steps:
providing a substrate base plate (11);
forming a first insulating layer (13) on the base substrate (11);
forming a passivation layer thin film (140) on the first insulating layer (13), and etching the passivation layer thin film (140) to form a first passivation layer (14) with a prism structure;
forming a planarization layer (15) on the first insulating layer (13) covering the first passivation layer (14);
forming a second insulating layer (16) on the planarization layer (15);
forming a first metal thin film on the second insulating layer (16);
coating a photoresist (24) on the first metal film, exposing and developing the photoresist (24), etching the first metal film by using the remained photoresist (24) as a mask to manufacture a first metal layer, and continuously covering the photoresist (24) on the first metal layer;
continuing to etch the second insulating layer (16) by using the photoresist (24) as a mask to remove the second insulating layer (16) not covered by the photoresist (24) and expose the planarization layer (15) not covered by the photoresist (24);
and removing the photoresist (24) to expose the first metal layer, wherein the first metal layer comprises a grid electrode (17) and a scanning line.
2. The method of manufacturing a thin film transistor array substrate of claim 1, further comprising:
forming a gate insulating layer (18) covering the gate electrode (17) and the scanning line on the exposed planarization layer (15);
forming an active layer film on the gate insulating layer (18), and etching the active layer film to manufacture an active layer (19);
forming a first oxide conductive layer on the gate insulating layer (18), and etching the first oxide conductive layer to form a pixel electrode (20);
and forming a second metal film on the gate insulating layer (18), etching the second metal film to manufacture a second metal layer, wherein the second metal layer comprises a source electrode (211), a drain electrode (212) and a data line, the source electrode (211) and the drain electrode (212) are respectively connected with the active layer (19), the source electrode (211) is connected with the data line, and the drain electrode (212) is connected with the pixel electrode (20).
3. The method of manufacturing a thin film transistor array substrate of claim 2, further comprising:
forming a second passivation layer (22) on the gate insulating layer (18) covering the second metal layer, the pixel electrode (20) and the active layer (19);
and forming a second oxide conducting layer on the second passivation layer (22), and etching the second oxide conducting layer to manufacture a common electrode (23).
4. The method of manufacturing a thin film transistor array substrate of claim 3, further comprising:
before forming the first insulating layer (13) on the substrate (11), forming a peripheral circuit metal film on the substrate (11), and etching the peripheral circuit metal film to manufacture a peripheral circuit metal layer, wherein the peripheral circuit metal layer comprises a common electrode wiring layer (12);
after the second passivation layer (22) is formed on the gate insulating layer (18), a through hole (181) is formed in the upper region of the common electrode wiring layer (12) through etching, then the second oxide conductive layer is formed on the second passivation layer (22), then the second oxide conductive layer is etched to manufacture the common electrode (23), and the common electrode (23) is filled in the through hole (181) and connected with the common electrode wiring layer (12).
5. The method of fabricating the thin film transistor array substrate of any one of claims 1 to 4, wherein the first insulating layer (13) is made of silicon oxynitride or silicon oxide, and the first passivation layer (14) is made of silicon nitride.
6. A thin film transistor array substrate, comprising:
a base substrate (11);
a first insulating layer (13) formed on the base substrate (11);
a first passivation layer (14) formed on the first insulating layer (13), the first passivation layer (14) having a prism structure;
a planarization layer (15) formed on the first insulating layer (13) and covering the first passivation layer (14);
a second insulating layer (16) formed on the planarization layer (15);
and a first metal layer formed on the second insulating layer (16), wherein the first metal layer includes a gate electrode (17) and a scan line, and the second insulating layer (16) and the first metal layer have the same patterned structure and are stacked one on another.
7. The thin film transistor array substrate of claim 6, further comprising:
a gate insulating layer (18) formed on the planarization layer (15) and covering the gate electrode (17) and the scan line;
an active layer (19) formed on the gate insulating layer (18);
a pixel electrode (20) formed on the gate insulating layer (18);
a second metal layer formed on the gate insulating layer (18), wherein the second metal layer includes a source electrode (211), a drain electrode (212), and a data line, the source electrode (211) and the drain electrode (212) are respectively connected to the active layer (19), and the source electrode (211) is connected to the data line, and the drain electrode (212) is connected to the pixel electrode (20);
a second passivation layer (22) formed on the gate insulating layer (18), wherein the second passivation layer (22) covers the source electrode (211), the drain electrode (212), the data line, the pixel electrode (20), and the active layer (19).
8. The thin film transistor array substrate of claim 7, further comprising:
a common electrode wiring layer (12) formed on the substrate (11), an upper region of the common electrode wiring layer (12) being provided with a through hole (181), the through hole (181) penetrating the gate insulating layer (18) and the second passivation layer (22);
a common electrode (23) formed on the second passivation layer (22), the common electrode (23) filling in the through hole (181) and being connected to the common electrode wiring layer (12).
9. The thin film transistor array substrate of any one of claims 6 to 8, wherein the first insulating layer (13) is made of silicon oxynitride or silicon oxide, and the first passivation layer (14) is made of silicon nitride.
10. The thin film transistor array substrate of any one of claims 6 to 8, wherein the first insulating layer (13) has a thickness of
The first passivation layer (14) has a thickness of
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| CN113540126A (en) * | 2021-07-19 | 2021-10-22 | 昆山龙腾光电股份有限公司 | Array substrate and manufacturing method |
| CN113540126B (en) * | 2021-07-19 | 2024-03-12 | 昆山龙腾光电股份有限公司 | Array substrate and manufacturing method |
| CN114171516A (en) * | 2021-12-08 | 2022-03-11 | 深圳市华星光电半导体显示技术有限公司 | Manufacturing method of array substrate, array substrate and display panel |
| CN114171516B (en) * | 2021-12-08 | 2023-07-25 | 深圳市华星光电半导体显示技术有限公司 | Manufacturing method of array substrate, array substrate and display panel |
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