CN112256502A - Memory performance test method, device and chip - Google Patents
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Abstract
The application provides a memory performance test method, a device and a chip, which are applied to a main core processor of the chip, wherein the chip is externally connected with a memory, the chip also comprises at least one slave core processor, and the method comprises the following steps: the method comprises the steps that a master core processor sends a first IPI (interrupt instruction) to at least one slave core processor respectively, wherein the first IPI is used for indicating the start of executing a performance test task of a memory; when the waiting time is up, sending a second IPI instruction to each slave core processor, wherein the second IPI instruction is used for indicating to stop executing the performance test task of the memory; obtaining the memory space size occupied by the memory space of the memory tested by each slave core processor when executing the performance test task of the memory; and determining the memory performance test result of the memory according to the time difference between the sending of the first IPI instruction and the sending of the second IPI instruction and the size of the memory space occupied by the memory space of the memory tested by each slave core processor. Thereby providing accuracy of memory performance test results.
Description
Technical Field
The present application relates to the field of storage technologies, and in particular, to a method, an apparatus, and a chip for testing memory performance.
Background
The memory is a very important component in a computer system, and is a bridge for the communication between the external memory and the CPU. In general, almost all programs in a computer system run in a memory, and at the same time, the performance of the memory at the present stage is significantly lower than the performance of components such as a CPU, a Level 1 Cache (L1C), a Level 2 Cache (L2C), and the like, so that the performance of the memory itself greatly affects the performance of the entire computer system. Based on the above considerations, it is very important to test the memory in chip development and PCB design to obtain the best performance data of the memory, especially in chip development, because the integration of the whole memory system is involved besides the performance difference between different types of memory particles, and each link may affect the performance of the whole memory system.
The existing memory performance test method is generally to develop a performance test program through a high-level language at an application layer of an Operating System (OS) to test the performance of a memory, and the basic implementation principle is to apply for a section of memory space through a function similar to calloc (), then record the start time of the test when the test starts and start the read-write access to the section of space, record the end time of the test after the section of memory access is completed, and finally calculate the speed of accessing the memory through two time differences and the size of the accessed memory space and display the performance value through a print function. Although the method is simple to implement, the performance of the memory can be observed visually, but the performance data obtained by the method is not the limit performance of the memory, but only the maximum speed at which the single core can access the memory, namely the limit performance of the single core, namely the maximum bandwidth of the memory, namely the optimal performance, cannot be measured by the method; in addition, the high-level language is adopted to write the test program, although the high-level language is easy to understand and convenient for program development, the high-level language has the defects of long codes, low running speed and low efficiency, namely, the performance test program developed by the high-level language is not suitable for the memory performance test with strict requirements on time and efficiency.
Therefore, how to accurately test the performance of the memory is one of the considerable technical problems.
Disclosure of Invention
In view of the above, the present application provides a method, an apparatus and a chip for testing memory performance, so as to accurately test the performance of a memory.
Specifically, the method is realized through the following technical scheme:
according to a first aspect of the present application, a method for testing memory performance is provided, which is applied to a master core processor of a chip, wherein a memory is externally hung on the chip, the chip further includes at least one slave core processor, and the method includes:
the master core processor sends a first inter-processor interrupt (IPI) instruction to the at least one slave core processor, wherein the first IPI instruction is used for indicating each slave core processor to start to execute the performance test task of the memory;
when the waiting time is up, sending a second IPI instruction to each slave core processor, wherein the second IPI instruction is used for indicating each slave core processor to stop executing the performance test task of the memory;
obtaining the memory space size occupied by the memory space of the memory tested by each slave core processor when executing the performance test task of the memory;
and determining a memory performance test result of the memory according to the time difference between the sending of the first IPI instruction and the sending of the second IPI instruction and the size of the memory space occupied by the memory space of the memory tested by each slave core processor.
According to a second aspect of the present application, another memory performance testing method is provided, which is applied to each slave core processor of a chip, where a memory is externally hung on the chip, the chip further includes a master core processor, and the method includes:
each slave core processor receives a first inter-processor interrupt IPI instruction sent by the master core processor;
starting to execute the performance test task of the memory;
receiving a second IPI instruction sent by the main core processor when the waiting time is up;
and stopping executing the performance test task of the memory.
According to a third aspect of the present application, there is provided a memory performance testing apparatus, applied to a master core processor of a chip, where the chip is externally connected with a memory, the chip further includes at least one slave core processor, and the apparatus includes:
the sending module is used for sending a first inter-processor interrupt (IPI) instruction to the at least one slave core processor, wherein the first IPI instruction is used for indicating each slave core processor to start to execute the performance test task of the memory;
the sending module is further configured to send a second IPI instruction to each slave core processor when the waiting time reaches, where the second IPI instruction is used to instruct each slave core processor to stop executing the performance test task of the memory;
the obtaining module is used for obtaining the memory space size occupied by the memory space of the memory tested by each slave core processor when executing the performance test task of the memory;
and the determining module is used for determining the memory performance test result of the memory according to the time difference between the sending of the first IPI instruction and the sending of the second IPI instruction and the memory space occupied by the memory space of the memory tested by each slave core processor.
According to a fourth aspect of the present application, there is provided another memory performance testing apparatus, applied to each slave core processor of a chip, where a memory is externally attached to the chip, the chip further includes a master core processor, and the apparatus includes:
the system comprises a receiving module, a judging module and a judging module, wherein the receiving module is used for receiving a first inter-processor interrupt IPI instruction sent by a main core processor;
the task execution module is used for starting to execute the performance test task of the memory when receiving the first IPI instruction;
the receiving module is further used for receiving a second IPI instruction sent by the main core processor when the waiting time is up;
and the task execution module is further configured to stop executing the performance test task of the memory when the second IPI instruction is received.
According to a fifth aspect of the present application, there is provided a chip comprising: the device comprises a main core processor and at least one slave core processor, wherein a memory is externally hung on the chip, the main core processor is used for executing the memory performance testing method provided by the first aspect of the application, and each slave core processor is used for executing the memory performance testing method provided by the second aspect of the application.
The beneficial effects of the embodiment of the application are as follows:
by respectively sending the first IPI instruction and the second IPI instruction to each slave core processor, the performance test of the memory can be simultaneously performed by the plurality of slave core processors in parallel, and the performance test error caused by the time difference among different cores is avoided, so that the accuracy of the performance test result of the memory is improved.
Drawings
Fig. 1 is a schematic flowchart of a method for testing memory performance according to an embodiment of the present disclosure;
fig. 2 is a schematic flowchart of another memory performance testing method according to an embodiment of the present disclosure;
fig. 3 is a schematic flowchart of another memory performance testing method according to an embodiment of the present disclosure;
fig. 4 is a block diagram of a memory performance testing apparatus according to an embodiment of the present disclosure;
fig. 5 is a block diagram of another memory performance testing apparatus according to an embodiment of the present disclosure.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the corresponding listed items.
It is to be understood that although the terms first, second, third, etc. may be used herein to describe various information, such information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the present application. The word "if" as used herein may be interpreted as "at … …" or "when … …" or "in response to a determination", depending on the context.
The memory performance testing method provided by the present application is described in detail below.
Referring to fig. 1, fig. 1 is a flowchart of a memory performance testing method provided by the present application, where the method is applied to a master core processor of a chip, the chip is externally connected with a memory, the chip further includes at least one slave core processor, and a flow of the master core processor executing the method may include the following steps:
s101, sending a first inter-processor interrupt IPI instruction to at least one slave core processor.
The first Inter-Processor Interrupt (IPI) instruction is used to instruct each slave core Processor to start executing the performance test task of the memory.
In this step, since the performance of the memory has a great influence on the performance of the whole computer system, the performance of the memory must be accurately tested in the chip design stage. For a system with better memory performance, if a test program is run on only one CPU core to test the memory performance, the measured performance data is not the best performance of the memory, but the best read/write performance of the CPU core. Therefore, in order to better and accurately measure the performance of the memory, the method provides that when the performance test of the memory is executed, the master core processor sends a first IPI instruction to at least one slave core processor, and all the slave core processors can be ensured to simultaneously receive the IPI interrupt from the master core processor by implementing the interrupt, so that the performance test tasks of the memory can be immediately and simultaneously executed after all the slave core processors receive the IPI interrupt.
It should be noted that, when only one slave core processor is included in a chip, a processing procedure of the slave core processor is similar to a processing procedure in which the chip includes a plurality of slave core processors, and therefore, for convenience of description, the subsequent embodiments of the present application will be described only by taking an example in which the chip includes a plurality of slave core processors.
In addition, the current first timestamp may also be recorded when the first IPI instruction is sent.
It should be noted that at least one slave core processor referred to in this application may be one of the chips, may be multiple of the chips, and may also be all the slave core processors in the chips, which may be determined specifically according to the actual situation. Generally, when a plurality of slave core processors are included in a chip, a first IPI instruction is sent to all the slave core processors to obtain an optimal memory performance test result.
S102, judging whether the waiting time is up, if so, executing a step S103; otherwise, the step S102 is continued.
In this step, since the slave core processor may spend some time when executing the performance test task of the memory, the present application may estimate the estimated time required for executing the performance test task of the memory in advance in the master core processor, and then set a waiting time based on the required time, where the waiting time should be less than the required estimated time, so as to ensure that the memory performance test task of each slave core processor is still executed, so as to avoid occurrence of a situation that the memory performance test has a deviation due to the fact that the slave core processor has completed the memory performance test task when triggering the second IPI instruction. In addition, each slave core processor starts to execute the performance test task of the memory at the same time, so that the method and the device can only set one waiting time.
And S103, sending a second IPI instruction to each slave core processor.
And the second IPI instruction is used for indicating each slave core processor to stop executing the performance test task of the memory.
Specifically, on the basis of ensuring that all the slave core processors start to execute the performance test tasks of the memory at the same time, it is further required to ensure that all the slave core processors stop executing the performance test tasks of the memory at the same time, so that it can be ensured that all the slave core processors are executed absolutely in parallel in the whole test process. And the performance test task of stopping executing the memory by all the slave core processors at the same time is also realized by IPI interruption. That is, after the master core processor sends out the IPI interrupt for the first time, that is, after sending the first IPI instruction, all the slave core processors start to execute the performance test tasks of the memory, the master core processor sends out the IPI interrupt again after waiting for a period of time, that is, sends the second IPI instruction to each slave core processor, and at this time, all the slave core processors receive the second IPI interrupt at the same time, so as to ensure that all the slave core processors stop executing the performance test tasks of the memory at the same time.
On this basis, when the waiting time is up, the slave core processors still execute the performance test tasks of the memories, and then the second IPI instructions are respectively sent to the slave core processors, and the interrupt instructions indicate that the slave core processors suspend the performance test tasks of the memories. By actively sending the interrupt instruction instead of passively waiting for each slave core processor to report the test completion, the slave core processors can be ensured to simultaneously stop executing the performance test task of the memory.
In addition, when the second IPI instruction is sent to each slave core processor, a second timestamp of when the second IPI instruction is sent may be recorded.
And S104, obtaining the memory space size occupied by the memory space of the memory tested by each slave core processor when executing the performance test task of the memory.
Specifically, each slave core processor accesses the memory space of the memory when executing the performance test task of the memory, and therefore, the master core processor can obtain the memory space occupied by the memory space tested by each slave core processor when executing the performance test task of the memory.
And S105, determining a memory performance test result of the memory according to the time difference between the sending of the first IPI instruction and the sending of the second IPI instruction and the size of the memory space occupied by the memory space of the memory tested by each slave core processor.
In this step, the master core processor may determine a time difference between the two timestamps based on the recorded first timestamp and the second timestamp, and then may calculate a memory performance test result of the memory based on the obtained memory space occupied by the memory space of the memory tested by each slave core processor and the time difference.
Specifically, when determining the memory performance test result of the memory, reference may be made to a currently given calculation method, which is not limited in this application. However, each slave core processor executes the memory performance test task simultaneously, so the time difference is accurate in the application, and the memory performance test result obtained by the application is also accurate even if the currently provided calculation method is adopted by combining the memory space occupied by the memory space of the memory tested by each slave core processor.
Therefore, by implementing the memory performance testing method provided by the application, the performance test of the memory can be simultaneously performed by a plurality of slave core processors in parallel by respectively sending the first IPI instruction and the second IPI instruction to each slave core processor, and the performance test error caused by the time difference between different cores is avoided, so that the accuracy of the performance test result of the memory is improved.
Optionally, the memory performance testing process provided by the present application may be performed on a Bare Metal (BM) testing platform running in a Bare Metal environment, because the testing result is closer to the bottom hardware than the OS application layer BM is, the testing result may be more accurate.
Before implementing step S101, that is, before sending the first inter-processor interrupt IPI instruction to each of the at least one slave core processor, this embodiment may further include the following process: and initializing each slave core processor to send the entry address of the memory performance test program to each slave core processor, wherein the memory performance test program is a program called when the slave core processor executes the performance test task of the memory.
Specifically, in order to ensure that each slave core processor can accurately call the memory performance test program when starting to execute the performance test task of the memory, the application provides that the master core processor maintains an interrupt vector table, and the interrupt vector table stores the entry address of the memory performance test program; then, when each slave core is initialized, the entry address of the memory performance test program is initialized to each slave core processor. Therefore, after each slave core processor receives the first IPI instruction, the memory performance test program can be called to execute the performance test task of the memory based on the entry address.
In one possible implementation manner, before implementing step S101, that is, before sending the first inter-processor interrupt IPI instruction to the at least one slave core processor, the following process may be performed: starting each slave core processor; and confirms that each slave core processor successfully boots.
Specifically, in order to ensure that each slave core processor executes the performance test task at the same time, each slave core processor is started before the first IPI instruction is sent, and after each slave core processor in the chip is started successfully, the first IPI instruction is sent to each slave core processor, so that each slave core processor is further ensured to execute the performance test task of the memory at the same time.
In this embodiment, when the multi-core chip runs on the BM, the master-core processor is started first, and after the master-core processor is started, the interrupt vector table is initialized for all the slave-core processors to indicate the entry address of the test program that needs to be run after the slave-core processor receives the IPI interrupt. The master core processor then activates all slave core processors either serially or in parallel. And after each slave core processor is started and ready, waiting for the master core processor to send the IPI interrupt through a scheduling instruction pause action. The method comprises the steps that a master core processor sends a first IPI instruction after all slave core processors are ready to start, so that the slave core processors start to run a memory performance test program when receiving the first IPI instruction no matter how the starting sequence and the starting speed of the slave core processors are.
Optionally, the interrupt vector table in the present application may be stored in a memory of the chip plug-in, or may be stored in a Synchronous Dynamic Random Access Memory (SDRAM), where the SDRAM is independent from the memory plug-in, and when the SDRAM is stored in the memory, it is to be ensured that a memory performance test program does not access a memory space corresponding to the interrupt vector table, that is, does not access the interrupt vector table, when performing a performance test of the memory.
Optionally, the memory performance test program is implemented in assembly language, and implementation codes of steps except the memory performance test program can be implemented in C language, so that the memory performance test program is more convenient and easier to develop, and accuracy of a memory performance test result is not affected.
Optionally, in a possible implementation manner, before implementing step S101, that is, before sending the first inter-processor interrupt IPI instruction to the at least one slave core processor, the following process may also be performed: applying for setting a memory space from the memory; and respectively allocating a first storage address and a second storage address to each slave core processor based on the local range of the set memory space, wherein the storage position corresponding to the first storage address allocated to each slave core processor is used for storing the initial access address of the memory space tested by the slave core processor, and the storage position corresponding to the second storage address allocated to each slave core processor is the actual access address of the memory space accessed by the slave core processor when the performance test task of the memory is executed.
In this embodiment, the first storage addresses corresponding to different slave core processors are different, and the second storage addresses corresponding to different slave core processors are also different.
Specifically, for the convenience of testing, the master core processor applies for a set memory space from the memory before counting the memory space size of the memory space tested by each slave core processor, the set memory space is dedicated for storing test-related data, e.g. a first memory address and a second memory address are assigned to each slave core processor, so that, when the slave core processor executes the memory test task, writing the initial access address of the memory space tested by the slave core processor into the storage position corresponding to the first storage address, then the actual access address of the memory space accessed by the slave core processor when executing the performance test task of the memory is stored in the storage position corresponding to the second storage address, the actual access address can be understood as a real-time access address, which dynamically changes during the performance test task of the memory.
Optionally, the memory spaces tested by different slave core processors are different from each other; when the non-overlapping memory spaces are distributed to each slave core processor, the memory spaces are uniformly distributed in the whole memory and are not overlapped with each other, so that the read-write performance of the memory can be ensured to be exerted to the maximum extent.
Further, step S104 may be implemented according to the following procedure: determining the size of a memory space occupied by the memory space tested by each slave core processor based on a starting access address and an ending access address of each slave core processor when executing the performance test task of the memory, wherein the ending access address is an actual access address of the memory space accessed by the slave core processor when stopping executing the performance test task of the memory.
Specifically, for each slave core processor, the master core processor performs difference processing on an ending access address and a starting access address stored in a set memory space by the slave core processor, so as to obtain the memory space size occupied by the memory space tested by the slave core processor. And then the main core processor can calculate the memory performance test result of the memory by combining the time difference of sending the IPI instruction twice.
By verification, the memory writing speed (memory performance test result) measured by using the mbw tool is about 23KB/s for the same memory, and by adopting the method provided by the application, the memory writing speed (memory performance test result) measured by starting a plurality of slave core processors is about 71KB/s, so that the accuracy of the memory performance test result is obviously improved.
Based on the same inventive concept, the present application also provides a memory performance testing method, please refer to fig. 2, the method is applied to each slave core processor of a chip, the chip is externally connected with a memory, the chip further comprises a master core processor, and each slave core processor can perform the following steps when implementing the method:
s201, receiving a first IPI instruction sent by a main core processor.
And S202, starting to execute the performance test task of the memory.
Alternatively, the following procedure may be implemented: and calling the memory performance test program based on the entry address of the memory performance test program acquired from the initialization of the core processor so as to execute the performance test task of the memory.
S203, receiving a second IPI instruction sent by the main core processor when the waiting time is up.
And S204, stopping executing the performance test task of the memory.
Optionally, the memory performance testing method provided in this embodiment further includes:
storing the initial access address of the memory space tested by the slave core processor in a storage position corresponding to a first storage address allocated to the slave core processor by the master core processor;
storing the actual access address of the memory space accessed by the slave core processor when executing the performance test task of the memory in the storage position corresponding to the second storage address allocated to the slave core processor by the master core processor;
and the storage position corresponding to the first storage address and the storage position corresponding to the second storage address are both contained in a set memory space applied by the main core processor from the memory.
It should be noted that, the implementation of any of the above processes can refer to the method described in the flow chart shown in fig. 1, and is not listed here in detail.
By implementing the embodiment, the performance test tasks of the memories can be ensured to be started and stopped simultaneously by the slave core processors, so that the performance test error caused by time difference errors caused by different starting and stopping times among the slave core processors is avoided, namely, the accuracy of the performance test result of the memories is improved.
For better understanding the memory performance testing method provided in the present application, reference may be made to the flow shown in fig. 3: taking the performance test of the memory by using all the slave core processors in the chip as an example for explanation, firstly, the master core processor is started; after the master core processor is started, initializing the slave core processors in the chip, and informing the entry addresses of the memory performance test programs to all the slave core processors; then starting the slave core processors, wherein each slave core processor can be started in series or in parallel; waiting for the slave core processor to start; it should be noted that after the start of any slave core processor is completed, the start state is fed back to the master core processor; the master core processor can judge whether all the slave core processors are started completely, and if all the slave core processors are started completely, first IPI instructions are sent to all the slave core processors at the same time, namely, first IPI interruption is triggered, so that all the slave core processors can receive the first IPI instructions at the same time, and then the memory performance test program can be called by using the entry address of the memory performance test program to start testing the performance of the memory; and meanwhile, the master core processor judges whether the waiting time is up, and if the waiting time is up, a second IPI instruction is sent to each slave core processor, namely, a second IPI interruption is triggered, so that each slave core processor simultaneously receives the second IPI instruction and then simultaneously stops executing the performance test task of the memory. In this way, the master core processor obtains the memory space size occupied by the memory space tested by each slave core processor when executing the memory performance test task, and then the memory performance test result of the memory can be determined based on the time difference between the sending of the first IPI instruction and the sending of the second IPI instruction and the memory space size occupied by the memory space tested by each slave core processor.
Based on the same invention concept, the application also provides a memory performance testing device corresponding to the memory performance testing method implemented by the main core processor. The implementation of the memory performance testing apparatus may refer to the above description of the memory performance testing method implemented by the main core processor, which is not discussed herein one by one.
Referring to fig. 4, fig. 4 is a memory performance testing apparatus provided in an exemplary embodiment of the present application, which is applied to a master core processor of a chip, where the chip is externally connected with a memory, the chip further includes at least one slave core processor, and the apparatus includes:
a sending module 401, configured to send a first inter-processor interrupt IPI instruction to the at least one slave core processor, where the first IPI instruction is used to instruct each slave core processor to start executing the performance test task of the memory;
the sending module 401 is further configured to send a second IPI instruction to each slave core processor when the waiting time reaches, where the second IPI instruction is used to instruct each slave core processor to stop executing the performance test task of the memory;
an obtaining module 402, configured to obtain a memory space size occupied by a memory space of a memory tested by each slave core processor when executing a performance test task of the memory;
the determining module 403 is configured to determine a memory performance test result of the memory according to a time difference between sending the first IPI instruction and sending the second IPI instruction and a memory space occupied by a memory space of the memory tested by each slave core processor.
Optionally, the memory performance testing apparatus provided in the present application further includes: the initialization module 404, also shown in FIG. 4, includes:
the initialization module 404 is configured to initialize each slave core processor to send an entry address of a memory performance test program to each slave core processor, where the memory performance test program is a program called when the slave core processor executes a performance test task of the memory.
Optionally, the memory performance testing apparatus provided in the present application further includes: the memory application module 405 and the address allocation module 406 are also shown in fig. 4, where:
the memory application module 405 is configured to apply for setting a memory space from the memory;
the address allocation module 406 is configured to allocate a first storage address and a second storage address to each slave core processor based on the local range of the set memory space, where a storage location corresponding to the first storage address allocated to each slave core processor is used to store an initial access address of the memory space tested by the slave core processor, and a storage location corresponding to the second storage address allocated to each slave core processor is an actual access address of the memory space accessed by the slave core processor when executing a performance test task of the memory;
on this basis, the obtaining module 402 is specifically configured to determine, based on a starting access address and an ending access address of each slave core processor when executing the performance test task of the memory, a size of a memory space occupied by the memory space tested by the slave core processor, where the ending access address is an actual access address of the memory space accessed by the slave core processor when stopping executing the performance test task of the memory.
Optionally, the memory performance testing apparatus provided in the present application may further include: the start module 407 and the confirmation module 408 are also shown in fig. 4, in which:
a starting module 407, configured to start each slave core processor;
and a confirmation module 408 for confirming that each slave core processor successfully starts.
Based on the same inventive concept, the application also provides a memory performance testing device corresponding to the memory performance testing method implemented by the slave core processor. The implementation of the memory performance testing apparatus may refer to the above description of the memory performance testing method implemented by the slave core processor, which is not discussed herein one by one.
Referring to fig. 5, fig. 5 is another memory performance testing apparatus provided in an exemplary embodiment of the present application, which is applied to each slave core processor of a chip, where the chip is externally connected with a memory, the chip further includes a master core processor, and the apparatus includes:
a receiving module 501, configured to receive an inter-processor interrupt IPI instruction sent by a main core processor;
a task execution module 502, configured to start executing a performance test task of the memory when receiving the first IPI instruction;
the receiving module 501 is further configured to receive a second IPI instruction sent by the main core processor when the waiting time arrives;
the task execution module 502 is further configured to stop executing the performance test task of the memory when the second IPI instruction is received.
Optionally, the task execution module 502 is specifically configured to call the memory performance test program based on an entry address of the memory performance test program acquired during initialization of the core processor, so as to execute the performance test task of the memory.
Optionally, the memory performance testing apparatus provided in this embodiment further includes: the memory module 503 is also shown in fig. 5, in which:
the storage module 503 is configured to store the initial access address of the memory space tested by the slave core processor in a storage location corresponding to the first storage address allocated by the master core processor to the slave core processor; storing the actual access address of the memory space accessed by the slave core processor when executing the performance test task of the memory in the storage position corresponding to the second storage address allocated to the slave core processor by the master core processor;
and the storage position corresponding to the first storage address and the storage position corresponding to the second storage address are both contained in a set memory space applied by the main core processor from the memory.
Based on the same inventive concept, the application also provides a chip, which comprises a master core processor and at least one slave core processor, wherein a memory is externally hung on the chip, the master core processor is used for executing the memory performance test method provided by any embodiment implemented by the master core processor, and each slave core processor is used for executing any memory performance test method provided by any embodiment implemented by the slave core processor.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The implementation process of the functions and actions of each unit/module in the above device is specifically described in the implementation process of the corresponding step in the above method, and is not described herein again.
For the device embodiments, since they substantially correspond to the method embodiments, reference may be made to the partial description of the method embodiments for relevant points. The above-described embodiments of the apparatus are merely illustrative, wherein the units/modules described as separate parts may or may not be physically separate, and the parts displayed as units/modules may or may not be physical units/modules, may be located in one place, or may be distributed on a plurality of network units/modules. Some or all of the units/modules can be selected according to actual needs to achieve the purpose of the scheme of the application. One of ordinary skill in the art can understand and implement it without inventive effort.
The above description is only exemplary of the present application and should not be taken as limiting the present application, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the scope of protection of the present application.
Claims (10)
1. A memory performance test method is characterized in that the method is applied to a main core processor of a chip, the chip is externally provided with a memory, the chip also comprises at least one slave core processor, and the method comprises the following steps:
the master core processor sends a first inter-processor interrupt (IPI) instruction to the at least one slave core processor, wherein the first IPI instruction is used for indicating each slave core processor to start to execute the performance test task of the memory;
when the waiting time is up, sending a second IPI instruction to each slave core processor, wherein the second IPI instruction is used for indicating each slave core processor to stop executing the performance test task of the memory;
obtaining the memory space size occupied by the memory space of the memory tested by each slave core processor when executing the performance test task of the memory;
and determining a memory performance test result of the memory according to the time difference between the sending of the first IPI instruction and the sending of the second IPI instruction and the size of the memory space occupied by the memory space of the memory tested by each slave core processor.
2. The method of claim 1, further comprising, prior to sending the first inter-processor interrupt (IPI) instruction to the at least one slave core processor, respectively:
and initializing each slave core processor to send the entry address of a memory performance test program to each slave core processor, wherein the memory performance test program is a program called when the slave core processor executes the performance test task of the memory.
3. The method of claim 1, further comprising, prior to sending the first inter-processor interrupt (IPI) instruction to the at least one slave core processor, respectively:
applying for setting a memory space from the memory;
respectively allocating a first storage address and a second storage address to each slave core processor based on the local range of the set memory space, wherein a storage position corresponding to the first storage address allocated to each slave core processor is used for storing an initial access address of the memory space tested by the slave core processor, and a storage position corresponding to the second storage address allocated to each slave core processor is an actual access address of the memory space accessed by the slave core processor when executing a performance test task of the memory;
the method for obtaining the memory space size occupied by the memory space of the memory tested by each slave core processor when executing the performance test task of the memory comprises the following steps:
determining the size of a memory space occupied by the memory space tested by each slave core processor based on a starting access address and an ending access address of each slave core processor when executing the performance test task of the memory, wherein the ending access address is an actual access address of the memory space accessed by the slave core processor when stopping executing the performance test task of the memory.
4. The method of claim 1, further comprising, prior to sending the first inter-processor interrupt (IPI) instruction to the at least one slave core processor, respectively:
starting each slave core processor; and are
Confirming the successful start of each slave core processor.
5. A memory performance test method is characterized in that the method is applied to each slave core processor of a chip, the chip is externally provided with a memory, the chip also comprises a master core processor, and the method comprises the following steps:
each slave core processor receives a first inter-processor interrupt IPI instruction sent by the master core processor;
starting to execute the performance test task of the memory;
receiving a second IPI instruction sent by the main core processor when the waiting time is up;
and stopping executing the performance test task of the memory.
6. The method of claim 5, wherein initiating execution of the performance testing task for the memory comprises:
and calling the memory performance test program based on the entry address of the memory performance test program acquired from the initialization of the core processor so as to execute the performance test task of the memory.
7. The method of claim 5, further comprising:
storing the initial access address of the memory space tested by the slave core processor in a storage position corresponding to a first storage address allocated to the slave core processor by the master core processor;
storing the actual access address of the memory space accessed by the slave core processor when executing the performance test task of the memory in the storage position corresponding to the second storage address allocated to the slave core processor by the master core processor;
and the storage position corresponding to the first storage address and the storage position corresponding to the second storage address are both contained in a set memory space applied by the main core processor from the memory.
8. The utility model provides a memory performance test device which characterized in that, is applied to the main core processor of chip, the chip joins externally has the memory, the chip still includes at least one from the core processor, and the device includes:
the sending module is used for sending a first inter-processor interrupt (IPI) instruction to the at least one slave core processor, wherein the first IPI instruction is used for indicating each slave core processor to start to execute the performance test task of the memory;
the sending module is further configured to send a second IPI instruction to each slave core processor when the waiting time reaches, where the second IPI instruction is used to instruct each slave core processor to stop executing the performance test task of the memory;
the obtaining module is used for obtaining the memory space size occupied by the memory space of the memory tested by each slave core processor when executing the performance test task of the memory;
and the determining module is used for determining the memory performance test result of the memory according to the time difference between the sending of the first IPI instruction and the sending of the second IPI instruction and the memory space occupied by the memory space of the memory tested by each slave core processor.
9. The utility model provides a memory performance test device which characterized in that, is applied to every from the core processor of chip, the chip is external to have the memory, the chip still includes main core processor, and the device includes:
the system comprises a receiving module, a judging module and a judging module, wherein the receiving module is used for receiving a first inter-processor interrupt IPI instruction sent by a main core processor;
the task execution module is used for starting to execute the performance test task of the memory when receiving the first IPI instruction;
the receiving module is further used for receiving a second IPI instruction sent by the main core processor when the waiting time is up;
and the task execution module is further configured to stop executing the performance test task of the memory when the second IPI instruction is received.
10. A chip, comprising: the system comprises a main core processor and at least one slave core processor, wherein a memory is hung outside a chip, the main core processor is used for executing the memory performance testing method of any one of claims 1 to 4, and each slave core processor is used for executing the memory performance testing method of any one of claims 5 to 7.
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