CN111124792A - Multi-core debugging method and device and storage medium - Google Patents
Multi-core debugging method and device and storage medium Download PDFInfo
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Abstract
The invention provides a multi-core debugging method, a device and a storage medium, wherein the method comprises the following steps: responding to a multi-core debugging instruction of a debugger, and when any core of a processor generates an interrupt, executing the following processing steps by taking the core as a target core: the target core instructs other cores of the processor to enter an interrupt; the target core sends the current context information to the debugger; the target core receives the debugging of the debugger and instructs other cores of the processor to exit the interrupt when runtime is resumed. The method is used for solving the problems of inter-core synchronization, inter-core communication, breakpoint synchronization, critical resource mutual exclusion access and the like when the GDB debugger conducts multi-core debugging, so that stable and reliable multi-core debugging is achieved.
Description
Technical Field
The present invention relates to the field of embedded system technologies, and in particular, to a multi-core debugging method, apparatus, and storage medium.
Background
Program debugging is the process of testing by manual or compiler method and correcting grammar and logic errors before the written computer program is put into actual operation. This is an essential step in ensuring the correctness of the computer information system. After the computer program is programmed, the computer program must be sent to a computer for testing. And further diagnosing according to errors found in the test, finding out reasons and specific positions and correcting.
The emergence of the multi-core processor brings new opportunities to an embedded system, and the emergence of the multi-core processor brings stronger computing performance to users, and can meet the requirements of the users on multitasking and multitasking computing environments. However, in order to maximize the advantages of the multi-core processor, various problems faced by the multi-core program debugging technology, such as inter-core synchronization, inter-core communication, breakpoint synchronization, and mutually exclusive access of critical resources, need to be solved. In the prior art, a GDB debugger is used as a preferred task-level debugger under a single-core architecture, and can be suspended at any specified breakpoint according to user requirements during program debugging, so that a user can check the running condition of the program and perform related debugging. However, in the multi-core program debugging process, due to the existence of the above problems of inter-core synchronization, inter-core communication, breakpoint synchronization, critical resource mutual exclusion access, etc., the GDB debugger cannot accurately and effectively reflect the information of the multi-core program through the original function, so that the function of the GDB debugger in the multi-core embedded system is very limited.
Disclosure of Invention
In view of the above, a main objective of the present invention is to provide a multi-core debugging method, apparatus and storage medium, so as to solve the problems of inter-core synchronization, inter-core communication, breakpoint synchronization, and critical resource mutual exclusion access faced by a GDB debugger during multi-core debugging, so as to implement stable and reliable multi-core debugging.
The technical scheme adopted by the invention is that the multi-core debugging method comprises the following steps:
responding to a multi-core debugging instruction of a debugger, and when any core of a processor generates an interrupt, executing the following processing steps by taking the core as a target core:
the target core instructs other cores of the processor to enter an interrupt;
the target core sends the current context information to the debugger;
the target core receives the debugging of the debugger and instructs other cores of the processor to exit the interrupt when runtime is resumed.
Therefore, the method realizes the synchronous control of the communication and the running state among the multiple cores by introducing the communication mechanism among the multiple cores on the basis of the real-time operating system debugging a single core, synchronously interrupts other cores by sending an inter-processor interrupt instruction when any core generates an interrupt in the process of carrying out the multiple core debugging, and instructs other cores to quit an interrupt processing program while recovering the running after the current core is debugged, thereby realizing the stable and reliable multiple core debugging.
Preferably, said one of the interrupts generated by any core of the processor comprises one of:
single step interruption, interruption triggering preset conditions and breakpoint abnormal interruption.
The single-step interruption is to stop to wait for indication after executing a line of statements, the breakpoint abnormal interruption is to set a breakpoint at a place needing to be suspended, then to run the program, to suspend and return to the debugging program without user intervention when executing to the breakpoint position, and to trigger the interruption of the preset condition, when the preset condition is satisfied, to generate the interruption, so that the debugger can perform some special operations on the specified core or all the cores.
Preferably, before the target core instructs other cores of the processor to enter the interrupt, the method further includes:
and acquiring the access qualification of the critical resource through atomic operation, and setting a memory barrier to prevent the access of other cores.
Therefore, when the target core accesses the critical resource, the critical resource is protected through atomic operation and a memory barrier, so that other cores are prevented from interfering with the access of the critical resource of the target core, meanwhile, the other cores are determined to be in a waiting state, and then the target core sends an interrupt instruction to control the other cores to enter interrupt.
Preferably, before the target core sends the current context information to the debugger, the method further includes: controlling the target core to enter an off-interrupt mode, and setting a network card to be a polling packet receiving mode;
correspondingly, the instructing the other cores to exit the interrupt further comprises: and controlling the target core to enter an interrupt mode, setting the network card to be in an interrupt packet receiving mode, and recovering the context information stored before the interrupt of the target core so as to continuously run the process on the target core.
After the target core sends the interrupt instruction to indicate other cores to enter the interrupt state, the current context information needs to be sent to the debugger for debugging, the target core needs to receive the exit interrupt instruction of the debugger before sending, and enters the off-interrupt state, and a network card between the target core and the debugger is also set to be in a polling packet receiving mode to wait for the context information sent by the target core; after the target core finishes reporting the context information, the target core enters a waiting state, after the debugger finishes debugging and sends a command for continuing execution, the target core can resume running according to the command for continuing execution and synchronously indicate other cores to quit interruption, at the moment, the target core enters an interruption state, the network card enters a packet receiving mode, the target core recovers the context information, and the target core waits for the arrival of the next interruption.
Preferably, the debugger is a GDB.
In the above, the GDB is a powerful command line debugging tool, and has functions of repairing network breakpoints, restoring links, and the like, thereby implementing more debugging functions.
Preferably, the instructing the other cores of the processor to enter the interrupt includes causing the other cores of the processor to enter a free-wheeling state; accordingly, the method can be used for solving the problems that,
the instructing the other cores of the processor to exit the interrupt includes causing the other cores of the processor to exit an idle state.
Therefore, under multi-core debugging, when one core is interrupted, the running states of other cores are changed through inter-core communication and running state control, for example, execution of a current program is abandoned, program running is rescheduled, special codes are executed, idling and the like, so that the method is more beneficial to debugging the interaction state among programs running across multiple cores.
Preferably, the indication is performed by an IPI instruction.
As such, an Inter-Processor Interrupt (IPI) is a special type of Interrupt, i.e., the act of an Interrupt issued by one Processor to another if the Interrupt handler requires action from another Processor in a multiprocessor system. The inter-processor interrupt (IPI) is an important component of a multi-core processor structure, and can be used for communication among multiple cores, so that the efficiency of the system is effectively improved.
Preferably, the method further comprises the following steps: when any core of the processor generates an interrupt, the current running state information of all the cores in the processor is acquired through a multi-core state control technology, the position of the core generating the interrupt is located, and the core is taken as a target core.
Therefore, because the inter-core synchronization problem exists in multi-core debugging, the running state information of all cores in the processor can be acquired through the multi-core state control technology to locate the position of the target core generating the interrupt, and in the process of debugging the target core, the running states of other cores also need to be monitored and changed, which can be more beneficial to debugging the interactive state among programs running across multiple cores.
Based on the above multi-core debugging method, the present invention also provides a multi-core debugging apparatus, comprising:
the debugger is used for debugging the multi-core processor;
the first trigger module is used for responding to a multi-core debugging instruction of a debugger, and when any core of the processor generates an interrupt, the core is taken as a target core to trigger the operation of the following modules;
the inter-core interrupt triggering module is used for indicating other cores of the processor to enter interrupt by the target core;
the context reporting module is used for sending the current context information to the debugger by the target core;
and the inter-core interrupt exit module is used for indicating other cores of the processor to exit the interrupt when the target core resumes the operation.
Therefore, the multi-core debugging device can receive and transmit the control instruction and the debugging instruction by the debugger during multi-core debugging so as to control the target core to enter or exit an interrupt state, meanwhile, relevant debugging is carried out according to context information reported by the target core, and the target core is issued to control the target core to execute the next step of instruction, and the target core realizes synchronous operation with other cores through an IPI mechanism.
Preferably, the debugger is further configured to perform polling monitoring on the operation states of all cores through a multi-core state control technology, and when polling is performed until a core generates an interrupt, the debugger takes the core as a target core and determines a type of the interrupt, and then performs corresponding debugging on the target core.
Therefore, the debugger monitors the running states of all cores by polling, when the target core generates an interrupt, the debugger can acquire the current context information of the target core and the identification information of the interrupt, and then can determine the type of the interrupt generated by the target core according to the identification information, such as single step interrupt, interrupt triggering preset conditions, and breakpoint abnormal interrupt, so as to perform corresponding debugging according to the specific interrupt type, and restore the context information to the target core after the debugging is completed, so that the target core continues to run.
Based on the multi-core debugging method, the invention also provides a computer storage medium, on which a computer program is stored, and the computer program realizes the steps of the multi-core debugging method when being executed by a processor.
Therefore, the storage medium is used for storing the computer program for executing the debugging method, and an executable carrier is provided for the debugging method, so that the debugging method is convenient to popularize and use.
Drawings
FIG. 1 is a block diagram of a multi-core debug apparatus according to the present invention;
FIG. 2 is a flowchart of a multi-core debugging method provided by the present invention;
FIG. 3 is a flow chart of the present invention host machine and multi-core processor establishing a debug relationship;
FIG. 4 is a flow diagram of a multi-core processor executing a host command in accordance with the present invention;
FIG. 5 is a flow diagram of the target core executing an exception handling function according to the present invention.
Detailed Description
The following describes in detail a specific embodiment of the multi-core debugging method based on a real-time operating system according to fig. 1 to 5.
As shown in fig. 2, an embodiment of the present invention provides a multi-core debugging method, which is applied to the multi-core debugging apparatus shown in fig. 1, where the multi-core debugging apparatus includes a host and a target,
the host machine comprises a debugger, preferably a GDB (graphics data bus), wherein the GDB debugger performs polling monitoring on the running state of a multi-core processor of the target machine through a multi-core state control technology, positions a certain core and takes the certain core as a target core when a certain core is polled to generate interruption, determines the type of the interruption generated by the target core and debugs the target core;
the target machine includes a multi-core processor; the first trigger module is used for responding to a multi-core debugging instruction of a debugger, and when any core of the multi-core processor generates an interrupt, the core is used as a target core to trigger the operation of the following modules; the inter-core interrupt triggering module is used for indicating other cores of the processor to enter interrupt by the target core; the context reporting module is used for sending the current context information to the debugger by the target core; and the inter-core interrupt exit module is used for indicating other cores of the processor to exit the interrupt when the target core resumes the operation. And the host machine and the target machine are in communication connection by using a network card.
Specifically, the multi-core debugging method provided by the embodiment of the invention comprises the following steps:
s100: establishing a debugging relation to the multi-core processor through a host machine, and starting a GDB debugger;
in the step, firstly, a debugging relation needs to be established between a host machine and a target machine, so that a multi-core processor in the target machine responds to an instruction of a GDB debugger in the host machine, and the GDB debugger can acquire debugging information of each core in the multi-core processor;
specifically, as shown in fig. 3, the process of establishing the debugging relationship between the host and the target is as follows:
s101-102: the host machine establishes communication connection with the target machine through the network card;
s103: debugging configuration such as program, parameter, single step or breakpoint setting is carried out on a multi-core processor in a target machine, and then a GDB debugger is started;
s104-105: when a preset breakpoint or single-step abnormal operation is performed in debugging configuration, the GDB debugger receives feedback of the running state of the multi-core processor and determines the position of a target core generating abnormal interruption so as to facilitate subsequent debugging;
s200: responding to a multi-core debugging instruction of a debugger, and when any core of a processor generates an interrupt, taking the core as a target core, and sending an interrupt instruction by the target core to instruct other cores of the processor to enter the interrupt;
in the step, the multi-core processor executes according to a multi-core debugging instruction preset by a GDB debugger, when a certain core executes the debugging instruction to generate interruption, the certain core is taken as a target core, the target core sends an interruption instruction to indicate other cores in the multi-core processor to enter interruption in the process of stopping operation, and the other cores refer to other cores which do not generate interruption in the multi-core processor;
as shown in fig. 4, in the embodiment of the present invention, the flow of the host command executed by the multicore processor is as follows:
s201-203: the multi-core processor in the target machine receives a command from the host machine through the network card, analyzes the command and sequentially executes functions in the command;
s204-205: when the host computer command is executed to generate abnormal interruption, feeding back the running state information of the multi-core processor to a GDB debugger of the host computer to determine the position of a target core generating the interruption, and at the moment, the GDB debugger sends an instruction entering an abnormal processing function to the target core to enable the GDB debugger to execute the abnormal processing function corresponding to the abnormal interruption;
it should be noted that the abnormal interrupt generated by the target core is a single-step interrupt, an interrupt triggering a preset condition, or a breakpoint abnormal interrupt, and the specifically selected interrupt mode can be a single-step interrupt according to the requirements in the actual debugging work, for example, if the program needs to execute one instruction, i.e., suspend once, to perform the status query and comparison; inserting some breakpoint instructions into a designated position or any position in a program to be debugged, and selecting interruption triggering a preset condition when the breakpoint instructions are executed and interruption is generated; and executing the complete program until the program cannot be continuously executed due to bug generation, debugging the bug, and selecting breakpoint abnormal interruption. The interrupt mode needs the target core to feed back the context information to the debugger.
S206-208: and the target core executes an exception handling function according to the instruction of the GDB debugger, synchronously sends an IPI interrupt instruction to indicate other cores to enter an idle running state in the process of stopping running, stores and reports the current context information to the GDB debugger, and waits for the debugging of the debugger.
It is worth noting that the state synchronization of the target core and other cores in the present invention needs to be realized through a multi-core state control technology. Different from the traditional single-core debugging, the multi-core debugging method has the problem of synchronization among multiple cores, the running states of all the cores are monitored through a multi-core state control technology in a normal state, when one core generates interruption, the running state information of all the cores needs to be acquired so as to position the position of the core generating the interruption, the core is determined as a target core, the core not generating the interruption is other cores, and the running states of the other cores need to be monitored and changed before and after the target core generating the interruption is debugged, so that the target core and the other cores keep the consistent running states.
In this embodiment, the changing of the operating states of the other cores is mainly to suspend the other cores and resume the other cores, that is, when the target core generates an interrupt, suspend the other cores and enter an idle state; after determining that other cores enter an idle state, debugging the target core by using a debugger; correspondingly, after the target core is debugged, other cores are recovered, the idle state is exited, and the program is continuously executed.
In this embodiment, the multi-core state control technology uses an IPI mechanism to implement communication between multiple cores and core operation state control, the IPI mechanism is a common mechanism for implementing the multi-core state control technology, and the IPI mechanism can implement communication between cores and core operation state control. When the multi-core debugging method generates interruption in a target core to be debugged, other cores need to be synchronously interrupted, the target core can inform the other cores by sending IPI interruption, when the other cores receive the IPI interruption, an inter-core interruption processing function is entered, and the inter-core interruption processing function enables the other cores to enter an idle state;
specifically, the IPI mechanism is mainly implemented by a related IPI initialization function, specifically, the IPI initialization function provides the following functions in the multi-core state control technology to implement mutual communication between the multi-core processors and maintain a uniform running state, and the IPI initialization function needs to call a part of function functions in the debug library, for example:
1) hooking an inter-core interrupt processing function, namely introducing the inter-core interrupt processing function into a multi-core processor, and when a certain core generates an interrupt, notifying other cores through an IPI interrupt instruction, so that the other cores can execute the hooked inter-core interrupt processing function to enter an idle state;
2) delivering an IPI interrupt instruction, namely sending the IPI interrupt instruction to other cores when a certain core generates interrupt;
3) enabling to debug the inter-core interrupt processing function, namely analyzing and executing the hooked inter-core interrupt processing function by other cores according to the IPI interrupt instruction received by the other cores, and entering an idle state;
4) and acquiring the ID of the current core, namely acquiring the ID of the target core to locate the position of the target core, so that the target core can execute the corresponding exception handling function according to the ID of the target core.
As shown in fig. 5, when the target core generates an interrupt, a preset exception handling function may be executed, where the exception handling function is a unified interface for handling a single-step or breakpoint exception, and specifically, before the target core executes the exception handling function, the method further includes the following steps:
s2071: when the target core is determined to be interrupted, the operating states of other cores need to be acquired and judged through the multi-core state control technology so as to judge whether the other cores are in the control state;
s2072: before the target core sends the IPI interrupt instruction to other cores, the access qualification of the critical resource is acquired through atomic operation, and a memory barrier is set to prevent the access of other cores. In the structure of the multi-core processor, because each core in the multi-core processor operates independently, even the operation which can be completed in a single instruction is possibly interfered, for example, some instructions access the memory twice in the execution process to form a process of reading, writing and reading, each step in the process is a micro operation, and the whole instruction is composed of a plurality of micro operations. Therefore, when a certain core writes a memory, other cores access the address, so that a plurality of cores interfere with each other to read and write results, critical resource protection needs to be performed through a spin lock mechanism when a debugger accesses a relevant critical resource, when one core accesses one critical resource (critical section), a spin lock needs to be acquired in advance, and if the spin lock cannot be acquired, the debugger waits in a null cycle spin lock until another core releases the spin lock, so that the critical resource protection is achieved. Therefore, the critical resource is protected by adopting the atomic operation and the memory barrier, so that the target core is not interfered by other cores when accessing the critical resource, and meanwhile, the other cores can be determined to be in the idle cycle spin lock waiting state, so that the target core sends an interrupt instruction to control the other cores to enter the interrupt;
s2073: the target core sends the IPI interrupt instruction to other cores according to the delivery IPI interrupt instruction in the IPI initialization function;
s2074-2076: after other cores receive an IPI interrupt instruction sent by a target core, executing the hooked inter-core interrupt processing function according to the enabled debugging inter-core interrupt processing function in the IPI initialization function, and entering an idle state;
at this time, the target core executes a corresponding exception handling function according to the ID of the target core, communicates with the GDB debugger, and proceeds to the following steps S300-S600;
s300: when the debugger determines that the target core generates interruption, the debugger sends a context information reporting instruction to the target core;
in this step, because the packet receiving mode of the communication network card between the multi-core processor and the GDB debugger is default to the interrupt mode, when the target core is interrupted, the interrupt information is fed back to the GDB debugger through the network card, at this time, the GDB debugger generates a context information reporting instruction according to the interrupt information and sends the context information reporting instruction to the target core generating the interrupt, and simultaneously controls the target core to enter the interrupt mode, that is, the target core does not receive other interrupt instructions any more, and sets the packet receiving mode of the network card to be the polling packet receiving mode.
S400: the target core sends the current context information to the debugger;
in this step, after receiving the context information reporting instruction of the GDB debugger, the target core collects and stores the context information before the interruption, and uploads the context information to the GDB debugger through the network card in the polling packet receiving mode.
S500: the debugger debugs the target core and sends a running recovery instruction to the target core after the debugging is finished;
s600: the target core receives the debugging of the debugger and instructs other cores of the processor to exit the interrupt when runtime is resumed.
Specifically, the step includes the following substeps:
s601: the target core receives debugging of the debugger and receives instructions of the debugger through a cycle packet receiving mode;
s602: when receiving an instruction of recovering the operation of the GDB debugger, the target core synchronously sends an instruction of recovering the operation of the IPI to other cores, and instructs the other cores to exit an idle state and continue to operate;
s603-604: the target core enters an interrupt-on mode, namely the target core can receive other interrupt instructions, the network card is set to be an interrupt-on mode, and after the target core recovers the context information stored before entering the interrupt processing program, the target core can continue to run synchronously with other cores, so that all processes of the target core for executing the exception handling function are completed.
In another embodiment of the present invention, the multi-core debugging method mentioned above may be further implemented in the form of a computer storage medium, on which a computer program is stored, so that when a computer device (which may be a personal computer, a server, or a network device, etc.) or a processor executes the computer program, part or all of the steps of the debugging method for a multi-core processor are implemented;
the storage medium may be any tangible medium that can contain, or store the computer program described above, for example, a portable disk, hard disk, Random Access Memory (RAM), Read Only Memory (ROM), erasable programmable read only memory (EPROM or flash memory), optical fiber, read only memory (CD-ROM), optical storage device, magnetic storage device, or the like, for use by or in connection with an instruction execution apparatus, device, or apparatus.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (10)
1. A multi-core debugging method, comprising:
responding to a multi-core debugging instruction of a debugger, and when any core of a processor generates an interrupt, executing the following processing steps by taking the core as a target core:
the target core instructs other cores of the processor to enter an interrupt;
the target core sends the current context information to the debugger;
the target core receives the debugging of the debugger and instructs other cores of the processor to exit the interrupt when runtime is resumed.
2. The method of claim 1, wherein generating the one of the interrupts by any core of a processor comprises one of:
single step interruption, interruption triggering preset conditions and breakpoint abnormal interruption.
3. The method of claim 1, wherein the target core further comprises, prior to instructing other cores of the processor to enter an interrupt:
and acquiring the access qualification of the critical resource through atomic operation, and setting a memory barrier to prevent the access of other cores.
4. The method of claim 3, wherein before the target core sends the current context information to the debugger, further comprising: controlling the target core to enter an off-interrupt mode, and setting a network card to be a polling packet receiving mode;
correspondingly, the instructing the other cores to exit the interrupt further comprises: and controlling the target core to enter an interruption mode, setting the network card to be in an interruption packet receiving mode, and recovering the context information stored before interruption of the target core.
5. The method of claim 1,
the instructing the other cores of the processor to enter the interrupt includes causing the other cores of the processor to enter a free-wheeling state; accordingly, the method can be used for solving the problems that,
the instructing the other cores of the processor to exit the interrupt includes causing the other cores of the processor to exit an idle state.
6. The method according to claim 1 or 5, wherein the indication is by an IPI instruction.
7. The method of claim 1, further comprising: when any core of the processor generates an interrupt, the current running state information of all the cores in the processor is acquired through a multi-core state control technology, the position of the core generating the interrupt is located, and the core is taken as a target core.
8. An apparatus for performing the multi-core debugging method of any one of claims 1 to 7, comprising:
the debugger is used for debugging the multi-core processor;
the first trigger module is used for responding to a multi-core debugging instruction of a debugger, and when any core of the processor generates an interrupt, the core is taken as a target core to trigger the operation of the following modules;
the inter-core interrupt triggering module is used for indicating other cores of the processor to enter interrupt by the target core;
the context reporting module is used for sending the current context information to the debugger by the target core;
and the inter-core interrupt exit module is used for indicating other cores of the processor to exit the interrupt when the target core resumes the operation.
9. The apparatus of claim 8, wherein the debugger is further configured to perform polling monitoring on the operating statuses of all cores through a multi-core status control technique, when polling occurs to a core, regarding the core as a target core and determining a type that causes an interrupt, and then performing corresponding debugging on the target core.
10. A computer storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of the multi-core debugging method of any of claims 1 to 7.
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