CN112256502B - Memory performance testing method, device and chip - Google Patents
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Abstract
The application provides a memory performance test method, a device and a chip, which are applied to a main core processor of the chip, wherein the chip is externally hung with a memory, and the chip also comprises at least one auxiliary core processor, and the method comprises the following steps: the method comprises the steps that a main core processor sends a first interruption IPI instruction to at least one auxiliary core processor respectively, wherein the first IPI instruction is used for indicating to start to execute performance test tasks of a memory; when the waiting time arrives, sending a second IPI instruction to each slave core processor, wherein the second IPI instruction is used for indicating to stop executing the performance test task of the memory; obtaining the memory space size occupied by the memory space of the tested memory when each slave core processor executes the performance test task of the memory; and determining a memory performance test result of the memory according to the time difference between the transmission of the first IPI instruction and the transmission of the second IPI instruction and the memory space size occupied by the memory space of the memory tested by each slave core processor. Thereby providing accuracy of memory performance test results.
Description
Technical Field
The present application relates to the field of memory technologies, and in particular, to a method, an apparatus, and a chip for testing memory performance.
Background
Memory is a very important component in computer systems, and is a bridge for communication between external memory and a CPU. In general, almost all programs in a computer system run in a memory, and at the same time, the performance of the memory is obviously lower than that of components such as a CPU, a Level 1 cache (l 1 c), a Level 2 cache (l 2 c) and the like, so that the performance of the memory itself has a great influence on the performance of the whole computer system. Based on the above factors, it is particularly important to test the memory in chip development and PCB design to obtain the best performance data of the memory, especially in chip development, because in addition to the performance differences among different types of memory particles, the integration of the whole memory system is involved, and each link may affect the performance of the whole memory system.
The basic implementation principle of the existing memory performance testing method is that a performance testing program is developed through a high-level language at an application layer of an Operating System (OS) to test the performance of a memory, a section of memory space is applied through a function similar to calloc (), then the starting time of the test is recorded at the beginning of the test, the read-write access is started to the section of space, the ending time of the test is recorded after the section of memory access is completed, finally the rate of accessing the memory is calculated through two time differences and the size of the accessed memory space, and the performance value is displayed through a printing function. Although the method is simple to realize, the performance of the memory can be intuitively observed, but the performance data obtained by the method is not the limit performance of the memory, but only the maximum rate of the memory access by the single core, namely the limit performance of the single core, namely the maximum bandwidth of the memory, namely the optimal performance, can not be measured by the method; in addition, the test program is written in a high-level language, which is easy to understand and convenient for program development, but has the defects of long code, low running speed and low efficiency, namely, the performance test program developed by the high-level language is not suitable for memory performance test with strict time and efficiency requirements.
Therefore, how to accurately test the performance of the memory is one of the technical problems.
Disclosure of Invention
In view of the above, the present application provides a method, an apparatus and a chip for testing performance of a memory, which are used for accurately testing performance of the memory.
Specifically, the application is realized by the following technical scheme:
according to a first aspect of the present application, there is provided a memory performance testing method applied to a master core processor of a chip, the chip being externally mounted with a memory, the chip further including at least one slave core processor, and the method comprising:
the main core processor sends a first inter-processor interrupt (IPI) instruction to the at least one auxiliary core processor, wherein the first IPI instruction is used for indicating each auxiliary core processor to start executing the performance test task of the memory;
when the waiting time arrives, sending a second IPI instruction to each slave core processor, wherein the second IPI instruction is used for indicating each slave core processor to stop executing the performance test task of the memory;
obtaining the memory space size occupied by the memory space of the tested memory when each slave core processor executes the performance test task of the memory;
and determining a memory performance test result of the memory according to the time difference between the transmission of the first IPI instruction and the transmission of the second IPI instruction and the memory space size occupied by the memory space of the memory tested by each slave core processor.
According to a second aspect of the present application, there is provided another memory performance testing method applied to each slave core processor of a chip, the chip having memory on the outside thereof, the chip further including a master core processor, and the method comprising:
each slave core processor receives a first inter-processor interrupt IPI instruction sent by a master core processor;
starting to execute the performance test task of the memory;
receiving a second IPI instruction sent by the main core processor when the waiting time arrives;
and stopping executing the performance test task of the memory.
According to a third aspect of the present application, there is provided a memory performance test apparatus applied to a master core processor of a chip, the chip having memory on the outside, the chip further including at least one slave core processor, and the apparatus comprising:
the sending module is used for sending a first inter-processor interrupt (IPI) instruction to the at least one slave core processor, wherein the first IPI instruction is used for indicating each slave core processor to start executing the performance test task of the memory;
the sending module is further configured to send a second IPI instruction to each slave core processor when the waiting time arrives, where the second IPI instruction is used to instruct each slave core processor to stop executing the performance test task of the memory;
the obtaining module is used for obtaining the memory space size occupied by the memory space of the memory tested by each slave core processor when executing the performance test task of the memory;
and the determining module is used for determining the memory performance test result of the memory according to the time difference between the transmission of the first IPI instruction and the transmission of the second IPI instruction and the memory space size occupied by the memory space of the memory tested by each slave core processor.
According to a fourth aspect of the present application, there is provided another memory performance test apparatus for use in each slave core processor of a chip, the chip having memory on its external surface, the chip further comprising a master core processor, and the apparatus comprising:
the receiving module is used for receiving a first inter-processor interrupt IPI instruction sent by the main core processor;
the task execution module is used for starting to execute the performance test task of the memory when receiving the first IPI instruction;
the receiving module is further used for receiving a second IPI instruction sent by the main core processor when the waiting time arrives;
and the task execution module is further used for stopping executing the performance test task of the memory when the second IPI instruction is received.
According to a fifth aspect of the present application, there is provided a chip comprising: the memory performance test method comprises a main core processor and at least one auxiliary core processor, wherein the memory is hung on the chip, the main core processor is used for executing the memory performance test method provided by the first aspect of the application, and each auxiliary core processor is used for executing the memory performance test method provided by the second aspect of the application.
The embodiment of the application has the beneficial effects that:
by respectively sending the first IPI instruction and the second IPI instruction to each slave core processor, the plurality of slave core processors can simultaneously and parallelly perform performance test on the memory, and performance test errors caused by time differences among different cores are avoided, so that the accuracy of performance test results of the memory is improved.
Drawings
FIG. 1 is a flow chart of a method for testing memory performance according to an embodiment of the present application;
FIG. 2 is a flow chart of another method for testing memory performance according to an embodiment of the present application;
FIG. 3 is a flowchart illustrating another method for testing memory performance according to an embodiment of the present application;
FIG. 4 is a block diagram of a memory performance testing apparatus according to an embodiment of the present application;
fig. 5 is a block diagram of another memory performance testing apparatus according to an embodiment of the present application.
Detailed Description
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples do not represent all implementations consistent with the application. Rather, they are merely examples of apparatus and methods consistent with aspects of the application as detailed in the accompanying claims.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this specification and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term "and/or" as used herein refers to and encompasses any or all possible combinations of one or more of the corresponding listed items.
It should be understood that although the terms first, second, third, etc. may be used herein to describe various information, these information should not be limited by these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the application. The word "if" as used herein may be interpreted as "at … …" or "at … …" or "responsive to a determination", depending on the context.
The method for testing the memory performance provided by the application is described in detail below.
Referring to fig. 1, fig. 1 is a flowchart of a method for testing performance of a memory, where the method is applied to a main core processor of a chip, where the chip is externally attached with a memory, and the chip further includes at least one slave core processor, and a flow of the main core processor executing the method may include the following steps:
s101, sending a first inter-processor interrupt IPI instruction to at least one slave core processor.
The first inter-processor interrupt (Inter Processor Interrupt, IPI) instruction directs each slave core processor to begin executing the performance test tasks of the memory.
In this step, since the memory performance has a very large influence on the performance of the whole computer system, the memory performance must be accurately tested in the chip design stage. For a system with better memory performance, if a test program is run on only one CPU core to test the memory performance, the measured performance data is not the best performance of the memory, but the best read-write performance of the CPU core. Therefore, in order to better and more accurately measure the performance of the memory, the application proposes that when the performance test of the memory is executed, the master core processor sends a first IPI instruction to at least one slave core processor, and by implementing the interrupt, it can ensure that all the slave core processors receive the IPI interrupt from the master core processor at the same time, thus, it can ensure that all the slave core processors immediately and simultaneously start to execute the performance test task of the memory after receiving the IPI interrupt.
It should be noted that, when only one slave processor is included in the chip, the processing procedure of the slave processor is similar to the processing procedure of the chip including a plurality of slave processors, and thus, for convenience of description, the following embodiments of the present application will be described only by taking the example that the chip includes a plurality of slave processors.
In addition, the current first timestamp may also be recorded when the first IPI instruction is sent.
It should be noted that, at least one slave processor in the present application may be one of the chips, may be a plurality of the chips, or may be all the slave processors in the chips, which may be specifically determined according to practical situations. Typically, when a plurality of slave core processors are included in a chip, a first IPI instruction is sent to all the slave core processors to obtain the best memory performance test result.
S102, judging whether the waiting time is reached, if so, executing a step S103; otherwise, the step S102 is continued.
In this step, since the slave core processor spends some time in executing the performance test task of the memory, the present application can estimate the estimated time required for executing the performance test task of the memory in advance when the master core processor, and then set a waiting time based on the required time, where the waiting time should be smaller than the estimated time required, so as to ensure that the performance test task of the memory of each slave core processor is still executing, so that the occurrence of deviation in the performance test of the memory caused by the slave core processor having completed the performance test task when the second IPI instruction is triggered can be avoided. In addition, since each slave processor starts to execute the performance test task of the memory at the same time, the application can only set one waiting time.
S103, sending a second IPI instruction to each slave core processor.
The second IPI instruction is configured to instruct each slave core processor to stop executing the performance test task of the memory.
Specifically, on the basis of ensuring that all the slave core processors start to execute the performance test tasks of the memory at the same time, it is also necessary to ensure that all the slave core processors stop executing the performance test tasks of the memory at the same time, so that all the slave core processors can be ensured to execute in absolute parallel in the whole test process. And the performance test task of stopping executing the memory simultaneously by all the slave core processors is realized by IPI interrupt. That is, after the primary core processor issues an IPI interrupt for the first time, that is, after the primary IPI instruction is sent, all the secondary core processors start to execute the performance test tasks of the memory, and after the primary core processor waits for a period of time, the primary core processor issues an IPI interrupt again, that is, sends a second IPI instruction to each secondary core processor, and at the same time, all the secondary core processors receive the second IPI interrupt at the same time, so as to ensure that all the secondary core processors stop executing the performance test tasks of the memory at the same time.
On the basis, when the waiting time arrives, the secondary core processors still execute the performance test tasks of the memory, and then a second IPI instruction is sent to each secondary core processor, and the interrupt instruction instructs each secondary core processor to suspend executing the performance test tasks of the memory. By adopting the active sending of the interrupt instruction instead of passively waiting for each slave core processor to report the end of the test, each slave core processor can be ensured to stop executing the performance test task of the memory at the same time.
Further, a second timestamp of when the second IPI instruction was sent may be recorded as the second IPI instruction was sent separately to each slave core processor.
S104, obtaining the memory space size occupied by the memory space of the tested memory when each slave core processor executes the performance test task of the memory.
Specifically, each slave processor accesses the memory space of the memory when executing the performance test task of the memory, so that the master processor can obtain the memory space size occupied by the memory space tested by each slave processor when executing the performance test task of the memory.
S105, determining a memory performance test result of the memory according to the time difference between the transmission of the first IPI instruction and the transmission of the second IPI instruction and the memory space size occupied by the memory space of the memory tested by each slave core processor.
In this step, the master core processor may determine a time difference between the two time stamps based on the recorded first time stamp and the second time stamp, and then calculate a memory performance test result of the memory based on the obtained memory space size occupied by the memory space of the memory tested by each slave core processor and the time difference.
Specifically, when determining the memory performance test result of the memory, reference may be made to the calculation method given at present, which is not limited in the present application. However, because each slave core processor is a memory performance test task executed simultaneously, the time difference is accurate, and the memory performance test result obtained by the method is accurate even if the calculation method provided at present is adopted by combining the memory space size occupied by the memory space of the memory tested by each slave core processor.
Therefore, by implementing the memory performance test method provided by the application, the performance test of the memory can be ensured to be simultaneously and parallelly performed by a plurality of slave core processors by respectively sending the first IPI instruction and the second IPI instruction to each slave core processor, so that the performance test error caused by the time difference between different cores is avoided, and the accuracy of the performance test result of the memory is improved.
Optionally, the memory performance test flow provided by the application can be run on a program (Bare-Metal, BM) test platform in a Bare Metal environment, because the test result can be more accurate compared with the OS application layer BM which is closer to the underlying hardware.
In a possible implementation manner, before implementing step S101, that is, before sending the first inter-processor interrupt IPI instruction to at least one slave core processor respectively, the present embodiment may further include the following procedure: initializing each slave core processor to send an entry address of a memory performance test program to each slave core processor, wherein the memory performance test program is a program called when the slave core processor executes a performance test task of the memory.
Specifically, in order to ensure that each slave core processor can accurately call a memory performance test program when starting to execute a performance test task of a memory, the application proposes that the master core processor maintains an interrupt vector table, and the interrupt vector table stores an entry address of the memory performance test program; then, when initializing each slave core, the entry address of the memory performance test program is initialized to each slave core processor. Thus, after each slave core processor receives the first IPI instruction, the memory performance test program can be called to execute the performance test task of the memory based on the entry address.
In a possible implementation manner, before implementing step S101, that is, before sending the first inter-processor interrupt IPI instruction to at least one slave core processor respectively, the following procedure may be performed: starting each slave core processor; and acknowledges each slave processor boot success.
Specifically, in order to ensure that each slave core processor executes the performance test task simultaneously, each slave core processor is started before the first IPI instruction is sent, and after each slave core processor in the chip is successfully started, the first IPI instruction is sent to each slave core processor, so that the slave core processors are further ensured to simultaneously start executing the performance test task of the memory.
In this embodiment, when the multi-core chip operates on the BM, the master core processor is started first, and after the master core processor is started, the interrupt vector table is initialized for all the slave core processors to indicate the entry address of the test program that needs to be operated after the slave core processor receives the IPI interrupt. The master core processor then starts all the slave core processors serially or in parallel. Each slave processor waits for the master processor to send an IPI interrupt by scheduling an instruction halt action after being ready to start. The master core processor sends the first IPI instruction after all the slave core processors are ready for starting, so that the slave core processors start running the memory performance test program at the same time when receiving the first IPI instruction regardless of the starting sequence and the starting speed of the slave core processors.
Optionally, the interrupt vector table in the present application may be stored in a memory of a chip plug-in, or may be stored in an SDRAM (synchronous dynamic random-access memory), where the SDRAM is independent of the plug-in memory, and when the interrupt vector table is stored in the memory, it is ensured that when performing performance test of the memory, the memory performance test program will not access the memory space corresponding to the interrupt vector table, that is, will not access the interrupt vector table.
Optionally, the memory performance test program is implemented in assembly language, and implementation codes of steps other than the memory performance test program can be implemented in C language, so that the memory performance test program is more convenient and easy to develop, and the accuracy of the memory performance test result is not affected.
Optionally, in one possible implementation manner, before implementing step S101, that is, before sending the first inter-processor interrupt IPI instruction to at least one slave core processor respectively, the following procedure may be further performed: applying for setting a memory space from the memory; and respectively allocating a first storage address and a second storage address for each slave core processor based on the set local range of the memory space, wherein the storage position corresponding to the first storage address allocated for each slave core processor is used for storing the initial access address of the memory space tested by the slave core processor, and the storage position corresponding to the second storage address allocated for each slave core processor is the actual access address of the memory space accessed by the slave core processor when executing the performance test task of the memory.
In this embodiment, the first memory addresses corresponding to different slave core processors are different, and the second memory addresses corresponding to different slave core processors are also different.
Specifically, for convenience of testing, before counting the memory space size of the memory space tested by each slave core processor, the master core processor applies for a set memory space from the memory, where the set memory space is dedicated to storing test related data, for example, a first memory address and a second memory address are allocated to each slave core processor, so that when the slave core processor performs a memory test task, a starting access address of the memory space tested by the slave core processor is written into a memory location corresponding to the first memory address, and then an actual access address of the memory space accessed by the slave core processor during performance test task of the memory is stored into a memory location corresponding to the second memory address, where the actual access address can be understood as a real-time access address, and dynamic changes during performance test task of the memory.
Optionally, the memory spaces tested by different slave core processors are different from each other; when each slave core processor is allocated with memory spaces which are not overlapped with each other, the memory spaces are uniformly distributed in the whole memory and are not overlapped with each other, so that the read-write performance of the memory can be guaranteed to be exerted to the maximum extent.
Further, step S104 may be implemented as follows: and determining the size of the memory space occupied by the memory space tested by each slave core processor based on a start access address and an end access address of each slave core processor when the performance test task of the memory is executed, wherein the end access address is the actual access address of the memory space accessed by the slave core processor when the performance test task of the memory is stopped.
Specifically, for each slave core processor, the master core processor performs a difference process on the end access address and the start access address stored in the set memory space by the slave core processor, so as to obtain the memory space size occupied by the memory space tested by the slave core processor. And then the main core processor is combined with the time difference of sending the IPI instruction twice, so that the memory performance test result of the memory can be calculated.
It is verified that, for the same memory, the memory writing speed (memory performance test result) measured by using mbw tool is about 23KB/s, and by adopting the method provided by the application, the accuracy of the memory performance test result is obviously improved by starting a plurality of memory writing speeds (memory performance test results) measured from the core processor to be about 71 KB/s.
Based on the same inventive concept, the application also provides a memory performance testing method, as shown in fig. 2, the method is applied to each slave core processor of a chip, the chip is externally hung with a memory, the chip also comprises a master core processor, and when each slave core processor implements the method, the method can be implemented according to the following steps:
s201, receiving a first IPI instruction sent by a main core processor.
S202, starting to execute the performance test task of the memory.
Alternatively, it may be implemented as follows: and calling the memory performance test program based on the entry address of the memory performance test program obtained from the initialization of the core processor so as to execute the performance test task of the memory.
S203, receiving a second IPI instruction sent by the main core processor when the waiting time arrives.
S204, stopping executing the performance test task of the memory.
Optionally, the memory performance testing method provided in this embodiment further includes:
storing a starting access address of the memory space tested by the slave core processor in a storage position corresponding to a first storage address allocated to the slave core processor by the master core processor;
storing an actual access address of a memory space accessed by the slave core processor when executing a performance test task of a memory in a storage position corresponding to a second storage address allocated to the slave core processor by the master core processor;
the storage position corresponding to the first storage address and the storage position corresponding to the second storage address are both contained in a set memory space of the main core processor applied from the memory.
It should be noted that, the implementation of any of the above processes may refer to the related description method in the flow shown in fig. 1, which is not specifically listed here.
By implementing the embodiment, each slave core processor can be ensured to simultaneously start and simultaneously stop executing the performance test tasks of the memory, so that the occurrence of performance test errors caused by error time differences caused by different start and stop times among different slave core processors is avoided, namely, the accuracy of the performance test results of the memory is improved.
For better understanding of the memory performance test method provided by the present application, reference may be made to the flow shown in fig. 3: taking performance test of memory by using all slave core processors in a chip as an example for explanation, starting a master core processor first; after the main core processor is started, initializing the auxiliary core processors in the chip, and informing each auxiliary core processor of the entry address of the memory performance test program; the slave core processors are then started, and each slave core processor can be started in series or in parallel; waiting for a slave core processor to boot; it should be noted that, after any slave processor completes the startup, the startup state is fed back to the master processor; the master core processor can judge whether all the slave core processors are started and completed, if so, a first IPI instruction is sent to each slave core processor at the same time, namely, a first IPI interrupt is triggered, so that each slave core processor receives the first IPI instruction at the same time, and then the memory performance test program is called by using the entry address of the memory performance test program at the same time to start testing the performance of the memory; and meanwhile, the main core processor judges whether the waiting time arrives, if the waiting time arrives, a second IPI instruction is sent to each auxiliary core processor, namely, a second IPI interrupt is triggered, so that each auxiliary core processor receives the second IPI instruction at the same time, and then, performance test tasks of the memory are stopped to be executed at the same time. In this way, the master core processor obtains the memory space size occupied by the memory space tested by each slave core processor when executing the memory performance test task, and then can determine the memory performance test result of the memory based on the time difference between sending the first IPI instruction and the second IPI instruction and the memory space size occupied by the memory space tested by each slave core processor.
Based on the same inventive concept, the application also provides a memory performance testing device corresponding to the memory performance testing method implemented by the main core processor. The implementation of the memory performance test apparatus may refer specifically to the above description of the memory performance test method implemented by the main core processor, which is not discussed herein.
Referring to fig. 4, fig. 4 is a schematic diagram of a memory performance test apparatus according to an exemplary embodiment of the present application, which is applied to a master core processor of a chip, where the chip is externally attached with a memory, and the chip further includes at least one slave core processor, and the apparatus includes:
a sending module 401, configured to send a first inter-processor interrupt IPI instruction to the at least one slave core processor, where the first IPI instruction is used to instruct each slave core processor to start executing a performance test task of the memory;
the sending module 401 is further configured to send, when the waiting time arrives, a second IPI instruction to each slave core processor, where the second IPI instruction is used to instruct each slave core processor to stop executing the performance test task of the memory;
an obtaining module 402, configured to obtain a memory space size occupied by a memory space of the memory tested by each slave core processor when performing a performance test task of the memory;
a determining module 403, configured to determine a memory performance test result of the memory according to a time difference between sending the first IPI instruction and sending the second IPI instruction and a memory space size occupied by a memory space of the memory tested by each slave core processor.
Optionally, the memory performance testing device provided by the application further includes: the initialization module 404 is also shown in fig. 4, in which:
the initialization module 404 is configured to initialize each slave processor to send an entry address of a memory performance test program to each slave processor, where the memory performance test program is a program called when the slave processor executes the performance test task of the memory.
Optionally, the memory performance testing device provided by the application further includes: referring also to fig. 4, the memory application module 405 and the address allocation module 406 are shown, in which:
the memory application module 405 is configured to apply for setting a memory space from the memory;
an address allocation module 406, configured to allocate a first storage address and a second storage address for each slave core processor based on the set local range of the memory space, where a storage location corresponding to the first storage address allocated for each slave core processor is used to store a starting access address of the memory space tested by the slave core processor, and a storage location corresponding to the second storage address allocated for each slave core processor is an actual access address of the memory space accessed by the slave core processor when executing a performance test task of the memory;
based on this, the obtaining module 402 is specifically configured to determine, based on a start access address and an end access address of each slave core processor when performing the performance test task of the memory, a memory space occupied by the memory space tested by the slave core processor, where the end access address is an actual access address of the memory space accessed by the slave core processor when stopping performing the performance test task of the memory.
Optionally, the memory performance testing device provided by the present application may further include: the start module 407 and the confirm module 408 are also shown with reference to fig. 4, wherein:
a start module 407 for starting each slave core processor;
a confirmation module 408, configured to confirm that each slave processor is successfully started.
Based on the same inventive concept, the application also provides a memory performance testing device corresponding to the memory performance testing method implemented by the slave core processor. The implementation of the memory performance test apparatus may refer specifically to the above description of the memory performance test method implemented by the slave core processor, and will not be discussed here.
Referring to fig. 5, fig. 5 is another memory performance testing apparatus according to an exemplary embodiment of the present application, which is applied to each slave processor of a chip, where the chip is externally attached with a memory, and the chip further includes a master processor, and the apparatus includes:
a receiving module 501, configured to receive a first inter-processor interrupt IPI instruction sent by a main core processor;
the task execution module 502 is configured to start executing the performance test task of the memory when receiving the first IPI instruction;
the receiving module 501 is further configured to receive a second IPI instruction sent by the main core processor when the waiting time arrives;
the task execution module 502 is further configured to stop executing the performance test task of the memory when the second IPI instruction is received.
Optionally, the task execution module 502 is specifically configured to call the memory performance test program based on an entry address of the memory performance test program obtained from the initialization of the core processor, so as to execute the performance test task of the memory.
Optionally, the memory performance testing device provided in this embodiment further includes: the storage module 503 is also shown in fig. 5, in which:
the storage module 503 is configured to store a start access address of the memory space tested by the slave core processor in a storage location corresponding to a first storage address allocated by the master core processor to the slave core processor; storing an actual access address of a memory space accessed by the slave core processor when executing a performance test task of a memory in a storage position corresponding to a second storage address allocated to the slave core processor by the master core processor;
the storage position corresponding to the first storage address and the storage position corresponding to the second storage address are both contained in a set memory space of the main core processor applied from the memory.
Based on the same inventive concept, the application also provides a chip, which comprises a main core processor and at least one auxiliary core processor, wherein the chip is externally hung with a memory, the main core processor is used for executing the memory performance test method provided by any embodiment implemented by the main core processor, and each auxiliary core processor is used for executing any one of the memory performance test methods provided by any embodiment implemented by the auxiliary core processor.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The implementation process of the functions and roles of each unit/module in the above device is specifically shown in the implementation process of the corresponding steps in the above method, and will not be repeated here.
For the device embodiments, reference is made to the description of the method embodiments for the relevant points, since they essentially correspond to the method embodiments. The above described apparatus embodiments are merely illustrative, wherein the units/modules illustrated as separate components may or may not be physically separate, and the components shown as units/modules may or may not be physical units/modules, i.e. may be located in one place, or may be distributed over a plurality of network units/modules. Some or all of the units/modules may be selected according to actual needs to achieve the purposes of the present solution. Those of ordinary skill in the art will understand and implement the present application without undue burden.
The foregoing description of the preferred embodiments of the application is not intended to be limiting, but rather to enable any modification, equivalent replacement, improvement or the like to be made within the spirit and principles of the application.
Claims (10)
1. The memory performance test method is characterized by being applied to a main core processor of a chip, wherein the chip is externally hung with a memory, the chip further comprises at least one auxiliary core processor, and the method comprises the following steps:
the main core processor sends a first inter-processor interrupt (IPI) instruction to the at least one auxiliary core processor, wherein the first IPI instruction is used for indicating each auxiliary core processor to start executing the performance test task of the memory;
when the waiting time arrives, sending a second IPI instruction to each slave core processor, wherein the second IPI instruction is used for indicating each slave core processor to stop executing the performance test task of the memory;
obtaining the memory space size occupied by the memory space of the tested memory when each slave core processor executes the performance test task of the memory;
and determining a memory performance test result of the memory according to the time difference between the transmission of the first IPI instruction and the transmission of the second IPI instruction and the memory space size occupied by the memory space of the memory tested by each slave core processor.
2. The method of claim 1, further comprising, prior to separately sending the first inter-processor interrupt IPI instruction to the at least one slave processor:
initializing each slave core processor to send an entry address of a memory performance test program to each slave core processor, wherein the memory performance test program is a program called when the slave core processor executes a performance test task of the memory.
3. The method of claim 1, further comprising, prior to separately sending the first inter-processor interrupt IPI instruction to the at least one slave processor:
applying for setting a memory space from the memory;
based on the set local range of the memory space, respectively allocating a first storage address and a second storage address for each slave core processor, wherein a storage position corresponding to the first storage address allocated for each slave core processor is used for storing a starting access address of the memory space tested by the slave core processor, and a storage position corresponding to the second storage address allocated for each slave core processor is an actual access address of the memory space accessed by the slave core processor when executing a performance test task of the memory;
obtaining the memory space size occupied by the memory space of the tested memory when each slave core processor executes the performance test task of the memory, comprising:
and determining the size of the memory space occupied by the memory space tested by each slave core processor based on a start access address and an end access address of each slave core processor when the performance test task of the memory is executed, wherein the end access address is the actual access address of the memory space accessed by the slave core processor when the performance test task of the memory is stopped.
4. The method of claim 1, further comprising, prior to separately sending the first inter-processor interrupt IPI instruction to the at least one slave processor:
starting each slave core processor; and is combined with
Each slave core processor is confirmed to start up successfully.
5. A method for testing performance of a memory, the method being applied to each slave processor of a chip, the chip having a memory on the outside, the chip further comprising a master processor, and the method comprising:
each slave core processor receives a first inter-processor interrupt IPI instruction sent by a master core processor;
starting to execute the performance test task of the memory;
receiving a second IPI instruction sent by the main core processor when the waiting time arrives;
and stopping executing the performance test task of the memory.
6. The method of claim 5, wherein starting performance testing tasks for the memory comprises:
and calling the memory performance test program based on the entry address of the memory performance test program obtained from the initialization of the core processor so as to execute the performance test task of the memory.
7. The method as recited in claim 5, further comprising:
storing a starting access address of the memory space tested by the slave core processor in a storage position corresponding to a first storage address allocated to the slave core processor by the master core processor;
storing an actual access address of a memory space accessed by the slave core processor when executing a performance test task of a memory in a storage position corresponding to a second storage address allocated to the slave core processor by the master core processor;
the storage position corresponding to the first storage address and the storage position corresponding to the second storage address are both contained in a set memory space of the main core processor applied from the memory.
8. A memory performance testing apparatus, applied to a master core processor of a chip, the chip having memory on the outside, the chip further comprising at least one slave core processor, and the apparatus comprising:
the sending module is used for sending a first inter-processor interrupt (IPI) instruction to the at least one slave core processor, wherein the first IPI instruction is used for indicating each slave core processor to start executing the performance test task of the memory;
the sending module is further configured to send a second IPI instruction to each slave core processor when the waiting time arrives, where the second IPI instruction is used to instruct each slave core processor to stop executing the performance test task of the memory;
the obtaining module is used for obtaining the memory space size occupied by the memory space of the memory tested by each slave core processor when executing the performance test task of the memory;
and the determining module is used for determining the memory performance test result of the memory according to the time difference between the transmission of the first IPI instruction and the transmission of the second IPI instruction and the memory space size occupied by the memory space of the memory tested by each slave core processor.
9. A memory performance testing apparatus for use in each slave core processor of a chip, the chip having memory on the outside, the chip further comprising a master core processor, and the apparatus comprising:
the receiving module is used for receiving a first inter-processor interrupt IPI instruction sent by the main core processor;
the task execution module is used for starting to execute the performance test task of the memory when receiving the first IPI instruction;
the receiving module is further used for receiving a second IPI instruction sent by the main core processor when the waiting time arrives;
and the task execution module is further used for stopping executing the performance test task of the memory when the second IPI instruction is received.
10. A chip, comprising: a master core processor and at least one slave core processor, wherein the chip is externally hung with a memory, the master core processor is used for executing the memory performance testing method according to any one of claims 1 to 4, and each slave core processor is used for executing the memory performance testing method according to any one of claims 5 to 7.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102681940A (en) * | 2012-05-15 | 2012-09-19 | 兰雨晴 | Method for carrying out performance test on memory management subsystem of Linux operation system |
| CN107046508A (en) * | 2016-02-05 | 2017-08-15 | 华为技术有限公司 | Message method of reseptance and the network equipment |
| WO2017215377A1 (en) * | 2016-06-16 | 2017-12-21 | 中兴通讯股份有限公司 | Method and device for processing hard memory error |
| CN111124792A (en) * | 2019-12-20 | 2020-05-08 | 北京东土科技股份有限公司 | Multi-core debugging method and device and storage medium |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9952954B2 (en) * | 2013-04-09 | 2018-04-24 | Siemens Aktiengesellschaft | Multicore processor system having an error analysis function |
| EP3103018B1 (en) * | 2014-02-28 | 2019-07-03 | Huawei Technologies Co., Ltd. | Method for debugging computer program |
-
2020
- 2020-09-25 CN CN202011022016.4A patent/CN112256502B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102681940A (en) * | 2012-05-15 | 2012-09-19 | 兰雨晴 | Method for carrying out performance test on memory management subsystem of Linux operation system |
| CN107046508A (en) * | 2016-02-05 | 2017-08-15 | 华为技术有限公司 | Message method of reseptance and the network equipment |
| WO2017215377A1 (en) * | 2016-06-16 | 2017-12-21 | 中兴通讯股份有限公司 | Method and device for processing hard memory error |
| CN111124792A (en) * | 2019-12-20 | 2020-05-08 | 北京东土科技股份有限公司 | Multi-core debugging method and device and storage medium |
Non-Patent Citations (2)
| Title |
|---|
| 基于SW26010处理器的FT程序的性能优化;陶小涵;庞建民;高伟;王琦;姚金阳;;计算机科学(04);全文 * |
| 片上多核中一种共享感知的数据主动推送Cache技术;王得利;高德远;;西安交通大学学报(10);全文 * |
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