CN113191114A - Method and apparatus for authenticating a system - Google Patents

Method and apparatus for authenticating a system Download PDF

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CN113191114A
CN113191114A CN202110489067.6A CN202110489067A CN113191114A CN 113191114 A CN113191114 A CN 113191114A CN 202110489067 A CN202110489067 A CN 202110489067A CN 113191114 A CN113191114 A CN 113191114A
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verification
verified
case
address
target memory
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CN113191114B (en
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李炎
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Beijing Baidu Netcom Science and Technology Co Ltd
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Beijing Baidu Netcom Science and Technology Co Ltd
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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
    • G06F30/39Circuit design at the physical level
    • G06F30/398Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]

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Abstract

The application discloses a method and a device for verifying a system, and relates to the technical field of system testing and chip design. The method comprises the following steps: in response to receiving a first instruction indicating to verify a system under verification, performing the following loop operations: obtaining a verification case; storing the verification case into a target memory, and sending an address of the verification case stored in the target memory to a system to be verified, wherein the address is used for enabling the system to be verified to obtain the verification case; and stopping the circulating operation in response to the fact that the data of the system to be verified for executing the verification case meets the preset conditions, and determining the state of the system to be verified according to the result obtained after the system to be verified executes the verification case. By adopting the method, the accuracy of verifying the system can be improved.

Description

Method and apparatus for authenticating a system
Technical Field
The present disclosure relates to the field of computer technologies, and in particular, to the field of system testing and chip design technologies, and in particular, to a method and an apparatus for verifying a system.
Background
After the hardware system or the software system is developed, the functions of the hardware system or the software system need to be verified. The existing method for verifying hardware system or software system function is to adopt massive directional verification use cases (namely verification use cases for verifying specified functions) to respectively verify each function of the system.
However, the existing method for verifying the system function has the problems of inaccurate verification and high maintenance cost of the verification case.
Disclosure of Invention
The present disclosure provides a method, an apparatus, an electronic device, and a computer-readable storage medium for verifying a system.
According to a first aspect, there is provided a method for authenticating a system, the method comprising: in response to receiving a first instruction indicating to verify a system under verification, performing the following loop operations: obtaining a verification case; storing the verification case into a target memory, and sending an address of the verification case stored in the target memory to a system to be verified, wherein the address is used for enabling the system to be verified to obtain the verification case; and stopping the circulating operation in response to the fact that the data of the system to be verified for executing the verification case meets the preset conditions, and determining the state of the system to be verified according to the result obtained after the system to be verified executes the verification case.
According to a second aspect, there is provided a method for authenticating a system, applied to a system to be authenticated, the method comprising: responding to the received address of the verification case in the target memory, and acquiring the verification case based on the address; and executing the verification case, and determining the state of the system to be verified according to a result obtained after the verification case is executed.
According to a third aspect, there is provided an apparatus for an authentication system, the apparatus comprising: a receiving unit configured to, in response to receiving a first instruction for instructing verification of a system to be verified, perform the following loop operation: a first acquisition unit configured to acquire a verification use case; the sending unit is configured to store the verification case into the target memory, and send the address of the verification case stored in the target memory to the system to be verified, wherein the address is used for enabling the system to be verified to obtain the verification case; and the judging unit is configured to respond to the fact that the data of the system to be verified for executing the verification case meet the preset conditions, stop the circulating operation and determine the state of the system to be verified according to the result obtained after the system to be verified executes the verification case.
According to a fourth aspect, there is provided an apparatus for authenticating a system, the apparatus being applied to a system to be authenticated, the apparatus comprising: a second obtaining unit configured to obtain, in response to receiving an address of the verification use case in the target memory, the verification use case based on the address; and the execution unit is configured to execute the verification case and determine the state of the system to be verified according to a result obtained after the verification case is executed.
According to a fifth aspect, embodiments of the present disclosure provide an electronic device, comprising: one or more processors: a storage device for storing one or more programs which, when executed by one or more processors, cause the one or more processors to implement the method for authenticating a system as provided in the first aspect, or the method for authenticating a system as provided in the second aspect.
According to a sixth aspect, embodiments of the present disclosure provide a computer readable storage medium having stored thereon a computer program, wherein the program, when executed by a processor, implements the method for authenticating a system as provided by the first aspect, or implements the method for authenticating a system as provided by the second aspect.
The method and the device for verifying the system, provided by the disclosure, respond to receiving a first instruction for indicating to verify the system to be verified, and carry out the following loop operation: obtaining a verification case; storing the verification case into a target memory, and sending an address of the verification case stored in the target memory to a system to be verified, wherein the address is used for enabling the system to be verified to obtain the verification case; and stopping the circulating operation in response to the fact that the data of the system to be verified for executing the verification case meets the preset conditions, and determining the state of the system to be verified according to the result obtained after the system to be verified executes the verification case. The accuracy of verifying the system can be improved, and the maintenance cost of the verification case can be reduced.
It should be understood that the statements in this section do not necessarily identify key or critical features of the embodiments of the present disclosure, nor do they limit the scope of the present disclosure. Other features of the present disclosure will become apparent from the following description.
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The drawings are included to provide a better understanding of the present solution and are not intended to limit the present application. Wherein:
FIG. 1 is an exemplary system architecture diagram in which embodiments of the present application may be applied;
FIG. 2 is a flow diagram of one embodiment of a method for validating a system according to the present application;
FIG. 3 is a flow diagram of another embodiment of a method for authenticating a system according to the present application;
FIG. 4 is a flow diagram of yet another embodiment of a method for validating a system according to the present application;
FIG. 5 is a flow diagram of one embodiment of a method for validating a system according to the present application;
FIG. 6 is a flow diagram of one application scenario of a method for validating a system according to the present application;
FIG. 7 is a schematic block diagram of one embodiment of an apparatus for an authentication system according to the present application;
FIG. 8 is a schematic block diagram of one embodiment of an apparatus for an authentication system according to the present application;
fig. 9 is a block diagram of an electronic device for implementing a method for authenticating a system of an embodiment of the present application.
Detailed Description
The following description of the exemplary embodiments of the present application, taken in conjunction with the accompanying drawings, includes various details of the embodiments of the application for the understanding of the same, which are to be considered exemplary only. Accordingly, those of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope and spirit of the present application. Also, descriptions of well-known functions and constructions are omitted in the following description for clarity and conciseness.
Fig. 1 illustrates an exemplary system architecture 100 to which embodiments of the present method for authenticating a system or apparatus for authenticating a system may be applied.
As shown in fig. 1, system architecture 100 may include devices 101, 102, 103, network 104, and server 105. Network 104 is the medium used to provide communication links between devices 101, 102, 103 and server 105. Network 104 may include various connection types, such as wired, wireless communication links, or fiber optic cables, to name a few.
A user may use the devices 101, 102, 103 to interact with the server 105 over the network 104 to receive or send messages or the like. Various emulation class processes or processes for testing the system may be installed on the devices 101, 102, 103. Various client applications may also be installed on the devices 101, 102, 103, such as video-type applications, play-type applications, audio-type applications, search-type applications, shopping-type applications, financial-type applications, and so forth.
The devices 101, 102, 103 may be chips, processors or hardware modules etc. to be verified/simulated. The devices 101, 102, 103 may also be various electronic devices having a display screen and supporting the reception of server messages, including but not limited to smartphones, tablet computers, e-book readers, electronic players, laptop portable computers, desktop computers, and the like.
The devices 101, 102, 103 may be hardware or software. When the devices 101, 102, 103 are hardware, they may be various hardware modules to be verified or electronic devices, and when the devices 101, 102, 103 are software, they may be installed in the electronic devices listed above. It may be implemented as multiple pieces of software or software modules (e.g., multiple software modules to provide distributed services) or as a single piece of software or software module. And is not particularly limited herein.
After the server or the verification platform receives a first instruction for instructing to verify the system to be verified, the following loop operations may be performed: the method comprises the steps of obtaining a verification case, storing the verification case into a target memory, and sending the address of the verification case stored in the target memory to a system to be verified so that the system to be verified obtains the verification case based on the address; and when the data of the system to be verified for executing the verification case meets the preset conditions, stopping the circulating operation, and determining the state of the system to be verified according to the result obtained after the system to be verified executes the verification case.
It should be noted that the method for authenticating the system provided by the embodiment of the present disclosure is generally performed by the server 105, and accordingly, the apparatus for authenticating the system is generally disposed in the server 105.
It should be understood that the number of devices, networks, and servers in fig. 1 is merely illustrative. There may be any number of devices, networks, and servers, as desired for an implementation.
With continued reference to FIG. 2, a flow 200 of one embodiment of a method for validating a system in accordance with the present disclosure is shown. A method for authenticating a system, comprising the steps of:
step 201, in response to receiving a first instruction for instructing to verify the system to be verified, a loop operation of step 2011 and step 2012 is performed.
In this embodiment, when an execution main body (for example, the server shown in fig. 1 or an authentication platform installed on the server) of the method for authenticating the system receives a first instruction for instructing the system to be authenticated to start authentication in a wired or wireless manner, the following loop operations such as step 2011 and step 2012 may be performed.
The first instruction can be an instruction for a user to authenticate a certain processor/hardware system/software system by using a request sent by the terminal equipment used by the user to the authentication platform; the first instruction may also be an instruction that is sent by the processor/hardware system/software system to be verified to the verification platform to request for verifying the processor/hardware system/software system to be verified based on the system update requirement or the system verification requirement of the processor/hardware system/software system.
Step 2011, a verification use case is obtained.
In this embodiment, the verification platform may search for a verification case from a pre-established verification case set, where the verification case set may include a plurality of directional verification cases (i.e., verification cases for verifying a specified function) and an identifier corresponding to each directional verification case, and the verification platform may randomly select one identifier to achieve the purpose of randomly selecting a verification case.
Step 2012, storing the verification case in the target memory, and sending the address where the verification case is stored in the target memory to the system to be verified, where the address is used for the system to be verified to obtain the verification case.
In this embodiment, after obtaining the verification case, the verification platform may store the verification case into the target memory, and send the address where the verification case is stored in the target memory (i.e., the location where the verification case is located in the target memory) to the system to be verified, so that the system to be verified executes the verification case after obtaining the verification case in the target memory based on the address.
The target memory can be a storage space in the system to be verified, the system to be verified can obtain a verification case by reading the storage space of the system to be verified, and the system to be verified can conveniently obtain information; the target memory can also be an external storage space in communication connection with the system to be verified, and the system to be verified obtains the verification case by reading the external storage space, so that the resources of the system to be verified can be saved.
Step 202, in response to determining that the data of the system to be verified for executing the verification use case meets the preset conditions, stopping the cycle operation, and determining the state of the system to be verified according to the result obtained after the system to be verified executes the verification use case.
In this embodiment, if it is determined that the data of the system to be verified for executing the verification case does not satisfy the preset condition, the loop operation described in step 2011 and step 2012 is continuously performed to repeatedly perform the steps of obtaining the verification case, storing the verification case, and sending the storage address of the verification case to the system to be verified and the step of executing the verification case by the system to be verified, until the data of the system to be verified for executing a plurality of verification cases satisfies the preset condition, the loop operation is stopped, and the state of the system to be verified is determined according to the result obtained after the system to be verified executes the plurality of verification cases.
The preset condition can be that the execution time of the system to be verified for executing the verification case meets the preset time; the number of the verification cases executed by the system to be verified meets the preset number, the total amount of data obtained by the system to be verified executing the verification cases meets the preset data amount, the length of the verification cases executed by the system to be verified meets the preset length, and the like.
After the system to be verified executes a plurality of verification cases, the obtained execution result can be sent to the verification platform, so that the verification platform can judge the state and performance of the verification system based on the execution result. For example, the verification platform may determine, based on data/parameters generated after the system to be verified executes the verification use case, or time for generating the data/parameters, whether a certain function of the system to be verified operates normally, whether a certain performance index reaches a target set in a system design stage, and other indexes used for representing the state/performance of the system.
The method for verifying the system provided by the embodiment performs the following loop operation in response to receiving a first instruction for instructing to verify the system to be verified: obtaining a verification case; storing the verification case into a target memory, and sending an address of the verification case stored in the target memory to a system to be verified, wherein the address is used for enabling the system to be verified to obtain the verification case; and stopping the circulating operation in response to the fact that the data of the system to be verified for executing the verification case meets the preset conditions, and determining the state of the system to be verified according to the result obtained after the system to be verified executes the verification case. Firstly, the method verifies the system to be verified through a plurality of verification cases randomly acquired by the verification platform in a plurality of rounds of circulation, so that the cross function of the system to be verified can be verified, and the comprehensiveness and accuracy of the verification system are improved.
Secondly, the cross function of the system to be verified is verified through a plurality of verification cases randomly acquired by the verification platform, instead of designing a new verification case based on the verification requirement of the cross function, the reuse of the existing verification case can be realized, and the design/maintenance cost of the verification case is reduced. Moreover, the cross function of the verification case group verification system formed by the verification cases randomly acquired by the verification platform in multiple rounds of circulation can be used for improving the randomness of the verified cross function and the accuracy of the cross function of the verification system.
And thirdly, the verification platform is adopted to send the randomly selected storage address of the verification case to the system to be verified, so that the system to be verified obtains and executes each verification case based on the storage address, and the problem of storage resource waste and communication resource waste caused by sending a large number of verification cases to the system to be verified or storing the verification cases in the system to be verified can be avoided.
Finally, in each circulation operation, the randomly selected verification case is stored to the storage address of the target memory by the verification platform and is sent to the system to be verified, so that the system to be verified acquires and executes each verification case based on the storage address each time, the unlimited use of the target memory with limited storage space can be realized, and the verification cases which can be executed by the system to be verified can be expanded infinitely.
With further reference to FIG. 3, a flow 300 of another embodiment of a method for authenticating a system is shown. The process 300 of the method for validating a system includes the steps of:
step 301, in response to receiving a first instruction for instructing to verify the system to be verified, performs a loop operation of step 3011, step 3012, and step 3013.
In this embodiment, when the execution main body of the method for authenticating a system (for example, the server shown in fig. 1 or an authentication platform installed on the server) receives a first instruction instructing the start of authentication of a system to be authenticated by a wired or wireless method, the following loop operations such as step 3011, step 3012, and step 3013 may be performed. In this embodiment, the definition of the first instruction is the same as that of the first instruction in step 201, and is not described herein again.
Step 3011, obtain a verification use case.
In this embodiment, the description of step 3011 is identical to that of step 2011, and is not repeated here.
And step 3012, randomizing data in the verification case, and generating at least one verification instruction.
In this embodiment, the verification platform may perform randomization on data in the verification case and generate at least one verification instruction. For example, the verification platform may randomize parameters of a certain functional instruction in the verification use case, or randomize the execution order of each instruction. The verification instruction may be an instruction instructing the system to perform an operation or complete a task, for example, a hardware system performs a timer starting operation, a communication system performs a sending operation on a preset data packet, a software system runs an operation of a designated program/process, and the like, so that the verification platform may evaluate, based on the execution result after the system performs the operation indicated by the verification instruction, a performance parameter of the system or whether the system can work normally.
Step 3013, store at least one verification instruction in the target memory, and send the at least one verification instruction to the starting location of the target memory, where the starting location is used for enabling the system to be verified to obtain a verification use case.
In this embodiment, the verification platform may store all or part of at least one verification instruction in the target memory, and send the start position of the at least one verification instruction stored in the target memory to the system to be verified, where the start position is used to indicate a storage unit position/storage unit identifier of a first storage unit occupied when the verification instruction is stored in the target memory, and after the system to be verified obtains the position of the first storage unit where the at least one verification instruction is stored in the target memory, the system to be verified may read, from the position, each storage unit after the first storage unit one by one, so as to obtain multiple continuously stored verification instructions one by one.
It can be understood that the verification platform and the system to be verified may agree in advance on the storage manner of the verification instruction, so that the system to be verified reads the verification instruction based on the agreement. For example, when the prearranged verification commands are stored in the memory locations in the target memory continuously, after the system to be verified obtains the initial location, the system to be verified reads the subsequent memory locations continuously from the memory location characterized by the initial location to obtain each verification command. When the prearranged verification instructions are non-continuous (the storage units with preset number of intervals between each verification instruction) are stored in the storage units in the target storage, after the system to be verified obtains the initial position, the system to be verified starts from the storage unit characterized by the initial position, and the storage units after the initial position are read at intervals to obtain each verification instruction.
Step 302, in response to determining that the data of the system to be verified executing the at least one verification instruction meets the preset condition, stopping the cycle operation, and determining the state of the system to be verified according to the result obtained after the system to be verified executes the at least one verification instruction.
In this embodiment, if it is determined that the data of at least one verification instruction executed by the system to be verified does not satisfy the preset condition, the loop operation described in step 3011, step 3012, and step 3013 is continuously performed to repeatedly perform the steps of obtaining the verification case, generating the verification instruction, and sending the storage address of the verification instruction to the system to be verified and the verification instruction executed by the system to be verified, until the data of a plurality of verification instructions executed by the system to be verified satisfy the preset condition, the loop operation is stopped, and the state of the system to be verified is determined according to the result obtained after the system to be verified executes the plurality of verification instructions.
The preset condition can be that the execution time of the system to be verified for executing the verification instruction meets the preset time; the number of the verification instructions executed by the system to be verified meets the preset number, the total amount of data obtained by the system to be verified executing the verification instructions meets the preset data amount, the length of the verification instructions executed by the system to be verified meets the preset length, and the like.
After the system to be verified executes the plurality of verification instructions, the obtained execution result can be sent to the verification platform, so that the verification platform can judge the state and performance of the verification system based on the execution result.
Compared with the method shown in fig. 2, the method for verifying the system provided in this embodiment adds a step in which the verification platform randomizes the verification case after acquiring the verification case and generates at least one verification instruction, and when the address of the verification case stored in the target memory is sent to the system to be verified, the method stores the at least one verification instruction to the start position of the target memory and sends the at least one verification instruction to the system to be verified, so that the system to be verified stores the at least one verification instruction to the start position of the target memory according to the plurality of verification instructions and acquires the plurality of verification instructions one by one. The randomness of each verification case can be improved, so that the comprehensiveness and accurate determination of the system to be verified can be further improved. In addition, only at least one verification instruction is stored to the initial position (not all addresses) of the target memory and sent to the system to be verified, so that communication and information reading and writing resources can be saved, and communication efficiency is improved.
Optionally, storing at least one validation instruction into the target memory, comprising: acquiring the storage capacity of a target memory, and acquiring the data volume of all verification instructions in at least one verification instruction; and determining a starting position for storing at least one verification instruction to the target memory according to the memory capacity of the target memory and the data volume of all the verification instructions, and storing at least one verification instruction one by one based on the starting position.
In this embodiment, the verification platform may obtain the storage amount of the target memory and the data amount of all the verification instructions in the at least one verification instruction, determine, according to the data amount of the target memory and the data amount of all the verification instructions, a starting position at which the at least one verification instruction is stored in the target memory, and store the at least one verification instruction item by item based on the starting position, that is, determine from which storage unit of the target memory the at least one verification instruction is written, so as to ensure that the last written verification instruction does not overflow the target memory.
For example, if the data size of at least one verification instruction (i.e. the storage space of the instruction memory needs to be occupied) is length, and the storage space that the target memory can provide is size, the determined starting location address addr of at least one instruction stored to the target memory needs to satisfy the condition: addr + length is less than or equal to size to ensure that data does not overflow the target memory after all the verification instructions are written into the target memory.
In this embodiment, before writing at least one verification instruction into the target memory, the size of the storage space of the target memory and the data size of all the verification instructions to be written into the target memory are obtained, and the start position for storing the at least one verification instruction is determined according to the size of the storage space and the data size, so that the integrity of the written data can be ensured.
Optionally, the method for verifying the system according to the embodiment of fig. 3 further includes: acquiring a second instruction for instructing to randomize the verification use case, and randomizing data in the verification use case, wherein the randomizing process comprises the following steps: and according to the second instruction, performing randomization processing on the data in the verification case.
In this embodiment, the verification platform may obtain a second instruction indicating to randomize the verification use case, where the second instruction may be an instruction sent by the system to be verified to the verification platform, or an instruction sent by the user to the verification platform. When randomizing the data in the verification case, the verification platform may randomize the data in the verification case based on an instruction of the second instruction. For example, if the second instruction indicates to randomize a certain function, the verification platform randomizes only the instruction for testing the function in the verification case. For another example, if the second instruction indicates the degree of randomization, the verification platform performs a corresponding level of randomization on the data in the verification case according to the degree of randomization.
In this embodiment, the verification platform randomizes the verification case according to the requirements of the user or the system to be verified, so that the pertinence of verification on the system to be verified can be improved.
With further reference to FIG. 4, a flow 400 of yet another embodiment of a method for validating a system is shown. The process 400 of the method for validating a system includes the steps of:
step 401, in response to receiving a first instruction for instructing to verify the system to be verified, performs loop operations of step 4011 and step 4012.
In this embodiment, when the execution subject of the method for authenticating a system (for example, the server shown in fig. 1 or the authentication platform installed on the server) receives a first instruction for instructing the start of authentication of the system to be authenticated by a wired or wireless method, the following loop operation of steps 4011 and 4012 may be performed. In this embodiment, the definition of the first instruction is the same as that of the first instruction in step 201, and is not described herein again.
Step 4011, obtain verification use case.
In this embodiment, the description of step 4011 is identical to that of step 2011, and is not repeated here.
Step 4012, storing the verification case into the target memory, and storing the verification case into an address of the target memory, where the address is used for enabling the system to be verified to obtain the verification case, and sending the address to the system to be verified through the preset transmission equipment.
In this embodiment, after obtaining the verification case, the verification platform may store the verification case into the target memory, and store the verification case to the address of the target memory, and send the address to the system to be verified through the preset transmission device, so that the system to be verified obtains the verification case in the target memory based on the address, and executes the verification case.
The verification platform can also store the verification instruction after randomizing the verification case to the initial position of the target memory, and send the verification instruction to the system to be verified through the preset transmission equipment, so that the system to be verified can obtain the verification instruction in the target memory based on the initial position.
The preset transmission device may be a transmission device (e.g., a virtual input output device) built in the verification platform, and the preset transmission device is used for communication between the verification platform and the system to be verified.
Step 402, in response to determining that the data of the system to be verified executing the verification use case meets the preset conditions, stopping the cycle operation, and determining the state of the system to be verified according to the result obtained after the system to be verified executes the verification use case.
Compared with the method described in fig. 2, the method for verifying the system provided by this embodiment enables the verification platform and the system to be verified to perform communication interaction through a pre-established communication mechanism, so that the stability and efficiency of transmission can be improved.
Optionally, the method for validating a system comprises: allocating a preset data transmission address to preset transmission equipment; in response to receiving the reception information or transmitting the transmission information based on the preset data transfer address, not storing the reception information or the transmission information; or, in response to receiving the receiving information based on the preset data transmission address, determining that the receiving information is information which is sent by the system to be verified and is used for requesting the system to be verified to verify.
In this embodiment, a preset data transmission address may be allocated to the preset transmission device, and if the verification platform receives information or sends information based on the preset transmission address, after the verification platform finishes processing the received information or the sent information, the verification platform does not cache/record the received information or the sent information, so as to save resources.
Or, if the verification platform receives the received information based on the preset data transmission address, the verification platform may determine that the received information is information which is sent to the verification platform by the system to be verified and is used for requesting to verify the verification system, so that the verification platform can conveniently and quickly call resources such as a related process or a component to process the information, and the information processing efficiency is improved.
In this embodiment, a preset transmission address is allocated to the preset transmission device for performing interaction between the verification platform and the system to be verified, so that when the verification platform receives or sends the information through the preset transmission address, the verification platform knows that the information is interacting with the system to be verified, and sends the verification case and/or the received information requesting verification sent by the system to be verified to the system to be verified, instead of a system log or system calculation data which needs to be archived for a long time, so that the received or sent information is not stored, and storage resources of the verification platform can be saved.
Optionally, the method for validating a system comprises: triggering a preset interrupt in a preset transmission device.
In this embodiment, before, after, or at the same time that the address storing the verification case to the target memory is sent to the system to be verified through the preset transmission device, the preset interrupt in the preset transmission device is triggered, and the state of the interrupt is identified according to the communication state between the verification platform and the system to be verified.
Specifically, a designated interrupt source may be reserved for the preset transmission device, when the verification platform needs to send the verification case to the system to be verified, the interrupt source is triggered, and a state is identified for the interrupt source according to a communication state between the verification platform and the system to be verified, where the state of the interrupt source may be, for example, a state in which the verification platform succeeds/fails to randomize data, a state in which the verification platform succeeds/fails to write data, and a state in which the verification platform has completed/has not completed sending information.
In this embodiment, a designated interrupt source is reserved for the preset transmission device, so that the interrupt source is triggered when the verification platform performs information interaction with the system to be verified, and the interrupt source is identified according to the information interaction state between the verification platform and the system to be verified, so that the verification platform or the system to be verified can suspend or restart corresponding operations at any time based on the interrupt source, and the flexibility of the system is improved.
With further reference to FIG. 5, a flow of one embodiment of a method for validating a system is shown, 500. The process 500 of the method for verifying a system, applied to a system to be verified, includes the following steps:
step 501, responding to the received address of the verification case in the target memory, and acquiring the verification case based on the address.
In this embodiment, after an execution subject (for example, the devices 101, 102, 103 shown in fig. 1, or a system to be verified) of the method for verifying the system receives an address of a verification use case in a target memory in a wired or wireless manner, the execution subject may jump to the address to obtain the verification use case. The system to be verified may be embodied as a functional module to be verified in a hardware or software system, or a verification process/test process for verifying the system.
Step 502, executing the verification case, and determining the state of the system to be verified according to the result obtained after the verification case is executed.
In this embodiment, the system to be verified may execute the verification use case acquired from the target storage, and determine the state of the system to be verified according to the result obtained after the verification use case is executed. The system to be verified can also send a result obtained after the verification case is executed to the verification platform, so that the state of the system to be verified is determined through the verification platform. The result may be data/parameters generated by the system to be verified after the verification case is executed, or time for generating the data/parameters, or the like.
After the system to be verified executes the obtained verification case, information requesting the next verification case can be sent to the verification platform, so that the verification platform can continuously send the storage address of the next verification case, and the system to be verified can continuously obtain and execute the verification case.
According to the method for verifying the system, after the system to be verified receives the address of the verification case in the target memory, the verification case is obtained based on the address, the verification case is executed, the state of the system to be verified is determined according to the result obtained after the verification case is executed, and waste of communication resources caused by the fact that the verification platform sends the verification case to the system to be verified is avoided. In addition, the system to be verified can obtain different verification cases based on the addresses sent by the verification platform for many times, and the cross function of the system to be verified can be tested by applying the mass verification cases while the mass verification cases are not required to be stored, so that the maintenance cost of the verification cases can be reduced, and the accuracy of verification results can be improved.
Optionally, in response to receiving an address of the verification use case in the target memory, acquiring the verification use case based on the address includes: and responding to the received starting position of the at least one verification instruction in the target memory, and reading the verification instructions in the at least one verification instruction one by one based on the starting position, wherein the at least one verification instruction is obtained by performing randomization processing on data in a verification case.
In this embodiment, the verification platform may randomize the verification use case and generate at least one verification instruction, and then store the at least one verification instruction to the start position of the target memory and send the at least one verification instruction to the system to be verified. After receiving the start position, the system to be verified can read the verification instructions one by one based on the start position and load the verification instructions into the local or verification process of the system to be verified so as to execute the verification instructions. After the system to be verified receives the initial position, each verification instruction can be read one by one based on the initial position, corresponding operation is executed according to the instruction of the verification instruction, the verification instruction is not loaded into the local part of the system to be verified or a verification process, and therefore local resources of the system to be verified can be saved and verification efficiency can be improved.
In some application scenarios, first, a communication mechanism between the verification platform and the to-be-verified system of the to-be-verified processor is established: and creating a virtual input/output device (virtual IO device) on the verification platform, wherein the virtual input/output device is only used for communication between the verification platform and the system to be verified. The virtual IO device is assigned reserved data sending and data receiving addresses (e.g., 0xABCD may be used as the data sending and data receiving addresses of the virtual IO device).
It is indicated in advance that in the verification process, any read-write operation based on the reserved address (such as 0xABCD) cannot be recorded by the memory model in the verification process, and any other input/output device state cannot be triggered or influenced, so that the storage or operation resources are saved.
All the information sent to the reserved address is indicated in advance, and is the information sent by the system to be verified to the verification platform (for example, the information requesting to start verification/request a verification case).
In the information that is indicated to be sent to the reserved address in advance, a preset identifier (e.g., 0xA 5A5) is used to characterize the start of sending information to the verification platform by the system to be verified, that is, the information after the preset identifier is valid request information that is sent to the verification platform by the system to be verified.
In the above process, the request information sent by the system to be verified to the verification platform may include at least one of the following: information type, information length, operation object and operation parameter. The information type is used for indicating the information which requests the verification platform to perform what operation on the verification case, such as requesting to randomize data in the verification case, requesting to reload instruction memory content, triggering a certain interrupt request of a certain input/output device, and the like; the information length is used for representing the length of the data information transmitted to the verification platform by the system to be verified; the operation object is used for representing an object verified by a verification case requested by the system to be verified, such as a register, an input/output device, a storage space and other objects related to instruction execution; the operation parameters are used for representing relevant parameters of an object verified by a verification case requested by the system to be verified, such as a register index value, register content, immediate, storage address, storage data content and the like.
And reserving a specific interrupt source for the virtual IO device in advance, and triggering the interrupt source to send an interrupt whenever the verification platform needs to send information to the system to be verified. And identifying different states for the interrupt register according to the type of information sent by the verification platform to the system to be verified, wherein the states of the interrupt register can be characterized as follows: the verification platform randomizes data success/failure, the verification platform records data success/failure, etc.
When the virtual device interrupt state indicates that the current verification platform requests to send data to the system to be verified, the system to be verified can obtain the information of the verification platform by reading the virtual IO device reserved address. The information communicated by the verification platform may include the following: information type, information length, operation object and operation parameter. The information type is used for representing information types such as instruction starting addresses and the like; the information length is used for representing the information length transmitted to the system to be verified by the verification platform; the operation object is used for representing instruction operation objects related to the transferred information, such as registers, storage space and the like; the operation parameters are used for representing register index values, register contents, immediate values, initial addresses of storage spaces and the like.
After the communication mechanism between the verification platform and the verification process is established, as shown in fig. 6, the verification process can acquire the verification case from the verification platform and execute the verification case through the following steps, so as to realize the process of verifying the function of the system to be verified:
step 601, the verification platform randomly selects a verification case from the verification case set: after the simulation/verification of a System to be verified (such as a System-on-a-Chip, SOC, System on a Chip) is started, the verification platform randomly selects a verification case from a pre-constructed verification case set. The verification case set includes each directional verification case (that is, a verification case for verifying a specified function of the SOC) and a unique identifier corresponding to the verification case.
The verification platform randomizes the acquired data in the verification case and generates a plurality of verification instructions (for example, the verification platform may randomize parameters of functional instructions in the verification case or randomize execution order of the instructions);
step 602, the verification platform writes the verification case into the target storage: and after the verification platform selects the verification case, the verification case is stored into the target memory in a back door writing mode.
Specifically, the verification platform can obtain the storage capacity of the target memory and the data volume of the plurality of verification instructions, and determine to store the plurality of verification instructions to the starting position of the target memory according to the storage capacity of the target memory and the data volume of the plurality of verification instructions, so as to ensure that the storage unit of the target memory, where the last verification instruction is stored, does not overflow the target memory. Thereafter, the verification platform stores each of the verification instructions on a per-entry basis based on the starting location.
Step 603, loading a verification case by the system to be verified: and the verification platform sends the address of the verification case in the target memory to the system to be verified through the virtual IO equipment, and the system to be verified reads the address and then takes out the verification case from the address. (wherein, the target memory can be an internal memory space and an external memory space of the system to be verified, and the address of the target memory is an entry address to which the verification process needs to jump.)
Step 604, the system to be verified executes the verification case, so as to verify the functions of the system to be verified through the data obtained after the system to be verified executes the verification case.
Step 605, after the system to be verified executes the current verification case, judging whether the simulation is finished: if the result that the system to be verified executes the verification case meets the preset condition is determined, the simulation is finished, and whether the system to be verified passes the verification or not is determined according to data obtained after the system to be verified executes the random verification case, or all performance indexes of the system to be verified are determined.
And if the result of executing the verification case by the system to be verified is determined not to meet the preset condition, sending a request for requesting to send the next verification case to the virtual IO equipment in the verification platform. The verification platform continues to request the verification platform to send the next verification case.
The result of the verification case meets the preset condition, wherein the length or the number of the verification cases meets the user requirement, and the time for executing all the verification cases meets the user requirement.
With further reference to fig. 7, as an implementation of the methods shown in the above figures, the present disclosure provides an embodiment of an apparatus for an authentication system, which corresponds to the method embodiments shown in fig. 2, 3 and 4, and which may be applied in various electronic devices in particular.
As shown in fig. 7, the apparatus 700 for an authentication system of the present embodiment includes: a receiving unit 701, a first acquiring unit 702, a transmitting unit 703, and a determining unit 704. Wherein the receiving unit is configured to, in response to receiving a first instruction for instructing verification of the system to be verified, perform the following loop operation: a first acquisition unit configured to acquire a verification use case; the sending unit is configured to store the verification case into the target memory, and send the address of the verification case stored in the target memory to the system to be verified, wherein the address is used for enabling the system to be verified to obtain the verification case; and the judging unit is configured to respond to the fact that the data of the system to be verified for executing the verification case meet the preset conditions, stop the circulating operation and determine the state of the system to be verified according to the result obtained after the system to be verified executes the verification case.
In some embodiments, a transmitting unit includes: the generating module is configured to randomize data in the verification use case and generate at least one verification instruction; a storage module configured to store at least one validation instruction into a target memory; and the sending module is configured to send the starting position of the target memory, in which at least one verification instruction is stored, to the system to be verified.
In some embodiments, a memory module, comprising: the data volume acquisition module is configured to acquire the storage volume of the target memory and acquire the data volume of all the verification instructions in at least one verification instruction; and the storage address allocation module is configured to determine a starting position for storing at least one verification instruction to the target memory according to the storage capacity of the target memory and the data volume of all the verification instructions, and store the at least one verification instruction one by one based on the starting position.
In some embodiments, the means for validating the system further comprises: a third acquisition unit configured to acquire a second instruction for instructing randomization of the verification use case; a generation module comprising: and the randomization processing module is configured to randomize the data in the verification case according to the second instruction.
In some embodiments, a transmitting unit includes: and the communication module is configured to store the verification use case to the address of the target memory and send the verification use case to the system to be verified through the preset transmission equipment.
In some embodiments, an apparatus for validating a system comprises: the address allocation module is configured to allocate a preset data transmission address to the preset transmission equipment; a first determination module configured not to store the reception information or the transmission information in response to reception of the reception information or transmission of the transmission information based on a preset data transfer address; or, the second determining module is configured to determine, in response to receiving the reception information based on the preset data transmission address, that the reception information is information that is sent by the system to be verified and is used for requesting verification of the system to be verified.
In some embodiments, the means for validating the system further comprises: an interrupt unit configured to trigger a preset interrupt in a preset transmission device.
The units in the apparatus 700 described above correspond to the steps in the method described with reference to fig. 2, 3 and 4. Thus, the operations, features and technical effects that can be achieved by the method for verifying the system described above are also applicable to the apparatus 700 and the units included therein, and are not described herein again.
With further reference to fig. 8, as an implementation of the methods shown in the above figures, the present disclosure provides an embodiment of an apparatus for an authentication system, which corresponds to the method embodiment shown in fig. 5, and which may be applied in various electronic devices.
As shown in fig. 8, the apparatus 800 for an authentication system of the present embodiment, applied to a system to be authenticated, includes: a second acquisition unit 801, an execution unit 802. The second obtaining unit is configured to respond to the received address of the verification case in the target memory and obtain the verification case based on the address; and the execution unit is configured to execute the verification case and determine the state of the system to be verified according to a result obtained after the verification case is executed.
In some embodiments, the second obtaining unit includes: the obtaining module is configured to respond to the receiving of the starting position of the at least one verification instruction in the target memory, and read the verification instructions in the at least one verification instruction one by one based on the starting position, wherein the at least one verification instruction is obtained by performing randomization processing on data in a verification case.
The units in the apparatus 800 described above correspond to the steps in the method described with reference to fig. 5. Thus, the operations, features and technical effects that can be achieved by the method for verifying the system described above are also applicable to the apparatus 800 and the units included therein, and are not described herein again.
There is also provided, in accordance with an embodiment of the present application, an electronic device, a readable storage medium, and a computer program product.
FIG. 9 illustrates a schematic block diagram of an example electronic device 900 that can be used to implement embodiments of the present application. Electronic devices are intended to represent various forms of digital computers, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. The electronic device may also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions, are meant to be examples only, and are not meant to limit implementations of the present application that are described and/or claimed herein.
As shown in fig. 9, the apparatus 900 includes a computing unit 901, which can perform various appropriate actions and processes in accordance with a computer program stored in a Read Only Memory (ROM)902 or a computer program loaded from a storage unit 908 into a Random Access Memory (RAM) 903. In the RAM903, various programs and data required for the operation of the device 900 can also be stored. The calculation unit 901, ROM 902, and RAM903 are connected to each other via a bus 904. An input/output (I/O) interface 905 is also connected to bus 904.
A number of components in the device 900 are connected to the I/O interface 905, including: an input unit 906 such as a keyboard, a mouse, and the like; an output unit 907 such as various types of displays, speakers, and the like; a storage unit 908 such as a magnetic disk, optical disk, or the like; and a communication unit 905 such as a network card, modem, wireless communication transceiver, etc. The communication unit 905 allows the device 900 to exchange information/data with other devices via a computer network, such as the internet, and/or various telecommunication networks.
The computing unit 901 may be a variety of general and/or special purpose processing components having processing and computing capabilities. Some examples of the computing unit 901 include, but are not limited to, a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), various dedicated Artificial Intelligence (AI) computing chips, various computing units running machine learning model algorithms, a Digital Signal Processor (DSP), and any suitable processor, controller, microcontroller, and so forth. The computing unit 901 performs the respective methods and processes described above, such as the method for authenticating the system. For example, in some embodiments, the method for validating the system may be implemented as a computer software program tangibly embodied in a machine-readable medium, such as storage unit 908. In some embodiments, part or all of the computer program may be loaded and/or installed onto the device 900 via the ROM 902 and/or the communication unit 905. When the computer program is loaded into the RAM903 and executed by the computing unit 901, one or more steps of the method for authenticating a system described above may be performed. Alternatively, in other embodiments, the computing unit 901 may be configured to perform the method for validating the system by any other suitable means (e.g., by means of firmware).
Various implementations of the systems and techniques described here above may be implemented in digital electronic circuitry, integrated circuitry, Field Programmable Gate Arrays (FPGAs), Application Specific Integrated Circuits (ASICs), Application Specific Standard Products (ASSPs), system on a chip (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include: implemented in one or more computer programs that are executable and/or interpretable on a programmable system including at least one programmable processor, which may be special or general purpose, receiving data and instructions from, and transmitting data and instructions to, a storage system, at least one input device, and at least one output device.
Program code for implementing the methods of the present application may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the program codes, when executed by the processor or controller, cause the functions/operations specified in the flowchart and/or block diagram to be performed. The program code may execute entirely on the machine, partly on the machine, as a stand-alone software package partly on the machine and partly on a remote machine or entirely on the remote machine or server.
In the context of this application, a machine-readable medium may be a tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
To provide for interaction with a user, the systems and techniques described here can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user; and a keyboard and a pointing device (e.g., a mouse or a trackball) by which a user can provide input to the computer. Other kinds of devices may also be used to provide for interaction with a user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form, including acoustic, speech, or tactile input.
The systems and techniques described here can be implemented in a computing system that includes a back-end component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such back-end, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local Area Networks (LANs), Wide Area Networks (WANs), and the Internet.
The computer system may include clients and servers. A client and server are generally remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other.
It should be understood that various forms of the flows shown above may be used, with steps reordered, added, or deleted. For example, the steps described in the present application may be executed in parallel, may be executed sequentially, or may be executed in different orders, as long as the desired data of the technical solution disclosed in the present application can be realized, and the present disclosure is not limited thereto.
The above-described embodiments should not be construed as limiting the scope of the present application. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions may be made in accordance with design requirements and other factors. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims (14)

1. A method for authenticating a system, comprising:
in response to receiving a first instruction indicating to verify a system under verification, performing the following loop operations:
obtaining a verification case;
storing the verification use case into a target memory, and sending an address of the verification use case stored in the target memory to a system to be verified, wherein the address is used for enabling the system to be verified to obtain the verification use case;
and stopping the circulating operation in response to the fact that the data of the system to be verified for executing the verification case meets the preset conditions, and determining the state of the system to be verified according to the result obtained after the system to be verified executes the verification case.
2. The method of claim 1, wherein the storing the verification use case in a target memory comprises:
randomizing data in the verification case, and generating at least one verification instruction;
storing the at least one validation instruction into the target memory;
the sending the address of the verification case stored in the target memory to a system to be verified comprises:
and sending the at least one verification instruction to the starting position of the target memory to be verified.
3. The method of claim 2, wherein said storing said at least one validation instruction into said target memory comprises:
acquiring the storage capacity of the target memory, and acquiring the data volume of all the verification instructions in the at least one verification instruction;
and determining a starting position for storing the at least one verification instruction to the target memory according to the storage capacity of the target memory and the data volume of all the verification instructions, and storing the at least one verification instruction one by one based on the starting position.
4. The method of claim 2, wherein the method further comprises:
obtaining a second instruction for instructing to randomize the verification use case,
the randomizing the data in the verification case includes:
and according to the second instruction, randomizing the data in the verification case.
5. The method of claim 1, wherein the sending the address of the verification use case stored to the target memory to a system to be verified comprises:
and storing the verification case to the address of the target memory, and sending the address to the system to be verified through preset transmission equipment.
6. The method of claim 5, wherein the method comprises:
distributing a preset data transmission address to the preset transmission equipment;
in response to receiving reception information or sending transmission information based on the preset data transfer address, not storing the reception information or the transmission information; alternatively, the first and second electrodes may be,
and responding to the received information based on the preset data transmission address, and determining the received information as the information which is sent by the system to be verified and is used for requesting to verify the system to be verified.
7. The method of claim 5, wherein the method further comprises:
triggering a preset interrupt in the preset transmission device.
8. A method for verifying a system is applied to a system to be verified and comprises the following steps:
responding to the received address of the verification case in the target memory, and acquiring the verification case based on the address;
and executing the verification case, and determining the state of the system to be verified according to a result obtained after the verification case is executed.
9. The method of claim 8, wherein the retrieving the verification use case based on the address in response to receiving the address in the target memory comprises:
in response to receiving a starting position of at least one verification instruction in the target memory, reading the verification instructions in the at least one verification instruction one by one based on the starting position, wherein the at least one verification instruction is obtained by randomizing data in the verification case.
10. An apparatus for authenticating a system, comprising:
a receiving unit configured to, in response to receiving a first instruction for instructing verification of a system to be verified, perform the following loop operation:
a first acquisition unit configured to acquire a verification use case;
the sending unit is configured to store the verification use case into a target memory, and send an address of the verification use case stored in the target memory to a system to be verified, wherein the address is used for enabling the system to be verified to obtain the verification use case;
and the judging unit is configured to respond to the fact that the data of the system to be verified for executing the verification case meet preset conditions, stop the circulating operation, and determine the state of the system to be verified according to a result obtained after the system to be verified executes the verification case.
11. An apparatus for authenticating a system, applied to a system to be authenticated, comprises:
a second obtaining unit configured to obtain, in response to receiving an address of a verification use case in a target memory, the verification use case based on the address;
and the execution unit is configured to execute the verification case and determine the state of the system to be verified according to a result obtained after the verification case is executed.
12. An electronic device, comprising:
at least one processor; and
a memory communicatively coupled to the at least one processor; wherein the content of the first and second substances,
the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-7 or claims 8-9.
13. A non-transitory computer readable storage medium having stored thereon computer instructions for causing the computer to perform the method of any of claims 1-7 or claims 8-9.
14. A computer program product comprising a computer program which, when executed by a processor, implements the method according to any one of claims 1-7 or claims 8-9.
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