CN111666102A - File format conversion method, chip verification method, related device and network chip - Google Patents
File format conversion method, chip verification method, related device and network chip Download PDFInfo
- Publication number
- CN111666102A CN111666102A CN202010430602.6A CN202010430602A CN111666102A CN 111666102 A CN111666102 A CN 111666102A CN 202010430602 A CN202010430602 A CN 202010430602A CN 111666102 A CN111666102 A CN 111666102A
- Authority
- CN
- China
- Prior art keywords
- data
- code
- file
- section
- program file
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/70—Software maintenance or management
- G06F8/76—Adapting program code to run in a different environment; Porting
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/362—Software debugging
- G06F11/3644—Software debugging by instrumenting at runtime
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F40/00—Handling natural language data
- G06F40/10—Text processing
- G06F40/12—Use of codes for handling textual entities
- G06F40/151—Transformation
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Software Systems (AREA)
- Computational Linguistics (AREA)
- General Health & Medical Sciences (AREA)
- Health & Medical Sciences (AREA)
- Audiology, Speech & Language Pathology (AREA)
- Artificial Intelligence (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Stored Programmes (AREA)
Abstract
The application provides a file format conversion method, a chip verification method, a related device and a network chip, wherein the file format conversion method comprises the following steps: acquiring an ELF program file of an application program, wherein the ELF format program file comprises an FMT mapping space and a common memory mapping space, and the FMT mapping space and the common memory mapping space are used for storing a data section and a code section of the application program; analyzing the ELF program file to respectively obtain the relevant information of the data section and the relevant information of the code section, wherein the relevant information of the data section comprises the following steps: the data section, the physical address of the data section and the length of the data section, and the related information of the code section comprises the code section, the physical address of the code section and the length of the code section; writing the physical address and length of the data segment into the target program file as the head and the data segment of the data segment; and writing the physical address and length of the code segment as the header of the code segment and the code segment into the target program file, thereby shortening the loading time of the application program.
Description
Technical Field
The present application relates to the field of integrated circuit technologies, and in particular, to a file format conversion method, a chip verification method, a related device, and a network chip.
Background
Since a lot of verification is needed in the chip development process, on the verification platform, due to the requirements on time and efficiency, a complete Operating System (OS) cannot be run, and a new program is needed to replace the OS as a verified software platform. BM (barrel-Metal, a platform software running in an operating system-free environment) is a solution for the industry to adopt more chip software verification platforms, and mainly can meet the verification requirements of chips due to the characteristics of refining, quick start and the like. Different functional modules are often required to be verified in the verification process of the chip, BM software is mainly responsible for initializing a hardware environment and debugging an application program to perform functional verification; different debugging application programs are loaded through one BM software for verification, so that repeated restarting of equipment can be avoided, and the verification efficiency is improved.
In the prior art, when a debugging application program is loaded, the debugging application program in the bin format is generally directly loaded. The bin file is a direct binary file with no address tags inside. The bin file internal data is arranged according to the physical space addresses of the code or data segments. When loading, the code is only copied to the corresponding memory position, and can be executed without any analysis. However before generating the bin file part of the code and data is placed in the fixed memory entry (FMT) mapping space, that is, data and code segments in the debugging application that have high performance requirements need to be placed in the space of the FMT mapping, other contents are placed in a common memory space, a compiling tool chain can fill the space without data among all the segments involved in the debugging application program with 0 when generating the bin file, this results in the space between the FMT virtual address and the normal code and data segment addresses also being filled with 0 s, and further the generated bin file becomes very large, and in the chip verification process, too large a debug application file will result in too long loading time, affecting the chip verification efficiency, if the size of the flash model is exceeded, the debugging application program cannot be used, and further the functions of the chip cannot be effectively verified.
Therefore, how to shorten the loading time of the application program and improve the verification efficiency of the chip is one of the considerable technical problems.
Disclosure of Invention
In view of the above, the present application provides a file format conversion method, a chip verification method, a related apparatus and a network chip, so as to shorten the loading time of an application program and further improve the verification efficiency of the chip.
Specifically, the method is realized through the following technical scheme:
according to a first aspect of the embodiments of the present application, there is provided a file format conversion method applied in an electronic device, the method including:
acquiring an ELF program file in an executable connection file format of an application program, wherein the ELF program file comprises a fixed memory table entry FMT mapping space and a common memory mapping space, and the FMT mapping space and the common memory mapping space are used for storing a data segment and a code segment of the application program;
analyzing the ELF program file to respectively obtain the relevant information of the data section and the relevant information of the code section, wherein the relevant information of the data section comprises: the data section, the physical address of the data section and the length of the data section, and the related information of the code section comprises the code section, the physical address of the code section and the length of the code section;
writing the physical address and the length of the data segment into a target program file as a header of the data segment and the data segment; and writing the physical address and the length of the code segment into the target program file as the head of the code segment and the code segment.
According to a second aspect of the embodiments of the present application, there is provided a chip verification method applied to a network chip, the method including:
acquiring a target program file of a debugging application program, wherein the target program file is generated according to the method provided by the first aspect of the application;
reading the data section and the code section from the target program file and copying the data section and the code section to a memory of the network chip according to the relevant information of the data section and the relevant information of the code section which are included in the target program file;
and running the debugging application program on the network chip to verify the network chip.
According to a third aspect of the embodiments of the present application, there is provided a file format conversion apparatus provided in an electronic device, the apparatus including:
the system comprises an acquisition module, a storage module and a processing module, wherein the acquisition module is used for acquiring an ELF program file in an executable connection file format of an application program, the ELF program file comprises a fixed memory table entry FMT mapping space and a common memory mapping space, and the FMT mapping space and the common memory mapping space are used for storing a data section and a code section of the application program;
an analyzing module, configured to analyze the ELF program file to obtain related information of the data segment and related information of the code segment, respectively, where the related information of the data segment includes: the data section, the physical address of the data section and the length of the data section, and the related information of the code section comprises the code section, the physical address of the code section and the length of the code section;
the file generation module is used for writing the physical address and the length of the data segment into a target program file as the head of the data segment and the data segment; and writing the physical address and the length of the code segment into the target program file as the head of the code segment and the code segment.
According to a fourth aspect of the embodiments of the present application, there is provided a chip verification apparatus, which is disposed in a network chip, the apparatus including:
an obtaining module, configured to obtain an object program file of a debugging application, where the object program file is generated according to the method provided in the first aspect of the present application;
the reading module is used for reading the data section and the code section from the target program file according to the relevant information of the data section and the relevant information of the code section which are included in the target program file;
the copying module is used for copying the read data segment and the read code segment into the internal memory of the network chip;
and the verification module is used for running the debugging application program on the network chip and verifying the network chip.
According to a fifth aspect of embodiments of the present application, there is provided an electronic device, comprising a processor and a machine-readable storage medium, the machine-readable storage medium storing a computer program capable of being executed by the processor, the processor being caused by the computer program to perform the method provided by the first aspect of embodiments of the present application.
According to a sixth aspect of embodiments of the present application, there is provided a machine-readable storage medium storing a computer program, which when invoked and executed by a processor causes the processor to perform the method provided by the first aspect of embodiments of the present application.
According to a seventh aspect of embodiments of the present application, there is provided a network chip, including a processor and a machine-readable storage medium, the machine-readable storage medium storing a computer program executable by the processor, the processor being caused by the computer program to execute the chip verification method provided by the second aspect of embodiments of the present application.
The beneficial effects of the embodiment of the application are as follows:
according to the file format forwarding method and the chip verification method provided by the embodiment of the application, the physical addresses of the data segments and the code segments in the ELF program file are written into a new target program file along with the data segments and the code segments, a bin file is not used any more, and compared with the situation that the file is too large because no data part needs to be filled with 0 among the segments of the bin file, the target program file generated by the application does not need to be filled with 0, the size of the target program file of the application is greatly reduced, so that the program loading time of the application is saved, and the verification efficiency of the chip is improved to a certain extent.
Drawings
FIG. 1a is a data structure diagram of an ELF program file according to an embodiment of the present disclosure;
FIG. 1b is a logic diagram of an FMT mapping as shown in an embodiment of the present application;
fig. 2 is a schematic structural diagram of an electronic device according to an embodiment of the present application;
FIG. 3a is a flowchart illustrating a file format conversion method according to an embodiment of the present application;
FIG. 3b is a schematic diagram illustrating file format conversion according to an embodiment of the present application;
FIG. 3c is a schematic structural diagram of a generated target program file according to an embodiment of the present application;
fig. 4a is a flowchart illustrating a chip verification method according to an embodiment of the present application;
FIG. 4b is a flowchart illustrating a start logic of a network chip start according to an embodiment of the present application;
FIG. 4c is a schematic diagram of a data or code copying process shown in an embodiment of the present application;
fig. 5 is a schematic structural diagram of a file format conversion device according to an embodiment of the present application;
fig. 6 is a schematic structural diagram of a chip verification apparatus according to an embodiment of the present application;
fig. 7 is a schematic structural diagram of a network chip according to an embodiment of the present application.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the corresponding listed items.
It is to be understood that although the terms first, second, third, etc. may be used herein to describe various information, such information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the present application. The word "if" as used herein may be interpreted as "at … …" or "when … …" or "in response to a determination", depending on the context.
For a better understanding of the present application, the technical terms referred to in the present application are explained first:
an Executable and Linkable Format (ELF) is a file Format with wide application, the definition of sections and the support of gnu tool chain make the ELF file Format very flexible, the ELF program file stores enough system related information to support cross compiling and cross linking on different platforms, and the portability is very strong. While it supports dynamically linking shared libraries in execution. The ELF program file is complex, and the data structure of the ELF program file is shown in fig. 1a, which includes the following information: the ELF header describes basic information such as a system structure, an operating system and the like, and indicates the positions of a section header table and a program header table in a file; the program header table is an ELF file from the operating point of view, mainly gives information of each segment, and is useless in the assembling and linking processes; the section header table stores all section information for viewing the ELF file from the view of compiling and linking; sections refer to the respective nodal regions; segments refer to individual segments at runtime.
The inventor finds that multi-core is the development trend of the current CPU chip, and the current mainstream CPU chip manufacturers support multi-core, heavy-core and even super-heavy-core architectures. In order to increase the running speed of the debugging application program, the multi-core processor CPU may use the FMT technology to perform address mapping, and a logic diagram of the FMT mapping is shown in fig. 1 b. The virtual address of the FMT mapping space is fixed, after the mapped physical address is configured, different CPUs can be mapped to different physical addresses when accessing the same virtual address, although the mapping relation cannot be dynamically changed and the flexibility is not high, codes and data of a debugging application program are placed in the FMT mapping space, and when a plurality of CPUs run the same debugging application program, conflicts among CPUs during memory access can be reduced, and the performance is improved.
In addition, the ELF file includes many sections and segments, which are useless during program operation, but they increase the file size, which results in longer loading time and lower chip verification efficiency in the chip verification environment; in addition, the complex file format causes the ELF file parsing process to be complex, on one hand, the size of the BM chip verification platform is increased, on the other hand, the parsing time is prolonged, and the chip verification efficiency is also reduced in a chip verification environment.
In view of this, an embodiment of the present application provides a file format conversion method, which obtains an ELF program file in an executable connection file format of an application program, where the ELF program file includes a fixed memory table entry FMT mapping space and a common memory mapping space, where the FMT mapping space and the common memory mapping space are used to store a data segment and a code segment of the application program; analyzing the ELF program file to respectively obtain the relevant information of the data section and the relevant information of the code section of the application program, wherein the relevant information of the data section comprises the following steps: the data section, the physical address of the data section and the length of the data section, and the related information of the code section comprises the code section, the physical address of the code section and the length of the code section; taking the physical address and the length of the data segment as the head of the data segment and writing the data segment into a target program file in sequence; and sequentially writing the physical address and the length of the code segment into the target program file as the head of the code segment and the code segment. In the method, only the code segment and the physical address of the data segment of the application program are analyzed from the ELF program file and written into the target program file, and compared with the bin file in the prior art, the size of the target program file is greatly reduced because 0 does not need to be filled in a data-free part, so that the loading time of loading the application program based on the target program file is effectively saved, and the verification efficiency of chip verification based on the application program is improved.
Fig. 2 is a block diagram of an electronic device 200 according to the present embodiment. The electronic device 200 includes a memory 210, a processor 220, and a communication module 230. The memory 210, the processor 220, and the communication module 230 are electrically connected to each other directly or indirectly to enable data transmission or interaction. For example, the components may be electrically connected to each other via one or more communication buses or signal lines.
The memory 210 is used for storing programs or data. The Memory 210 may be, but is not limited to, a Random Access Memory (RAM), a Double Data synchronous Dynamic Random Access Memory (DDR SDRAM), a High Bandwidth Memory (HBM), a Read Only Memory (ROM), a Programmable Read Only Memory (PROM), an Erasable Read Only Memory (EPROM), an electrically Erasable Read Only Memory (EEPROM), and the like, wherein the RAM, the DDR and the EEPROM are generally used to run programs, and the ROM, the PROM, the EPROM and the EEPROM are generally used to store Data.
The processor 220 is used to read/write data or programs stored in the memory 210 and perform corresponding functions. For example, when the computer program stored in the memory 110 is executed by the processor 120, the file format conversion method disclosed in the embodiments of the present application can be implemented.
The communication module 230 is used for establishing a communication connection between the network device 200 and another communication terminal through a network, and for transceiving data through the network. For example, the electronic device 200 may acquire an ELF program file of an application program from another communication terminal through the communication module 230.
It should be understood that the configuration shown in fig. 2 is merely a schematic configuration of the electronic device 200, and that the electronic device 200 may include more or fewer components than shown in fig. 2, or have a different configuration than shown in fig. 2. The components shown in fig. 2 may be implemented in hardware, software, or a combination thereof. Optionally, the electronic device 200 in the embodiment of the present application may be a computer or other devices, and may also be other devices, which is determined according to the actual situation.
The following describes the file format conversion method provided in the present application in detail.
Referring to fig. 3a, fig. 3a is a flowchart of a file format conversion method shown in the present application, which may include the following steps:
s301, acquiring an ELF program file in an executable connection file format of the application program.
The ELF program file comprises a fixed memory table entry FMT mapping space and a common memory mapping space, wherein the FMT mapping space and the common memory mapping space are used for storing a data section and a code section of the application program.
Optionally, the FMT mapping space includes at least one data segment and/or at least one code segment, and the common memory mapping space includes at least one data segment and/or at least one code segment. It is understood that important code segments and/or data segments in the application program are stored in the FMT mapping space, and other code segments and/or data segments are stored in the platform memory mapping space.
Specifically, when the program file of the application program is written, the program file is written according to the ELF format requirement, so that the ELF program file of the application program can be obtained.
S302, analyzing the ELF program file to respectively obtain the relevant information of the data section and the relevant information of the code section.
Specifically, please refer to the file format conversion diagram shown in fig. 3b, and fig. 3b shows a structural diagram of an ELF program file, where the ELF program file includes a program header table field, and a required data segment and a code segment can be parsed from the field.
Alternatively, when step S302 is executed, the following procedure may be implemented:
and analyzing the ELF program file to respectively obtain the relevant information of the data section of the LOAD type and the relevant information of the code section of the LOAD type.
Specifically, the code and data of the application program generally include multiple types, such as LOAD, DYNAMIC link DYNAMIC, NULL character, NOTE, and the like, and accordingly, the program header table field of the ELF program file includes fields of types of LOAD, DYNAMIC, NULL, and NOTE, and the like, so that when the ELF program file is parsed, the LOAD type is identified from the program header table field, and then the position of the code segment and the data segment of the LOAD type is determined so as to obtain the code segment and the data segment of the LOAD type, that is, only the data segment and the code segment required by the application program to be loaded into the memory of the network chip at runtime are parsed.
It should be noted that when writing the code and data of the application program into the ELF program file, the code and data are written in segment units, and one data segment is a segment and one code segment is a segment.
In addition, when each data segment or code segment is parsed, the length and the physical address of each data segment or code segment can be parsed from the ELF program file, and the physical address is used for representing the storage address of each data segment or code segment in the memory. Specifically, when the ordinary memory mapping space stores code or data, a data segment generally follows a code segment, that is, a code segment in the ordinary memory mapping space and a data segment corresponding to the code segment can be regarded as a segment, and the code segment and the data segment corresponding to the code segment share a physical address, that is, the physical address of a code segment is the same as the physical address of the data segment corresponding to the code segment. For the FMT mapping space, the code segment and the data segment are usually stored separately, and the physical address of a code segment and the physical address of the corresponding data segment of the code segment are generally different.
S303, writing the physical address and the length of the data segment into the target program file as the header and the data segment of the data segment, and writing the physical address and the length of the code segment into the target program file as the header and the code segment of the code segment.
Specifically, segments consistent with the total number of code segments and data segments in the ELF file may be configured in the target program file, and then each segment is used to store one data segment or code segment, and each segment includes a header of several bytes, for example, 8 bytes, when the target program file is written into each data segment, the physical address of the data segment and the length of the data segment are written into the header of one segment, and then the data segment is written into an area of the segment other than the header, as shown in fig. 3b, the data structure of the target program file is shown on the left side of fig. 3b, and includes a plurality of segments, for example, segment1, segment1 size, and segment1 constitute one segment, and the process of writing the related information of the data segment1 into the segment is as follows: the physical address of the data segment1 is written into segment1 in fig. 3b, the length of the data segment is written into segment1 size, and the data segment1 is written into segment1 data, thereby completing the process of writing the data segment into the target program file. When the next data segment2 is written again, the offset address of the data segment2 in the target program file can be found according to the address of the data segment1 in the target program file and the length of the data segment1, and then the physical address, the length and the data segment2 of the data segment2 are written in sequence in the segment2, the segment2 size and the segment2 data based on the offset address, and so on, so that all the data segments of the LOAD type can be written in the target program file, and the structure of the generated target program file can refer to fig. 3 c. It should be noted that the writing process of the LOAD type code segment is consistent with the writing process of the data segment, and is not described in detail here. It should be noted that, when writing the target program file, the present application does not limit the writing positions of the respective data segments and the respective code segments in the target program file.
Optionally, the target program file provided in the embodiment of the present application further includes an entry address of an operating program of the application program.
Specifically, the target program file comprises a file header, the file header comprises a plurality of bytes, and an entry address of an operating program of the application program can be stored, so that after the application program is loaded based on the target program file, the entry address can be directly read to quickly operate the operating program of the application program, and the purpose of quickly verifying the chip is further achieved.
Optionally, the target program file provided in the embodiment of the present application may further include a data segment and a total number of code segments.
Specifically, for convenience of verification, the total number of data segments and code segments written in the target program file may be written in a file header of the target program file, so that when the network chip loads the target program file, a comparison may be performed according to the total number in the file header and the actual total number, when the number is the same, it indicates that the application program may be run, and when the number is not the same, it indicates that verification fails, and it may not run the application program.
Optionally, the target program file provided in this embodiment of the present application may further include at least one of a file type identifier and a file size. Specifically, the file type identifier of the file type and the file size are both used for checking during parsing, and the file type identifier may be composed of several characters, such as 4 characters ' ″, ' B ', ' M ', and ' B '. The file size indicates the size of the entire object program file, and is also used for verifying the object program file during parsing.
It should be noted that, when the header of the target program file may be a header of 16 characters, and when the target program file includes the entry address, the total number, the file type, and the file size, the order of BMB, entry address entry, total number segment number, and file size total size may be as shown in fig. 3b or fig. 3 c.
In specific implementation, when the ELF-based program file is converted into the target program file, the conversion may be implemented through a script, specifically, the related information of the data segment and the related information of the code segment may be obtained from a program header table of the ELF program file through a readelf function under Linux, and then, after sequentially writing the physical address and length of each data segment or code segment into the header of each segment of the target program file, the target program file is obtained through conversion.
By implementing the file format conversion method provided by the application, the physical addresses of each data segment and code segment in the ELF program file are written into a new target program file along with the data segment and the code segment, and a bin file is not used any more, compared with the situation that the file is too large because no data part between the segments of the bin file needs to be filled with 0, the size of the target program file of the application program is greatly reduced because the target program file generated by the application does not need to be filled with 0, thereby saving the program loading time of the application program and improving the verification efficiency of a chip to a certain extent. And bin file does not contain any address information of data or code, must know the address of the code or data in advance while loading, the flexibility is lower, and because the physical address of code segment and data segment has been written into in the file of the object program in this application, obtain from the file of the object program directly like this, the flexibility is higher.
Based on the same inventive concept, the embodiment of the present application further provides a chip verification method, which is applied to a network chip, and when the network chip executes the chip verification method, the chip verification method can be implemented according to the flow shown in fig. 4a, and includes the following steps:
s401, obtaining a target program file of the debugging application program.
Specifically, the target program file of the debugging application program in the embodiment of the present application is generated based on the file format conversion method provided in any embodiment of the present application.
Specifically, the network chip may refer to the starting logic flowchart shown in fig. 4b when starting, when verifying the network chip, the chip verification platform based on the BM software performs verification, and the BM program code and the debugging application program code are solidified in the non-volatile memory, that is, the target program file of the debugging application program is stored in the non-volatile memory in advance.
S402, reading the data section and the code section from the target program file and copying the data section and the code section to the memory of the network chip according to the related information of the data section and the related information of the code section included in the target program file.
Specifically, since the CPU can access only the code and data in the RAM (random access memory), the program of each stage needs to copy the data and code required for the program required for the next stage from the nonvolatile memory into the RAM; in this way, after the network chip is started, a boot loader (BootLoader) in the network chip is firstly operated, and after the BootLoader copies the BM program code to the RAM, the BM software is skipped to start to operate; after the BM software finishes hardware initialization, relevant codes and data in a target program file of the debugging application program are copied to the RAM from the nonvolatile memory.
In specific implementation, when BM software loads a target program file, the header of segment1 can be found from the position offset by 16 bytes from the start address of the target program file, the header of segment2 can be found by the size of segment1, each segment header is sequentially read to find the data of the segment, and then the segment data is copied to the corresponding memory, specifically referring to the data or code copy diagram shown in fig. 4 c. When all segments in the target program file of the debugging application program are copied into the memory, the loading process of the debugging application program can be completed.
And S403, running a debugging application program on the network chip and verifying the network chip.
Specifically, after the data segment and the code segment are copied into the memory, the debugging application program can be run, and the verification of the network chip can be completed in the process of running the debugging application program. The existing chip method can be referred to in the specific verification process, which is not limited in the present application. Because the target program file of the application program is reduced, namely, only 16+ (segment quantity x 2) bytes of loading information are included, after a 500K ELF program file is converted into the target program file, the file size is 180K, the size of the application program can be effectively reduced, the loading and running time of the application program is saved, and the verification speed of a network chip is accelerated.
Based on the same inventive concept, the application also provides a file format conversion device corresponding to the file format conversion method. The implementation of the file format conversion apparatus may refer to the above description of the file format conversion method, and is not discussed here.
Referring to fig. 5, fig. 5 is a file format conversion apparatus according to an exemplary embodiment of the present application, including:
an obtaining module 501, configured to obtain an ELF program file in an executable connection file format of an application program, where the ELF program file includes a fixed memory table entry FMT mapping space and a common memory mapping space, and the FMT mapping space and the common memory mapping space are used to store a data segment and a code segment of the application program;
an analyzing module 502, configured to analyze the ELF program file to obtain related information of the data segment and related information of the code segment, respectively, where the related information of the data segment includes: the data section, the physical address of the data section and the length of the data section, and the related information of the code section comprises the code section, the physical address of the code section and the length of the code section;
a file generating module 503, configured to write the physical address and the length of the data segment into a target program file as a header of the data segment and the data segment; and writing the physical address and the length of the code segment into the target program file as the head of the code segment and the code segment.
Optionally, the parsing module 502 is specifically configured to parse the ELF program file to obtain information related to the data segment with the LOAD type and information related to the code segment with the LOAD type, respectively.
Optionally, the target program file further includes an entry address of an operating program of the application program.
Optionally, the object program file further includes a data segment and a total number of code segments.
Based on the same inventive concept, the application also provides a chip verification device corresponding to the chip verification method. The chip verification method can be specifically implemented by referring to the above description of the chip verification method, which is not discussed herein.
Referring to fig. 6, fig. 6 is a chip verification apparatus according to an exemplary embodiment of the present application, including:
an obtaining module 601, configured to obtain an object program file of a debugging application, where the object program file is generated according to a file format conversion method provided in any embodiment of the present application;
a reading module 602, configured to read a data segment and a code segment from the target program file according to relevant information of the data segment and relevant information of the code segment included in the target program file;
a copy module 603, configured to copy the read data segment and code segment into the memory of the network chip;
the verification module 604 is configured to run the debugging application on the network chip to verify the network chip.
The embodiment of the present application provides a network chip, as shown in fig. 7, including a processor 701 and a machine-readable storage medium 702, where the machine-readable storage medium 702 stores a computer program capable of being executed by the processor 701, and the processor 701 is caused by the computer program to execute the chip verification method provided in the embodiment of the present application.
The computer-readable storage medium may include a RAM (Random Access Memory) and a NVM (Non-volatile Memory), such as at least one disk Memory. Alternatively, the computer readable storage medium may be at least one memory device located remotely from the processor.
The Processor may be a general-purpose Processor, including a Central Processing Unit (CPU), a Network Processor (NP), and the like; but also a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field-Programmable Gate Array) or other Programmable logic device, discrete Gate or transistor logic device, discrete hardware component.
In addition, an embodiment of the present application provides a machine-readable storage medium, which stores a computer program, and when the computer program is called and executed by a processor, the computer program causes the processor to execute the file format forwarding method provided in any embodiment of the present application, or execute the chip verification method provided in any embodiment of the present application.
For the embodiments of the electronic device, the network chip and the machine-readable storage medium, since the contents of the related methods are substantially similar to those of the foregoing method embodiments, the description is relatively simple, and for the relevant points, reference may be made to the partial description of the method embodiments.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The implementation process of the functions and actions of each unit in the above device is specifically described in the implementation process of the corresponding step in the above method, and is not described herein again.
For the device embodiments, since they substantially correspond to the method embodiments, reference may be made to the partial description of the method embodiments for relevant points. The above-described embodiments of the apparatus are merely illustrative, and the units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the scheme of the application. One of ordinary skill in the art can understand and implement it without inventive effort.
The above description is only exemplary of the present application and should not be taken as limiting the present application, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the scope of protection of the present application.
Claims (10)
1. A file format conversion method is applied to electronic equipment, and the method comprises the following steps:
acquiring an ELF program file in an executable connection file format of an application program, wherein the ELF program file comprises a fixed memory table entry FMT mapping space and a common memory mapping space, and the FMT mapping space and the common memory mapping space are used for storing a data section and a code section of the application program;
analyzing the ELF program file to respectively obtain the relevant information of the data section and the relevant information of the code section, wherein the relevant information of the data section comprises: the data section, the physical address of the data section and the length of the data section, and the related information of the code section comprises the code section, the physical address of the code section and the length of the code section;
and writing the physical address and the length of the data section as the head of the data section and the data section into a target program file, and writing the physical address and the length of the code section as the head of the code section and the code section into the target program file.
2. The method of claim 1, wherein parsing the ELF program file to obtain information related to the data segment and information related to the code segment respectively comprises:
and analyzing the ELF program file to respectively obtain the relevant information of the data section of the LOAD type and the relevant information of the code section of the LOAD type.
3. The method of claim 1, wherein the object file further comprises an entry address of a running program of the application program.
4. The method of claim 1, wherein the target program file further comprises a total number of data segments and code segments.
5. A chip verification method is applied to a network chip, and the method comprises the following steps:
acquiring an object program file of a debugging application program, wherein the object program file is generated according to the method of any one of claims 1 to 4;
reading the data section and the code section from the target program file and copying the data section and the code section to a memory of the network chip according to the relevant information of the data section and the relevant information of the code section which are included in the target program file;
and running the debugging application program on the network chip to verify the network chip.
6. A file format conversion apparatus, provided in an electronic device, the apparatus comprising:
the system comprises an acquisition module, a storage module and a processing module, wherein the acquisition module is used for acquiring an ELF program file in an executable connection file format of an application program, the ELF program file comprises a fixed memory table entry FMT mapping space and a common memory mapping space, and the FMT mapping space and the common memory mapping space are used for storing a data section and a code section of the application program;
an analyzing module, configured to analyze the ELF program file to obtain related information of the data segment and related information of the code segment, respectively, where the related information of the data segment includes: the data section, the physical address of the data section and the length of the data section, and the related information of the code section comprises the code section, the physical address of the code section and the length of the code section;
the file generation module is used for writing the physical address and the length of the data segment into a target program file as the head of the data segment and the data segment; and writing the physical address and the length of the code segment into the target program file as the head of the code segment and the code segment.
7. The apparatus of claim 6,
the analysis module is specifically configured to analyze the ELF program file to obtain information related to the data segment with the LOAD type and information related to the code segment with the LOAD type, respectively.
8. A chip verification apparatus, disposed in a network chip, the apparatus comprising:
an obtaining module, configured to obtain an object program file of a debugging application, where the object program file is generated according to the method of any one of claims 1 to 4;
the reading module is used for reading the data section and the code section from the target program file according to the relevant information of the data section and the relevant information of the code section which are included in the target program file;
the copying module is used for copying the read data segment and the read code segment into the internal memory of the network chip;
and the verification module is used for running the debugging application program on the network chip and verifying the network chip.
9. An electronic device comprising a processor and a machine-readable storage medium storing a computer program executable by the processor, the processor being caused by the computer program to perform the file format conversion method according to any one of claims 1 to 4.
10. A network chip comprising a processor and a machine-readable storage medium storing a computer program executable by the processor, the processor being caused by the computer program to perform the chip authentication method of claim 5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010430602.6A CN111666102A (en) | 2020-05-20 | 2020-05-20 | File format conversion method, chip verification method, related device and network chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010430602.6A CN111666102A (en) | 2020-05-20 | 2020-05-20 | File format conversion method, chip verification method, related device and network chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN111666102A true CN111666102A (en) | 2020-09-15 |
Family
ID=72384024
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010430602.6A Pending CN111666102A (en) | 2020-05-20 | 2020-05-20 | File format conversion method, chip verification method, related device and network chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111666102A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112579207A (en) * | 2020-12-24 | 2021-03-30 | 深圳市优必选科技股份有限公司 | Data loading method, device and equipment |
| CN114020693A (en) * | 2021-10-19 | 2022-02-08 | 北京五八信息技术有限公司 | Header file address acquisition method and device, electronic equipment and storage medium |
-
2020
- 2020-05-20 CN CN202010430602.6A patent/CN111666102A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112579207A (en) * | 2020-12-24 | 2021-03-30 | 深圳市优必选科技股份有限公司 | Data loading method, device and equipment |
| CN112579207B (en) * | 2020-12-24 | 2023-12-15 | 深圳市优必选科技股份有限公司 | Data loading method, device and equipment |
| CN114020693A (en) * | 2021-10-19 | 2022-02-08 | 北京五八信息技术有限公司 | Header file address acquisition method and device, electronic equipment and storage medium |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107291480B (en) | Function calling method and device | |
| CN108459962B (en) | Code normalization detection method and device, terminal equipment and storage medium | |
| US8261130B2 (en) | Program code trace signature | |
| US5581697A (en) | Method and apparatus for run-time error checking using dynamic patching | |
| CN108847950B (en) | Electronic device, cloud system software automatic deployment method and storage medium | |
| US8086833B2 (en) | Method and system for linking firmware modules in a pre-memory execution environment | |
| US7743228B2 (en) | Information processing apparatus and method for obtaining software processing log | |
| CN110618903A (en) | Electronic equipment testing method and device | |
| CN109739824B (en) | Log obtaining method and device | |
| CN111666102A (en) | File format conversion method, chip verification method, related device and network chip | |
| CN111666210A (en) | Chip verification method and device | |
| CN110716845A (en) | Method for reading log information of Android system | |
| US8397217B2 (en) | Integrating templates into tests | |
| US9639451B2 (en) | Debugger system, method and computer program product for utilizing hardware breakpoints for debugging instructions | |
| US11599342B2 (en) | Pathname independent probing of binaries | |
| CN111324553A (en) | Method for realizing virtual address space on embedded system | |
| CN114428642B (en) | Random instruction generation environment based on novel processor architecture | |
| CN114047952B (en) | Processor and method for single chip microcomputer, single chip microcomputer and storage medium | |
| CN111190658B (en) | System for supporting dynamic loading of application program on SoC (system on chip) without MMU (memory management unit) based on-chip execution | |
| CN113590133A (en) | Android system injection detection method, device, equipment and computer storage medium | |
| US20130124925A1 (en) | Method and apparatus for checking a main memory of a processor | |
| CN114942779A (en) | Patch implementation method and device, embedded system and storage medium | |
| CN113742252B (en) | Method and device for detecting memory disorder | |
| CN113672260A (en) | CPU initialization method for processor | |
| US20010052114A1 (en) | Data processing apparatus |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |