CN114942779A - Patch implementation method and device, embedded system and storage medium - Google Patents
Patch implementation method and device, embedded system and storage medium Download PDFInfo
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- CN114942779A CN114942779A CN202210539897.XA CN202210539897A CN114942779A CN 114942779 A CN114942779 A CN 114942779A CN 202210539897 A CN202210539897 A CN 202210539897A CN 114942779 A CN114942779 A CN 114942779A
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Abstract
The application provides a patch implementation method, a device, an embedded system and a storage medium, when patching is needed, a patch function corresponding to a target function with a jump operation instruction arranged at a function inlet is obtained and stored, then an address in a memory variable corresponding to the target function is modified into an address pointing to the patch function, the whole process is carried out automatically, manual participation is not needed, in addition, the patch function can be skipped to by changing the address in the memory variable, the function calling semantics is not needed to be changed, and code optimization and static analysis are facilitated.
Description
Technical Field
The present application relates to the field of data processing technologies, and in particular, to a patch implementation method, an apparatus, an embedded system, and a storage medium.
Background
With the rapid development of internet technology, various software layers are endless, and when a BUG appears in the software or new functions need to be upgraded and added, the code corresponding to the software can be patched. In the existing scheme, a software developer is required to modify codes manually, and the semantics of function calling is required to be changed. If the number of points needing patching is large, the workload of software developers is large, and a new BUG is easily introduced.
Disclosure of Invention
An object of the embodiments of the present application is to provide a patch implementation method, an apparatus, an embedded system, and a storage medium, so as to solve the problems in the prior art that when a software patch is patched, the function call semantics needs to be manually changed, the workload is large, and a new BUG is easily introduced.
The embodiment of the application provides a patch implementation method, which comprises the following steps:
acquiring and storing a patch function corresponding to a target function; a jump operation instruction is arranged at a function inlet of the target function; the jump operation instruction is used for jumping to an address in a memory variable corresponding to the target function when an execution instruction aiming at the target function is received so as to execute a function corresponding to the address;
and modifying the address in the memory variable into an address pointing to the patch function.
In the implementation process, when patching is needed, the patch function corresponding to the target function with the skip operation instruction at the function entrance is obtained and stored, then the address in the memory variable corresponding to the target function is modified into the address pointing to the patch function, the whole process is carried out automatically without manual participation, in addition, the patch function can be skipped to by changing the address in the memory variable, the function calling semantics are not required to be changed, and the code optimization and the static analysis are more convenient.
Further, before the obtaining and storing the patch function corresponding to the target function, the method further includes:
acquiring a source program;
determining a function to be patched from the source program;
generating a null operation instruction at a function entrance of the function to be patched;
generating a corresponding jump operation instruction aiming at the function to be patched;
and replacing the idle operation instruction with the corresponding jump operation instruction to obtain the target function.
In the implementation process, a null operation instruction is generated at a function entrance of a function to be patched, and a storage space is reserved for subsequent modification into a skip operation instruction.
Further, the generating a no-operation instruction at a function entry of the function to be patched includes:
and in the process of compiling the source program, generating a no-operation instruction at a function entrance of the function to be patched through a compiling tool.
In the implementation process, the no-operation instruction is directly generated at the function entrance of the function to be patched through the compiling tool, and the generation mode is simple and convenient.
Further, the jump operation instruction is configured to, when an execution instruction for the target function is received, load an address in a memory variable corresponding to the target function into a temporary register, and jump to an address pointed to by the temporary register.
In the implementation process, the jump operation is implemented based on the temporary register, the address pointed by the temporary register can be jumped to, and the space range of the jump is enlarged.
Further, the function of the jump operation instruction is realized by an extension operation instruction; the extended operation instruction comprises memory variable identification information, register identification information and operation code information, and is used for: loading an address to a temporary register corresponding to the register identification information from a memory variable corresponding to a memory variable address, and jumping to an address pointed by the temporary register; the memory variable address is an address obtained by calculation according to a corresponding offset address and a preset address in a base address register, and the offset address is an address obtained by calculation according to the memory variable identification information.
In the implementation process, the function of the jump operation instruction is implemented through one expansion operation instruction, and compared with the function implemented through a plurality of operation instructions, the memory space occupied by the program can be saved, and the execution efficiency of the processor can be improved.
Further, the target function is a function preset in a read-only memory.
In the implementation process, the objective function is preset in the read-only memory, so that the system power consumption can be reduced, and the cost is reduced.
Further, the acquiring and storing a patch function corresponding to the target function includes:
and acquiring a patch function corresponding to the target function, and storing the patch function into a memory with modifiable data.
In the implementation process, the patch function is stored in the memory with the modifiable data, so that the patch function can be modified subsequently.
Further, after modifying the address in the memory variable to the address pointing to the patch function, the method further includes:
acquiring a new patch function corresponding to the target function;
storing the new patch function in the data modifiable memory;
when the starting address of the new patch function in the data modifiable storage is different from the starting address of the original patch function in the data modifiable storage, modifying the address in the memory variable to point to the address of the new patch function.
In the implementation process, the address in the memory variable is modified into the address pointing to the new patch function, so that a new patch can be printed on the target function.
Further, the storing the new patch function in the data modifiable memory includes:
when the size of the memory space occupied by the new patch function is determined to be smaller than or equal to the size of the memory space occupied by the original patch function, deleting the original patch function from the data modifiable memory, and storing the new patch function in the position of the original patch function; the starting address of the new patch function in the data modifiable memory is the same as the starting address of the original patch function in the data modifiable memory;
and when the size of the memory space occupied by the new patch function is larger than the size of the memory space occupied by the original patch function, storing the new patch function into a free space capable of accommodating the new patch function, wherein the free space is a free storage space in a memory with modifiable data.
In the implementation process, on one hand, when it is determined that the size of the memory space occupied by the new patch function is smaller than or equal to the size of the memory space occupied by the original patch function, the new patch function can be overlaid on the original patch function, so that the memory resource occupied by the program can be saved, and since the starting address of the new patch function in the data modifiable memory is the same as the starting address of the original patch function in the data modifiable memory, the address in the corresponding memory variable does not need to be modified at this time, so that the processing efficiency can be improved; on the other hand, when it is determined that the size of the memory space occupied by the new patch function is larger than the size of the memory space occupied by the original patch function, the new patch function may be stored in a free space that may otherwise accommodate the function, and then the address in the memory variable is modified to an address pointing to the new patch function.
An embodiment of the present application further provides a patch implementing apparatus, including:
the acquisition and storage module is used for acquiring and storing a patch function corresponding to the target function; the target function is a function to be complemented, wherein a jump operation instruction is arranged at a function inlet; the jump operation instruction is used for controlling jump to an address in a memory variable corresponding to the target function when the target function receives an execution instruction so as to execute a function corresponding to the address;
and the modification module is used for modifying the address in the memory variable into the current storage address of the patch function.
An embodiment of the present application further provides an embedded system, which includes a processor and a memory, where the memory stores a computer program, and the processor executes the computer program to implement any one of the above methods.
Embodiments of the present application further provide a computer-readable storage medium, which stores a computer program, and when the computer program is executed by at least one processor, the computer program implements any one of the above methods.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments of the present application will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and that those skilled in the art can also obtain other related drawings based on the drawings without inventive efforts.
Fig. 1 is a schematic flowchart of a patch implementation method according to an embodiment of the present application;
fig. 2 is a schematic flowchart of generating an objective function according to an embodiment of the present application;
FIG. 3 is a first functional layout diagram according to an embodiment of the present application;
FIG. 4 is a second functional layout diagram according to an embodiment of the present application;
FIG. 5 is a schematic diagram illustrating an instruction structure of an extended operation instruction according to an embodiment of the present disclosure;
FIG. 6 is a layout diagram of a third function provided in the first embodiment of the present application;
fig. 7 is a schematic structural diagram of a patch implementing apparatus according to a second embodiment of the present application;
fig. 8 is a schematic structural diagram of an embedded system according to a third embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the descriptions relating to "first", "second", etc. in the embodiments of the present invention are only for descriptive purposes and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the feature. In addition, technical solutions between various embodiments may be combined with each other, but must be realized by a person skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination should not be considered to exist, and is not within the protection scope of the present invention.
In the description of the present invention, it should be understood that the numerical references before the steps do not indicate the order of performing the steps, but merely serve to facilitate the description of the present invention and to distinguish each step, and thus, should not be construed as limiting the present invention.
Various embodiments will be provided below to specifically describe a patch implementation method, apparatus, embedded system, and storage medium.
The first embodiment is as follows:
in order to solve the problems that in the prior art, when software is patched, function call semantics need to be manually changed, workload is large, and a new BUG is easily introduced, an embodiment of the present application provides a patch implementation method, please refer to fig. 1. The method can be executed by an embedded system, wherein the embedded system is stored with a target function, and a jump operation instruction is arranged at a function inlet of the target function; the jump operation instruction is used for jumping to an address in the memory variable corresponding to the target function when receiving an execution instruction aiming at the target function so as to execute the function corresponding to the address.
The following describes the specific flow of the patch implementation method in detail. It should be noted that the method provided by the present invention is not limited by the specific order shown in fig. 1 and described below.
Step S11: and acquiring and storing a patch function corresponding to the target function, wherein a jump operation instruction is arranged at a function entrance of the target function.
Step S12: and modifying the address in the memory variable into an address pointing to the patch function.
It should be noted that the embedded system generally has a CPU (central processing unit), a RAM (random access memory), a ROM (read only memory), a Flash (Flash memory), and the like. The program code may be located in ROM and the data in on-chip RAM. The program code is put in ROM, and features low cost, production with IC mask, no modification of program code after IC is manufactured, and patching in case of error in manufacture or logic error of program code.
In the embodiment of the present application, in order to reduce cost and save power consumption, the objective function may be set in a rom when the integrated circuit is manufactured. Since the patch function is usually generated after the integrated circuit is manufactured, and the patch function may be modified again later, the obtained patch function may be stored in a data-modifiable memory, such as a RAM or a Flash, in step S11.
For ease of understanding, the process of generating the objective function will first be described.
Referring to fig. 2, the objective function in the embodiment of the present application may be generated before step S11 by the following steps:
step S111: a source program is acquired.
In this embodiment of the present application, a corresponding source program may be obtained for an application program, where the source program refers to a source code of the application program.
Step S112: a function to be patched is determined from a source program.
In step S112, the functions to be patched may be determined according to the actual application scenario, for example, there may be 100 or 200 functions to be patched in one source program.
Step S113: and generating a no-operation instruction at a function entrance of the function to be patched.
In step S113, a no-operation instruction may be generated at a function entry of the function to be patched by the compiling tool when the source program is compiled. For example, a NOP instruction may be generated at a function entry of a function to be patched through a compiling option patchable-function-entry in the open source compiler GNU GCC, where the NOP instruction is also a no-operation instruction, for example, when the fpatchable-function-entry is set to 3, the compiler may generate an additional and consecutive series of 3 NOP instructions at the function entry.
Step S114: and generating a corresponding jump operation instruction for the function to be patched.
Step S115: and replacing the null operation instruction with a corresponding jump operation instruction to obtain the target function.
When the linker completes the linking of the source program, the no-operation instruction can be replaced by the corresponding jump operation instruction to obtain the target function, and then the target function is stored in the read-only memory.
It is understood that the jump operation instruction in the embodiment of the present application is a function in nature, and the function may be executed by a processor in an embedded system, so as to implement a corresponding function. The jump operation instruction in the embodiment of the present application may adopt an instruction in an existing instruction set, for example, a standard instruction in an ARM instruction set, an RISCV instruction set, an MIPS instruction set, or an x86 instruction set may be directly adopted to implement a jump function.
It is understood that, in practical applications, an appropriate number of NOP instructions may be reserved at the function entry of the function to be patched according to the characteristics of the instructions to be used, where the appropriate number of NOP instructions function as placeholders, and the size of the space occupied by the NOP instructions needs to accommodate the size of the jump operation instruction in step S114.
The jump operation instruction in the embodiment of the present application may implement a jump function based on a register, that is, the jump operation instruction is used to load an address in a memory variable corresponding to a target function into a temporary register and jump to an address pointed to by the temporary register when receiving an execution instruction for the target function. Of course, in other embodiments, the jump function may be implemented based on a long jump or a short jump.
When the jump operation instruction realizes the jump function based on the register, if the instruction in the existing RISCV instruction set is adopted, 3 NOP instructions are required to be generated at the function entrance of the function to be patched. Specifically, as shown in fig. 3, fig. 3 is a function layout diagram before the completion of the link but before the instruction replacement is started, 3 functions to be patched, which are func1, func2, and func3, exist in fig. 3, and any of the 3 functions may be patched as needed. It should be noted that, the embodiment of the present application is not limited to 3 functions to be patched.
Entry1, Entry2, and Entry3 in fig. 3 respectively represent a memory variable corresponding to the target function func1, a memory variable corresponding to the target function func2, and a memory variable corresponding to the target function func3, and Entry1, Entry2, and Entry3 in fig. 3 respectively store the start addresses of the func1, func2, and func3 function bodies, instead of the start addresses of the functions func1, func2, and func 3. Where the start address of each function is equal to the start address of each function minus some fixed offset, i.e. the length occupied by consecutive NOP instructions, given that the fixed offset is N bytes, func (x) is the start address of the function func (x) which is the start address-N of the function.
After replacing the no-operation instruction with the corresponding jump-operation instruction to obtain the target function, the function layout diagram may be as shown in fig. 4, at this time, the jump-operation instruction has replaced the NOP instruction sequence. It should be noted that, in the embodiment of the present application, a corresponding memory variable needs to be preset for each function to be patched, and the memory variable is stored in a data-modifiable memory, and the size of the memory variable can be flexibly selected according to the memory resources of the system, so that each target function has a corresponding memory variable.
It can be understood that a continuous address space can be opened up in the data modifiable memory to store the memory variables corresponding to the functions to be patched, and the memory variables are stored continuously in the address space, that is, the memory variables can be stored in the manner shown in fig. 3 or fig. 4.
The temporary Register used to load the memory variable, i.e., the Register in fig. 3 and 4, may be selected from the temporary registers in the instruction set specification.
It should be noted that the function of the jump operation instruction in the embodiment of the present application may be implemented by an extended operation instruction. Referring to fig. 5, the extended operation instruction includes memory variable identification information, register identification information, and opcode information. In the embodiment of the present application, 10 bits may be allocated to the memory variable identification information, and the extended operation instruction in the embodiment of the present application is used for: loading an address to a temporary register corresponding to the register identification information from a memory variable corresponding to the memory variable address, and jumping to an address pointed by the temporary register; the memory variable address is an address calculated according to a corresponding offset address and a preset address in the base address register, and the offset address is an address calculated according to the memory variable identification information.
If the standard instruction in the 32-bit RISCV instruction set architecture is adopted to realize that the address in the corresponding memory variable is loaded to the temporary register and the jump is carried out to the address pointed by the temporary register, since the memory variable occupies 4 bytes, and the operation of loading needs to occupy a certain byte space, and each instruction in the RISCV instruction set architecture corresponds to a storage space of 4 bytes at most, 3 RISCV instructions are needed if the function of the jump operation instruction is realized by the standard instruction in the RISCV instruction set architecture, wherein two instructions of 4 bytes realize that the address in the memory variable is loaded to the temporary register, one instruction of 2 bytes realizes that the jump is carried out to the address pointed by the temporary register, so if the function of the jump operation instruction in the embodiment of the application is realized by the standard instruction in the existing instruction set architecture, the instruction takes up 10 bytes of memory space.
In the embodiment of the present application, a mode of implementing a function of a jump operation instruction by an extended operation instruction is provided, where when the extended operation instruction provided in the embodiment of the present application implements "loading an address in a corresponding memory variable to a temporary register and jumping to an address pointed to by the temporary register", since a memory variable address can be calculated by a processor through memory variable identification information and a preset address in a base address register, there is no need to carry the memory variable address in the extended instruction, and thus "loading an address in a corresponding memory variable to a temporary register and jumping to an address pointed to by the temporary register" can be implemented by a 4-byte instruction. On the one hand, the storage space is saved by the extended instruction, and on the other hand, the jump of the whole address space is realized.
It can be understood that the semantics of the extended instruction in the embodiment of the present application are as follows: and loading the value of L + P into a corresponding Register, jumping to the address indicated by the Register, wherein L represents a preset address in a base address Register JBRegister, and P represents the offset of the address of the patch function relative to the preset address. P can be calculated according to the memory variable identification information in the extended operation instruction, the size of the address space occupied by the memory variable, and the size of the address space occupied by the address stored in the memory variable. Generally, the size of the address space occupied by the memory variable is equal to the size of the address space occupied by the address stored in the memory variable, so that the offset address can be calculated by using a formula P ═ Entry ID × M-M, where Entry ID is a memory variable identifier and indicates the 1 st and 2 nd … th memory variables, M indicates the size of the address space occupied by one memory variable, and the size of the address space occupied by one address in the memory variable can also be M. For a 32-bit processor, M may take 4 bytes, for a 64-bit processor, M may take 8 bytes, and the specific value of M may be flexibly set according to the actual application scenario. The embodiment of the present application is exemplified by M equal to 4 bytes. At this time, the semantics of the extended instruction are: load the value of L + Entry ID 4-4 into the corresponding Register and jump to the address indicated by the Register.
In the embodiment of the present application, JBRegister is a writable register of a program, and may point to an address of a first memory variable, that is, an address of Entry1, according to a plan of Flash or RAM in an embedded system. Of course, in other embodiments, JBRegister may point to addresses of other memory variables, such as Entry2, Entry3, and so on. In the embodiment of the present application, the jbrelist is configured to be used in cooperation with an extended instruction, so as to implement a function of "loading an address in a corresponding memory variable to a temporary register, and jumping to an address pointed by the temporary register".
It is understood that, in order to increase the speed of reading the memory variables, the memory variables in the embodiment of the present application may be stored in the RAM.
After the target functions are generated and the configuration of the memory variables corresponding to the target functions is completed, the target functions may be patched through the steps S11 and S12.
Referring to fig. 6, it is assumed that an application has 3 target functions shown in fig. 6, and the 3 target functions are stored in the ROM, and here, the example of patching the target function func2 is described.
First, a new func2 may be obtained and stored, where the new func2 is also the patch function of the target function func2, and the new func2 is the function that has undergone the compilation linking process. In the embodiment of the application, the obtained new func2 can be stored in Flash. It should be noted that here the new func2 may be a normal function, i.e., a function without NOP instructions at the entry of the function.
Then, the address stored in the memory variable Entry2 corresponding to the target function func2 is changed to the start address of the new func2 function. The effect of this is that when the original func2 in ROM is called, i.e., the target function func2 is called, the program control flow will branch to the new func2 execution via the pointer of the Register. That is, at this point the body of function of old func2 is no longer being executed, achieving the goal of replacing old func2 with new func 2.
In practical application, when an application program needs to be patched, patch functions corresponding to a plurality of target functions of the application program may be obtained, and then each patch function is stored in a data modifiable memory, and an address in a memory variable corresponding to each target function is modified to an address pointing to the corresponding patch function. It will be appreciated that after the target function is patched as described above, the target function may also be patched newly.
In an embodiment, when a certain target function of the application program needs to be patched, all patch functions corresponding to the application program in the data modifiable memory may be removed first, and then all patch functions corresponding to the application program in the data modifiable memory may be rewritten. That is, at this time, a new patch function corresponding to the target function needs to be obtained, and also an original patch function corresponding to another target function needs to be obtained, and then the new patch function and the original patch function are rewritten into the data modifiable memory, where the another target function refers to a target function that has been patched before but does not need to be patched at this time. It is understood that the new patch function and the original patch function are compiled and linked functions. In the embodiment, all patch function packages corresponding to the target application program are rewritten as a whole, so that the storage space can be saved, and the patch reliability can be improved.
In another embodiment, when a certain target function needs to be patched, without clearing the patch function corresponding to the application program in the data modifiable memory, only the new patch function corresponding to the target function may be rewritten into the data modifiable memory, and the original patch function corresponding to the other target function may be retained in the data modifiable memory, that is, in this embodiment, it is not necessary to rewrite the original patch function corresponding to the other target function into the data modifiable memory. The function rewriting amount can be reduced, and the rewriting efficiency is improved.
Specifically, in the embodiment of the present application, after completing patching the target function, patching a new patch to the patch function, that is, after step S12, the method may further include the following steps:
acquiring a new patch function corresponding to the target function;
storing the new patch function in a data modifiable memory;
when the starting address of the new patch function in the data modifiable storage is different from the starting address of the original patch function in the data modifiable storage, the address in the memory variable corresponding to the target function is modified to be an address pointing to the new patch function.
When the size of the memory space occupied by the new patch function is determined to be smaller than or equal to the size of the memory space occupied by the original patch function, deleting the original patch function from the data modifiable memory, and storing the new patch function in the position of the original patch function; the starting address of the new patch function in the data modifiable memory is the same as the starting address of the original patch function in the data modifiable memory;
and when the size of the memory space occupied by the new patch function is determined to be larger than that occupied by the original patch function, storing the new patch function into a free space capable of accommodating the new patch function, wherein the free space is a free storage space in the data modifiable storage.
In the implementation process, on one hand, when it is determined that the size of the memory space occupied by the new patch function is smaller than or equal to the size of the memory space occupied by the original patch function, the new patch function can be overlaid on the original patch function, so that the memory resource occupied by the program can be saved, and since the starting address of the new patch function in the data modifiable memory is the same as the starting address of the original patch function in the data modifiable memory, the address in the corresponding memory variable does not need to be modified at this time, so that the processing efficiency can be improved; on the other hand, when it is determined that the size of the memory space occupied by the new patch function is larger than the size of the memory space occupied by the original patch function, the new patch function may be stored in a free space that may otherwise accommodate the function, and then the address in the memory variable is modified to an address pointing to the new patch function.
According to the patch implementation method provided by the embodiment of the application, when patching is needed, the patch function corresponding to the target function with the jump operation instruction arranged at the function inlet is obtained and stored, then the address in the memory variable corresponding to the target function is modified into the address pointing to the patch function, the whole process is automatically carried out, manual participation is not needed, in addition, the patch function can be skipped to by changing the address in the memory variable, the function call semantics is not needed to be changed, and the code optimization and static analysis are more convenient.
Example two:
an embodiment of the present application provides a patch implementation apparatus, please refer to fig. 7, including:
an obtaining and storing module 701, configured to obtain and store a patch function corresponding to the target function; the target function is a function to be complemented, wherein a jump operation instruction is arranged at a function inlet; the jump operation instruction is used for controlling jump to an address in a memory variable corresponding to the target function when the target function receives the execution instruction so as to execute a function corresponding to the address;
a modifying module 702, configured to modify an address in the memory variable to an address pointing to the patch function.
In an exemplary embodiment, the apparatus further includes an objective function generation module for obtaining a source program; determining a function to be patched from the source program; generating a null operation instruction at a function entrance of the function to be patched; generating a corresponding jump operation instruction aiming at the function to be patched; and replacing the no-operation instruction with the corresponding jump operation instruction to obtain the target function.
In an exemplary embodiment, the target function generation module is configured to generate, by a compiling tool, a no-operation instruction at a function entry of the function to be patched in the process of compiling the source program.
In an exemplary embodiment, the jump operation instruction is configured to, when an execution instruction for the target function is received, load an address in a memory variable corresponding to the target function into a temporary register, and jump to an address pointed to by the temporary register.
In an exemplary embodiment, the function of the jump operation instruction is implemented by an extended operation instruction; the extended operation instruction comprises memory variable identification information, register identification information and operation code information, and is used for: loading an address to a temporary register corresponding to the register identification information from a memory variable corresponding to a memory variable address, and jumping to an address pointed by the temporary register; the memory variable address is an address obtained by calculation according to a corresponding offset address and a preset address in a base address register, and the offset address is an address obtained by calculation according to the memory variable identification information.
In an exemplary embodiment, the objective function is a function preset in a read-only memory.
In an exemplary embodiment, the obtaining and storing module 701 is configured to obtain a patch function corresponding to the target function and store the patch function in a data modifiable memory.
In an exemplary embodiment, the obtaining storage module 701 is configured to obtain a new patch function corresponding to the target function, store the new patch function in the data modifiable storage, and modify an address in the memory variable to point to an address of the new patch function when a start address of the new patch function in the data modifiable storage is different from a start address of the original patch function in the data modifiable storage.
In an exemplary embodiment, the obtaining and storing module 701 is configured to, when it is determined that the size of the memory space occupied by the new patch function is smaller than or equal to the size of the memory space occupied by the original patch function, delete the original patch function from the data modifiable memory, and store the new patch function in the position of the original patch function; the starting address of the new patch function in the data modifiable memory is the same as the starting address of the original patch function in the data modifiable memory; and when the size of the memory space occupied by the new patch function is determined to be larger than that occupied by the original patch function, storing the new patch function into a free space capable of accommodating the new patch function, wherein the free space is a free storage space in the data modifiable storage.
In an exemplary embodiment, the obtaining and storing module 701 is configured to store a new patch function, and the modifying module 702 is configured to modify an address in the memory variable to an address pointing to the new patch function.
It should be understood that, for the sake of brevity, the contents described in some embodiments are not repeated in this embodiment.
Example three:
based on the same inventive concept, an embedded system is provided in the embodiments of the present application, please refer to fig. 8, which includes a processor 801 and a memory 802, a computer program is stored in the memory 802, and the processor 801 executes the computer program to implement the steps of the method in the first embodiment, which are not described herein again.
It will be appreciated that the architecture shown in FIG. 8 is merely illustrative, and that an embedded system may also include more or fewer components than shown in FIG. 8, or have a different configuration than shown in FIG. 8.
The processor 801 may be an integrated circuit chip having signal processing capabilities. The processor 801 may be a general-purpose processor including a CPU, an NP (network processor), and the like; but also DSPs (digital signal processors), ASICs (application specific integrated circuits), FPGAs (field programmable gate arrays) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. Which may implement or perform the various methods, steps, and logic blocks disclosed in the embodiments of the present application.
The memory 802 may include, but is not limited to, RAM (random access memory), ROM (read only memory), PROM (programmable read only memory), EPROM (erasable read only memory), EEPROM (electrically erasable read only memory), and the like.
The present embodiment further provides a computer-readable storage medium, such as a floppy disk, an optical disk, a hard disk, a flash memory, a usb (universal serial bus), an SD (secure digital) card, an MMC (multimedia data card), etc., where one or more programs for implementing the above steps are stored in the computer-readable storage medium, and the one or more programs may be executed by one or more processors to implement the steps of the method in the above embodiments, which is not described herein again.
The above-mentioned serial numbers of the embodiments of the present invention are merely for description and do not represent the merits of the embodiments.
Through the above description of the embodiments, those skilled in the art will clearly understand that the method of the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but in many cases, the former is a better implementation.
The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (12)
1. A patch implementation method, comprising:
acquiring and storing a patch function corresponding to a target function; a jump operation instruction is arranged at a function inlet of the target function; the jump operation instruction is used for jumping to an address in a memory variable corresponding to the target function when an execution instruction aiming at the target function is received so as to execute a function corresponding to the address;
and modifying the address in the memory variable into an address pointing to the patch function.
2. The patch implementation method of claim 1, wherein prior to the obtaining and storing the patch function corresponding to the target function, the method further comprises:
acquiring a source program;
determining a function to be patched from the source program;
generating a null operation instruction at a function entrance of the function to be patched;
generating a corresponding jump operation instruction aiming at the function to be patched;
and replacing the idle operation instruction with the corresponding jump operation instruction to obtain the target function.
3. The patch implementation method of claim 2, wherein the generating of the no-operation instruction at the function entry of the function to be patched comprises:
and generating a no-operation instruction at a function inlet of the function to be patched by a compiling tool in the process of compiling the source program.
4. The patch implementation method as claimed in claim 2, wherein the jump operation instruction is configured to load an address in a memory variable corresponding to the target function into a temporary register and jump to an address pointed to by the temporary register when receiving an execution instruction for the target function.
5. The patch implementation method of claim 4 wherein the function of the jump operation instruction is implemented by an extended operation instruction; the extended operation instruction comprises memory variable identification information, register identification information and operation code information, and is used for: loading an address to a temporary register corresponding to the register identification information from a memory variable corresponding to a memory variable address, and jumping to an address pointed by the temporary register; the memory variable address is an address obtained by calculation according to a corresponding offset address and a preset address in a base address register, and the offset address is an address obtained by calculation according to the memory variable identification information.
6. The patch implementation method of claim 1, wherein the objective function is a function preset in a read only memory.
7. A patch implementation method as claimed in any one of claims 1 to 6, wherein said obtaining and storing a patch function corresponding to an objective function comprises:
and acquiring a patch function corresponding to the target function, and storing the patch function into a memory with modifiable data.
8. The patch implementation method of claim 7, wherein after modifying the address in the memory variable to an address pointing to the patch function, the method further comprises:
acquiring a new patch function corresponding to the target function;
storing the new patch function in the data modifiable memory;
when the starting address of the new patch function in the data modifiable storage is different from the starting address of the original patch function in the data modifiable storage, modifying the address in the memory variable to point to the address of the new patch function.
9. The patch implementation method of claim 8 wherein said storing said new patch function in said data modifiable memory comprises:
when the size of the memory space occupied by the new patch function is determined to be smaller than or equal to the size of the memory space occupied by the original patch function, deleting the original patch function from the data modifiable memory, and storing the new patch function in the position of the original patch function; the starting address of the new patch function in the data modifiable memory is the same as the starting address of the original patch function in the data modifiable memory;
and when the size of the memory space occupied by the new patch function is determined to be larger than the size of the memory space occupied by the original patch function, storing the new patch function into a free space capable of accommodating the new patch function, wherein the free space is a free storage space in a memory with the modifiable data.
10. A patch implementation apparatus, comprising:
the acquisition and storage module is used for acquiring and storing a patch function corresponding to the target function; the target function is a function to be complemented, wherein a jump operation instruction is arranged at a function inlet; the jump operation instruction is used for controlling jump to an address in a memory variable corresponding to the target function when the target function receives an execution instruction so as to execute a function corresponding to the address;
and the modifying module is used for modifying the address in the memory variable into an address pointing to the patch function.
11. An embedded system, comprising a processor and a memory, the memory having stored therein a computer program, the processor executing the computer program to implement the method of any one of claims 1-9.
12. A computer-readable storage medium, characterized in that the computer-readable storage medium stores a computer program which, when executed by at least one processor, implements the method of any one of claims 1-9.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN115291918A (en) * | 2022-10-08 | 2022-11-04 | 紫光同芯微电子有限公司 | Code upgrading method and device for smart card, electronic equipment and storage medium |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN115291918A (en) * | 2022-10-08 | 2022-11-04 | 紫光同芯微电子有限公司 | Code upgrading method and device for smart card, electronic equipment and storage medium |
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