CN116107649A

CN116107649A - Method and system for starting D1-H application processor

Info

Publication number: CN116107649A
Application number: CN202310085505.1A
Authority: CN
Inventors: 王旭昊; 王宜怀; 李志嫒; 孟雪; 徐佳蕊; 张露; 刘肖; 李春亭
Original assignee: Suzhou University
Current assignee: Suzhou University
Priority date: 2023-02-06
Filing date: 2023-02-06
Publication date: 2023-05-12

Abstract

The application provides a method and a system for starting a D1-H application processor, wherein the method comprises the following steps: running an internal cure boot program; running SPL programs in the on-chip SDRAM; and running the application program in the DDR until the D1-H starting is completed. The 48KB from the 0 address in the D1-H chip is ROM, and the boot program BROM of the chip is solidified; after the D1-H is powered on and reset, the internal mechanism of the chip acquires a first instruction from an address 0x0, starts to run, starts to detect the state of a firmware exchange starting pin FEL, and enters a forced burning mode for downloading a program if the FEL pin is at a low level; if the FEL pin is at high level, the program SPL to be operated in the next stage is searched in which external nonvolatile memory and loaded to the address 0x20000 for operation, namely, the on-chip SDRAM. The method improves the starting speed of the D1-H chip and ensures the starting safety.

Description

Method and system for starting D1-H application processor

Technical Field

The application relates to the technical field of chips, in particular to a method and a system for starting a D1-H application processor.

Background

The D1-H application processor chip is put forward and mass-produced at present, is an application processor which is produced in quantity and is carried with the flat-headed brothers 906RISC-V in the first world, provides a new intelligent key chip for the universal interconnection AIoT era, integrates a self-grinding on-chip high-speed interconnection bus NSI and rich application interfaces, and can provide high-performance heterogeneous multi-core computing processing and excellent graphic acceleration capability. D1-H is a RISC-V architecture processor, and the product can be widely applied to a plurality of fields such as intelligent automobiles, intelligent household appliances, intelligent cities, intelligent business displays, intelligent offices and the like.

At present, the starting speed of the D1-H chip of the original version is slightly slow, and further optimization space is provided for the starting speed and the safety of the D1-H chip.

Disclosure of Invention

In view of this, the present application aims to provide a method and a system for starting a D1-H application processor, which can solve the existing problems in a targeted manner.

Based on the above objects, the present application proposes a method for starting a D1-H application processor, comprising:

running an internal cure boot program;

running SPL programs in the on-chip SDRAM;

and running the application program in the DDR until the D1-H starting is completed.

Further, the running the internal cure boot program includes:

the 48KB from the 0 address in the D1-H chip is ROM, and the boot program BROM of the chip is solidified;

after the D1-H is powered on and reset, the internal mechanism of the chip acquires a first instruction from an address 0x0, starts to run, starts to detect the state of a firmware exchange starting pin FEL, and enters a forced burning mode for downloading a program if the FEL pin is at a low level; if the FEL pin is at high level, the program SPL to be operated in the next stage is searched in which external nonvolatile memory and loaded to the address 0x20000 for operation, namely, the on-chip SDRAM.

Further, the external nonvolatile memory includes: dMMC/SD card, nand Flash, nor Flash.

Further, if the next stage is not found, the forced burning mode is entered, and the idle level of the FEL pin is high.

Further, the running SPL program in the on-chip SDRAM includes:

initializing a clock to 1GHz, initializing a serial port 0 for a program in the DDR to output debugging information by using the serial port, initializing the DDR, and copying an application program in nonvolatile storage to a 0x40000000 address in the DDR memory.

Further, the first 48 bytes of the SPL program are guide heads, wherein the checksum field is filled by a checksum tool, and the checksum tool accumulates every 4 bytes according to the bin file of the SPL program to obtain a checksum, and the initial value of the checksum field is 0x5F0A6C39; SPL code length field information is obtained through a link script;

the method for setting the guide head comprises the steps of firstly setting the guide head at the beginning of a starting file according to preset information; secondly, linking the starting file to the forefront in the linking file; finally, filling of the checksum field is completed in the Makefile using a checksum tool.

Further, the BROM checks the checksum field in the guide head, copies the SPL program with the corresponding size to the internal SDRAM of the chip according to the SPL code length field in the guide head after the checksum is passed, and then runs the SPL program.

Based on the above objects, the present application further provides a system for starting a D1-H application processor, including:

the solidification guide module is used for running an internal solidification guide program;

the SPL module is used for running the SPL program in the on-chip SDRAM;

and the application program module is used for running the application program in the DDR until the D1-H starting is completed.

Overall, the advantages of the present application and the experience brought to the user are: compared with the starting program of the D1-H chip of the original version, the method improves the starting speed of the D1-H chip and ensures the starting safety.

Drawings

In the drawings, the same reference numerals refer to the same or similar parts or elements throughout the several views unless otherwise specified. The figures are not necessarily drawn to scale. It is appreciated that these drawings depict only some embodiments according to the disclosure and are not therefore to be considered limiting of its scope.

Fig. 1 shows a flowchart of a method for starting up a D1-H application processor according to an embodiment of the present application.

FIG. 2 illustrates a D1-H interrupt response flow chart according to an embodiment of the present application.

Fig. 3 shows a configuration diagram of a startup system of a D1-H application processor according to an embodiment of the present application.

Fig. 4 shows a schematic structural diagram of an electronic device according to an embodiment of the present application.

Fig. 5 shows a schematic diagram of a storage medium according to an embodiment of the present application.

Detailed Description

The present application is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be noted that, for convenience of description, only the portions related to the present invention are shown in the drawings.

It should be noted that, in the case of no conflict, the embodiments and features in the embodiments may be combined with each other. The present application will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.

Fig. 1 shows a flowchart of a method for starting up a D1-H application processor according to an embodiment of the present application. The D1-H application processor is different from the starting flow of a general microcontroller and can be divided into three stages of running an internal curing boot program, running an SPL program in an on-chip SDRAM and running an application program in the DDR.

As shown in fig. 1, the method for starting the D1-H application processor includes:

in the first stage, an internal cure boot program is run. The 48KB from the 0 address inside the D1-H chip is ROM, and the boot program BROM of the chip is solidified. After the power-on reset of D1-H, the internal mechanism of the chip acquires a first instruction from an address 0x0 and starts to run, and the program is called a first-stage program, and has the functions of starting to detect the state of a firmware exchange starting (Fireware Exchange Launch, FEL) pin, and entering a forced burning mode for downloading the program if the FEL pin is at a low level; if the FEL pin is at high level, the program to be run in the second stage is searched in which external nonvolatile memory and loaded to the address 0x20000 for running, namely in-chip SDRAM. If the second stage is not found, the forced burning mode is also entered, and the idle level of the FEL pin is high. D1-H supports four nonvolatile memories including SPI Nor Flash, SPI Nand Flash, SD card and eMMC.

And in the second stage, running the SPL program in the on-chip SDRAM. The second-stage program (Secondary Program Loader, SPL) is not a user application program, but still needs to be implemented by the user, and is ready for the application program to run, and is responsible for initializing a clock to 1GHz, initializing a serial port 0 for the program in the DDR to output debug information using the serial port, initializing the DDR, and then copying the application program in the nonvolatile memory to the address 0x40000000 in the DDR memory.

And thirdly, running the application program in the DDR until the D1-H starting is completed. This process can be briefly represented using fig. 1.

The process of the BROM loading the SPL program from the external nonvolatile memory to the on-chip SDRAM is not controlled by the user, but the copying of the SPL program can be accomplished by properly setting the structure of the SPL program. The first 48 bytes of the SPL program are the boot head, and the detailed information is shown in table 1. The checksum field can be filled by a checksum tool, and the checksum tool accumulates every 4 bytes according to the bin file of the SPL program to obtain a checksum, wherein the initial value of the checksum field is 0x5F0A6C39; the "SPL code length" field information will be obtained by linking scripts.

The BROM checks the checksum field in the guide head, copies the SPL program with corresponding size to the internal SDRAM of the chip according to the SPL code length field in the guide head after the check is passed, and then runs the SPL program.

SPL program guide head of Table 1D1-H

The specific setting method of the guide head is that firstly, the guide head is set at the beginning of the starting file according to the information of the table 1; secondly, linking the starting file to the forefront in the linking file; finally, filling of the 'checksum' field is completed in the Makefile using a checksum tool.

As can be seen from the starting flow of D1-H, the SPL program and the application program together form the NOS software minimum system of D1-H. The SPL program is mainly responsible for the guidance of the application program, and determines whether the application program can run successfully, and the application program is the place where the user really programs, and is also the place where the system is interrupted. Three aspects of SPL programming, interrupt system set-up, and link file implementation are set forth below.

To simplify the design, the SPL program and the application program use one link file and start-up file together, and when linked, the SPL program can be seen to be absent when the user programs the DDR.

SPL programming

Since both SPL and application program are linked to DDR, and SPL program runs in on-chip SDRAM, the running address and linking address of SPL program are inconsistent, and SPL program must be Position-independent code (PIC) to run. In short, the location independent code refers to a binary code that is loaded into any memory location without affecting its operation, and can operate without relying on an absolute memory address, where all memory-related parts of the code are relative addresses. When the total principle of compiling the assembly code of the PIC is to refer to symbols in the same position-independent segment or another position-independent segment with fixed relative position, the total principle is to refer to symbols based on the PC, namely, the jump or constant access is realized by using the offset relative to the current PC; the C language code is then to take care to avoid using global and static variables, only local variables and not be able to call external libraries. The implementation of the SPL program is based on the principles described above.

1) Serial port and clock initialization

D1-H has 6 sets of UART, UART 0-UART 5 respectively, the serial port of SPL procedure initialization is UART0, and the baud rate is set to 115200. The initialization of the serial port is to initialize DDR service, and after DDR initialization, relevant debugging information is printed out through the serial port so as to judge whether DDR initialization is successful or not.

The clock is self-evident to the role of a chip, being the pulse of an embedded system. Clock initialization is to determine the system clock and bus clock and to service the clock frequency inputs required for the subsequent operation of the various modules of the system. The clock configuration of D1-H is determined by a clock control unit (Clock controller Unit, CCU) that controls the phase locked loop (Phase Locked Loop, PLL) configuration and most of the clock generation, frequency division, synchronization and gating. The initialization of the clock mainly comprises the steps of initializing the main frequency of the chip to be 1GHZ, initializing a high-performance system bus (Advanced High Performance Bus, AHB), initializing a peripheral bus (Advanced Peripheral Bus, APB) and the like.

The serial port and clock initialization are packaged separately into two independent functional functions as shown in table 2.

TABLE 2 description of serial port and clock initialization functions

2) DDR initialization

The on-chip SDRAM of D1-H is smaller, and is typically used to run SPL programs with smaller code volumes, while SPL programs copy applications with larger code volumes into DDR, where they run. H5TQ4G63EFR-RDC DDR3 is selected, and the single chip capacity is 512MB.

A closed source binary environment may be constructed, running the machine code of the DDR initialization code at the specified address using embedded machine code.

Since the SPL program code length needs to be calculated, the machine code of the DDR initialization code is stored in a specific section (section), and can be implemented by means of an attribute key in the GNU environment, which is specifically implemented as follows:

/>

where "DDR. Bin" is the segment that is opened up, this operation is the machine code array ddr_bin that will store the DDR initialization code

Stored in section ". Ddr.bin".

The DDR initialization code runs at address 0x 00030000. Thus, before initializing the DDR, the DDR initialized binary code is copied to address 0x00030000 by memcpy function, and then the DDR initialization is completed through "((void)) ((void) (0 x 00030000)) ()". Since the SPL program is implemented using location independent code, the memcpy function needs to be implemented by itself and cannot call the memcpy function in the C library.

3) Application copying and running

The selection of the external nonvolatile memory is related to the copying of the application program, and the D1-H supports four nonvolatile memories of SPI Nor Flash, SPI Nand Flash, SD card and eMMC. Compared with an SD card and an eMMC, the SPI Nor Flash and the SPI Nand Flash have the advantages of small volume and simple interface, so that the SPI Nor Flash and the PI Nand Flash can be selected as external memories of D1-H.

A copy of the application, i.e., a copy of a certain size of code from the specified address of Flash to the DDR memory at the 0x40000000 address. Because the downloading and burning of the program is to download the machine code to the zero address of Flash, in order to facilitate the copying of the application program, the SPL program and the application program are copied together into the DDR. According to the loading requirement of the application program, the programming characteristic of Flash is combined, and the functional function shown in the table 3 is designed. The method comprises the steps of determining the type of an external memory through a function spl_get_boot function; the code sizes of SPL programs and applications can be obtained by linking files.

Table 3 application copy function specification

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The running of the application may be accomplished by setting a PC pointer. Since the running environment of the chip is in the internal SDRAM and the application program is in the DDR, the PC pointer needs to add a certain offset, and the offset can be obtained by the difference between the link start address and the running start address, which is specifically implemented as follows:

wherein, "_image_start" is related to the link start address, and the value thereof is the link start address, namely, the start address 0x40000000 of the DDR; "start" is related to the running start address, i.e. the start address of the internal SDRAM of the chip 0x20000; "_main" is the application entry address.

2. Interrupt system establishment

RISC-V specifies that when a CPU is interrupted, a new program is executed from the PC address defined by the mtvec register. The program is typically an Interrupt service routine and may further jump to a more specific Interrupt service routine by querying the Interrupt field and the number field in the mcuse register. After the interrupt processing is completed, the MERT instruction is used to exit from the interrupt service routine and return to the main program. And since there is no hardware automatic save and restore context operation in the entry interrupt and exit interrupt mechanisms specified by the RISC-V architecture, software is required to explicitly use instructions for context save and restore. According to the mechanism, the specific implementation of the interrupt system of D1-H is as follows:

the vector function is the total entry address of the interrupt service routine, and the purpose of four-byte alignment is to set the MODE field of the mtvec register to 0, i.e. the address indicated by the BASE field of the mtvec register is jumped to by the CPU in response to all interrupts; the context refers to the CPU internal registers, namely 31 general registers x 1-x 31; the handle_trap function determines the type of interrupt by reading the value of the mcuse register, thereby entering different interrupt service routines.

Thus, the interrupt service routine corresponding to each interrupt and exception needs to be implemented by the user, and is called in the handle_trap function, and default is infinite loop. For external interrupts, i.e. interrupts generated by external devices such as uart and gpio, it is further necessary to determine what external device is caused to jump to the corresponding interrupt service routine. The machine mode, the user mode and the management mode all have corresponding external interrupts, and in a default, any interrupt occurring in any mode is switched to the machine mode to respond, so that the machine mode external interrupt is mainly aimed at.

d1-H implements a platform level interrupt controller (Platform Level Interrupt Controller, PLIC) for priority arbitration and dispatch of multiple external interrupt sources, the number and information of which can be viewed by reading the PLIC's associated registers. After knowing the number of the interrupt source, a corresponding interrupt service routine is called according to the interrupt source number, and the specific implementation is as follows:

the design of an interrupt vector table similar to vector interrupt is that interrupt service routines are placed into a global array one by one according to the sequence of interrupt numbers in the form of function pointers, such as irqTable, and when a certain external interrupt occurs, a program can call the corresponding interrupt service routine in the irqTable according to the interrupt numbers. The default interrupt service routine is endless loop, and when actually programmed, the user needs to complete the registration of the external interrupt service routine by himself, i.e. replace the default external interrupt processing routine. The interrupt system of D1-H has been initially established, but if an external interrupt is to be triggered successfully, the initialization of PLIC will also need to be completed. RISC-V specifies that the interrupt source priority must be above the interrupt target threshold and greater than 0, otherwise no final interrupt notification is generated. Thus PLIC initialization mainly sets the priority and threshold of each interrupt source, defaults to all interrupt sources with priority 1 and threshold 0. Based on the above analysis, the processing associated with external interrupts is packaged into independent functional functions, following the componentization concept, as shown in table 4.

TABLE 4 external interrupt related function specification

According to the established D1-H interrupt system, when the interrupt occurs, the response flow is shown in figure 2.

3. Implementation of link files

The link file defines how the segments in the input intermediate file are mapped into the final destination file and controls the allocation of addresses for the parts in the destination file. The mapping of the segments in the intermediate file input through the commands such as MEMORY and SECTINONS to the final target file and the address allocation of each part in the target file generally comprises the following segments:

(1) text section. For saving the program code.

(2) A data section. Typically for storing global and static variables that are initialized to other than 0.

(3) And a bss segment. Typically for storing global and static variables initialized to 0 or uninitialized.

(4) A heel section. The method is used for dynamically distributing the memory, the size of which is not fixed, and can be dynamically expanded or reduced. Typically assigned and released by a programmer.

(5) statck segment. The compiler automatically allocates and releases, stores parameter values, local variables and the like of the functions.

The design of the link file is completed according to the composition and grammar of the link file, and part of the contents are shown in the following codes.

The following description will be made for this link file:

(1) The start of the link file designates the output executable file as a 64-bit RISC-V instruction, the small end format, the platform of the output executable file as RISC-V, the entry address of the program as start, and the stack size as 61440 bytes. Wherein the stack size user can set itself within the RAM size range.

(2) The start address of the link is 0x40000000 and the area size is 512MB.

(3) Since the text section contains two code parts of the SPL program and the application program, in order to calculate the code size of the SPL program, it is necessary to explicitly indicate in the text section which files belong to the SPL program, that is, obj/start.o (text x), obj/mymemcpy.o (text x) in the above code, and so on. Meanwhile, in order to ensure the correctness of the position of the guide header information, the start file should be linked to the forefront.

(4) The program code size is obtained by adding a "tag" to the link file. The label is similar to a variable in the C language, can be used for recording the address of the current description position in a link file, for example, the size of SPL program codes is calculated, two labels of __ spl_start and __ spl_end are defined, the starting address and the ending address of the SPL program are respectively recorded, and the difference between the starting address and the ending address is the code size of the SPL program.

An embodiment of the present application provides a system for starting a D1-H application processor, where the system is configured to execute the method for starting the D1-H application processor described in the foregoing embodiment, as shown in fig. 3, and the system includes:

a cure guidance module 201 for running an internal cure guidance program;

the SPL module 202 is configured to run a SPL program in the on-chip SDRAM;

the application module 203 is configured to run an application in the DDR until the D1-H startup is completed.

The starting system of the D1-H application processor provided in the above embodiment of the present application and the starting method of the D1-H application processor provided in the embodiment of the present application have the same beneficial effects as the method adopted, operated or implemented by the application program stored therein, because of the same inventive concept.

The embodiment of the application also provides an electronic device corresponding to the starting method of the D1-H application processor provided by the previous embodiment, so as to execute the starting method of the D1-H application processor. The embodiments of the present application are not limited.

Referring to fig. 4, a schematic diagram of an electronic device according to some embodiments of the present application is shown. As shown in fig. 4, the electronic device 20 includes: a processor 200, a memory 201, a bus 202 and a communication interface 203, the processor 200, the communication interface 203 and the memory 201 being connected by the bus 202; the memory 201 stores a computer program that can be executed on the processor 200, and when the processor 200 executes the computer program, the method for starting up the D1-H application processor provided in any of the foregoing embodiments of the present application is executed.

The memory 201 may include a high-speed random access memory (RAM: random Access Memory), and may further include a non-volatile memory (non-volatile memory), such as at least one disk memory. The communication connection between the system network element and at least one other network element is implemented via at least one communication interface 203 (which may be wired or wireless), the internet, a wide area network, a local network, a metropolitan area network, etc. may be used.

Bus 202 may be an ISA bus, a PCI bus, an EISA bus, or the like. The buses may be classified as address buses, data buses, control buses, etc. The memory 201 is configured to store a program, and the processor 200 executes the program after receiving an execution instruction, and the method for starting up the D1-H application processor disclosed in any embodiment of the present application may be applied to the processor 200 or implemented by the processor 200.

The processor 200 may be an integrated circuit chip with signal processing capabilities. In implementation, the steps of the above method may be performed by integrated logic circuits of hardware in the processor 200 or by instructions in the form of software. The processor 200 may be a general-purpose processor, including a central processing unit (Central Processing Unit, CPU for short), a network processor (Network Processor, NP for short), etc.; but may also be a Digital Signal Processor (DSP), application Specific Integrated Circuit (ASIC), an off-the-shelf programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic device, discrete hardware components. The disclosed methods, steps, and logic blocks in the embodiments of the present application may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of a method disclosed in connection with the embodiments of the present application may be embodied directly in hardware, in a decoded processor, or in a combination of hardware and software modules in a decoded processor. The software modules may be located in a random access memory, flash memory, read only memory, programmable read only memory, or electrically erasable programmable memory, registers, etc. as well known in the art. The storage medium is located in the memory 201, and the processor 200 reads the information in the memory 201, and in combination with its hardware, performs the steps of the above method.

The electronic device provided by the embodiment of the application and the starting method of the D1-H application processor provided by the embodiment of the application have the same beneficial effects as the method adopted, operated or realized by the same invention conception.

The present embodiment also provides a computer readable storage medium corresponding to the method for starting the D1-H application processor provided in the foregoing embodiment, referring to fig. 5, the computer readable storage medium is shown as an optical disc 30, on which a computer program (i.e. a program product) is stored, where the computer program, when executed by the processor, performs the method for starting the D1-H application processor provided in any of the foregoing embodiments.

It should be noted that examples of the computer readable storage medium may also include, but are not limited to, a phase change memory (PRAM), a Static Random Access Memory (SRAM), a Dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), a Read Only Memory (ROM), an Electrically Erasable Programmable Read Only Memory (EEPROM), a flash memory, or other optical or magnetic storage medium, which will not be described in detail herein.

The computer readable storage medium provided by the above embodiment of the present application and the method for starting the D1-H application processor provided by the embodiment of the present application are the same inventive concept, and have the same advantages as the method adopted, operated or implemented by the application program stored therein.

It should be noted that:

the algorithms and displays presented herein are not inherently related to any particular computer, virtual system, or other apparatus. Various general-purpose systems may also be used with the teachings herein. The required structure for a construction of such a system is apparent from the description above. In addition, the present application is not directed to any particular programming language. It will be appreciated that a variety of programming languages may be used to implement the teachings of the present application as described herein, and the above description of specific languages is provided for disclosure of preferred embodiments of the present application.

In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the present application may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.

Similarly, it should be appreciated that in the foregoing description of exemplary embodiments of the application, various features of the application are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the application and aiding in the understanding of one or more of the various inventive aspects. However, the disclosed method should not be construed as reflecting the intention that: i.e., the claimed application requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this application.

Those skilled in the art will appreciate that the modules in the apparatus of the embodiments may be adaptively changed and disposed in one or more apparatuses different from the embodiments. The modules or units or components of the embodiments may be combined into one module or unit or component and, furthermore, they may be divided into a plurality of sub-modules or sub-units or sub-components. Any combination of all features disclosed in this specification (including any accompanying claims, abstract and drawings), and all of the processes or units of any method or apparatus so disclosed, may be used in combination, except insofar as at least some of such features and/or processes or units are mutually exclusive. Each feature disclosed in this specification (including any accompanying claims, abstract and drawings), may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise.

Furthermore, those skilled in the art will appreciate that while some embodiments described herein include some features but not others included in other embodiments, combinations of features of different embodiments are meant to be within the scope of the present application and form different embodiments. For example, in the following claims, any of the claimed embodiments can be used in any combination.

Various component embodiments of the present application may be implemented in hardware, or in software modules running on one or more processors, or in a combination thereof. Those skilled in the art will appreciate that some or all of the functions of some or all of the components in a virtual machine creation system according to embodiments of the present application may be implemented in practice using a microprocessor or Digital Signal Processor (DSP). The present application may also be embodied as a device or system program (e.g., a computer program and a computer program product) for performing a portion or all of the methods described herein. Such a program embodying the present application may be stored on a computer readable medium, or may have the form of one or more signals. Such signals may be downloaded from an internet website, provided on a carrier signal, or provided in any other form.

It should be noted that the above-mentioned embodiments illustrate rather than limit the application, and that those skilled in the art will be able to design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The application may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware. The use of the words first, second, third, etc. do not denote any order. These words may be interpreted as names.

The foregoing is merely specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think of various changes or substitutions within the technical scope of the present application, and these should be covered in the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A method for starting a D1-H application processor, comprising:

running an internal cure boot program;

running SPL programs in the on-chip SDRAM;

2. The method of claim 1, wherein the step of determining the position of the substrate comprises,

the running an internal cure boot program includes:

3. The method of claim 2, wherein the step of determining the position of the substrate comprises,

the external nonvolatile memory includes: dMMC/SD card, nand Flash, nor Flash.

4. The method of claim 2, wherein the step of determining the position of the substrate comprises,

if the next stage is not found, the forced burning mode is entered, and the idle level of the FEL pin is high.

5. The method according to any one of claim 1 to 4, wherein,

the running SPL program in the on-chip SDRAM includes:

6. The method of claim 5, wherein the step of determining the position of the probe is performed,

the first 48 bytes of the SPL program are guide heads, wherein a checksum field is filled through a checksum tool, and the checksum tool accumulates every 4 bytes according to a bin file of the SPL program to obtain a checksum, and the initial value of the checksum field is 0x5F0A6C39; SPL code length field information is obtained through a link script;

the method for setting the guide head comprises the following steps of firstly setting the guide head at the beginning of a starting file according to preset information; secondly, linking the starting file to the forefront in the linking file; finally, filling of the checksum field is completed in the Makefile using a checksum tool.

7. The method of claim 6, wherein the step of providing the first layer comprises,

and the BROM checks the checksum field in the guide head, copies the SPL program with the corresponding size to the internal SDRAM of the chip according to the SPL code length field in the guide head after the checksum is passed, and then runs the SPL program.

8. A system for starting a D1-H application processor, comprising:

the SPL module is used for running the SPL program in the on-chip SDRAM;

9. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor runs the computer program to implement the method of any one of claims 1-7.

10. A computer readable storage medium having stored thereon a computer program, wherein the program is executed by a processor to implement the method of any of claims 1-7.