CN112242487A - Gate tube with quasi-superlattice structure and preparation method thereof - Google Patents
Gate tube with quasi-superlattice structure and preparation method thereof Download PDFInfo
- Publication number
- CN112242487A CN112242487A CN202011100542.8A CN202011100542A CN112242487A CN 112242487 A CN112242487 A CN 112242487A CN 202011100542 A CN202011100542 A CN 202011100542A CN 112242487 A CN112242487 A CN 112242487A
- Authority
- CN
- China
- Prior art keywords
- layer
- sub
- metal electrode
- superlattice
- layers
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
- H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
- H10N70/257—Multistable switching devices, e.g. memristors based on radiation or particle beam assisted switching, e.g. optically controlled devices
Abstract
The invention discloses a gate tube with a superlattice-like structure and a preparation method thereof, and belongs to the technical field of micro-nano electronics. The gate tube comprises a substrate, and a first metal electrode layer, a super-lattice-like layer and a second metal electrode layer which are sequentially stacked on the substrate, wherein the super-lattice-like layer comprises n +1 first sub-layers and n second sub-layers which are periodically and alternately stacked, the material of the first sub-layer comprises GeS or GeSe, and the material of the second sub-layer comprises one of GeTe, ZnTe, AlTe, SiTe, BTe or CTe. Since both the GeS and GeSe materials have high stability, the diffusion separation of Te in the material of the second sublayer due to high temperature can be prevented. Meanwhile, each sublayer of the quasi-superlattice structure is very thin, the coupling between adjacent wells is very strong, periodic quantum potential wells are formed in the quasi-superlattice layer, and the original discrete energy levels in each quantum well are expanded into energy bands, so that the band gap width can be reduced, the power consumption is reduced, and the quasi-superlattice structure is better integrated with a storage device unit.
Description
Technical Field
The invention relates to the technical field of micro-nano electronics, in particular to a gate tube with a superlattice-like structure and a preparation method thereof.
Background
With the vigorous development of the industries of big data, cloud computing and internet of things, along with the explosive growth of mass information and the constantly expanding market demand, the high-efficiency storage and convenient transmission of data are the strict requirements of the storage technology in the modern times, and various novel high-performance storage technologies are also produced. The phase change memory technology has the characteristics of relatively mature material system, simple preparation process, good compatibility with CMOS, high device reliability, superiority in speed and service life and the like, and is generally accepted in the industry.
The phase change memory has a leakage current problem, and the gate current may flow through the peripheral cells to affect the reliability of the device, so each memory cell must be connected with a gate tube. Since the phase change material is transformed from the crystalline state to the amorphous state by heating the gate tube to a certain temperature with a sufficient Reset current, the gate tube is also a critical factor for realizing high-density storage of phase change access.
At present, typical materials used as the gate tube are sulfur compounds, and commonly used materials are GeS, GeSe, and GeTe. The S atoms and the Se atoms in the GeS and the GeSe have smaller radiuses and are more stable in bonding with Ge, so that the GeS and the GeSe have good temperature thermal stability and are easy to form stable lattice orientation; however, the GeS mobility band gap is relatively wide, so that the threshold voltage of the GeS mobility band gap is relatively large. The radius of Te atoms in the GeTe material is larger, so that the mobility band gap of the GeTe is smaller, and the GeTe material has lower threshold voltage; but are less thermally stable at temperatures than GeS and GeSe. Therefore, the material has poor comprehensive performance and is difficult to meet the requirement of a high-performance gate tube.
Disclosure of Invention
In order to meet the requirement of a high-performance gate tube, the embodiment of the invention provides a gate tube with a superlattice-like structure and a preparation method thereof. The technical scheme is as follows:
in one aspect, an embodiment of the present invention provides a gate tube having a superlattice-like structure, where the gate tube includes a substrate, and a first metal electrode layer, a superlattice-like layer, and a second metal electrode layer sequentially stacked on the substrate, the superlattice-like layer includes n +1 first sublayers and n second sublayers that are periodically and alternately stacked, the first sublayers are made of GeS or GeSe, and the second sublayers are made of one of GeTe, ZnTe, AlTe, SiTe, BTe, or CTe.
Optionally, the thickness of the first sub-layer is 2-15 nm, and the thickness of the second sub-layer is 2-10 nm.
Optionally, the number n of the alternating lamination periods of the first sub-layer and the second sub-layer is 5-20.
Optionally, the first metal electrode layer and the second metal electrode layer are both inert metal electrode layers.
Optionally, the material of the inert metal electrode layer includes: at least one of Pt, Ti, W, Au, Ru, Al, TiW, TiN, TaN, IrO2, ITO and IZO, or an alloy material formed by combining any two or more of Pt, Ti, W, Au, Ru, Al, TiW, TiN, TaN, IrO2, ITO and IZO.
On the other hand, the embodiment of the invention also provides a preparation method of the gate tube with the superlattice-like structure, which comprises the following steps:
providing a substrate;
preparing a first metal electrode layer on the substrate;
preparing a superlattice-like layer on the first metal electrode layer, wherein the superlattice-like layer comprises n +1 first sub-layers and n second sub-layers which are periodically and alternately stacked, the first sub-layers are made of GeS or GeSe, and the second sub-layers are made of one of GeTe, ZnTe, AlTe, SiTe, BTe or CTe;
and preparing a second metal electrode layer on the superlattice-like layer.
Optionally, preparing a superlattice-like layer on the first metal electrode layer includes:
and sequentially depositing the first sub-layer and the second sub-layer on the first metal electrode layer until the alternating lamination cycle number n is completed.
Optionally, the number n of the alternating lamination periods of the first sub-layer and the second sub-layer is 5-20.
Optionally, the thickness of the first sub-layer is 2-15 nm, and the thickness of the second sub-layer is 2-10 nm.
Optionally, the depositing comprises using physical vapor deposition, chemical vapor deposition, molecular beam epitaxy, atomic layer deposition, or metal organic deposition.
The technical scheme provided by the embodiment of the invention has the beneficial effects that at least:
the gate tube comprises a substrate, and a first metal electrode layer, a super-lattice-like layer and a second metal electrode layer which are sequentially stacked on the substrate, wherein the super-lattice-like layer comprises n +1 first sub-layers and n second sub-layers which are periodically and alternately stacked, the first sub-layers are made of GeS or GeSe, and the second sub-layers are made of one of GeTe, ZnTe, AlTe, SiTe, BTe or CTe. Because both the GeS material and the GeSe material have higher stability, the GeS material and the GeSe material are prepared into a structure which is in contact with the first metal electrode layer and the second metal electrode layer, so that Te in the material of the second sub-layer can be prevented from being diffused and separated due to high temperature, and the thermal stability of the gate tube with the similar superlattice structure is improved compared with the gate tube made of the material of the pure second sub-layer. Meanwhile, each sublayer of the quasi-superlattice structure is thin, the coupling between adjacent wells is strong, periodic quantum potential wells are formed in the quasi-superlattice layer, the original discrete energy levels in each quantum well are expanded into energy bands, the band gap width can be reduced, namely the quasi-superlattice with the same thickness has lower threshold voltage than a gate tube made of a pure first sublayer material, the power consumption can be reduced, and the quasi-superlattice structure can be better integrated with a storage device unit.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a gate tube having a superlattice-like structure according to an embodiment of the present invention;
fig. 2 is a flowchart of a method for manufacturing a gate tube having a superlattice-like structure according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
An embodiment of the present invention provides a gate tube having a superlattice-like structure, and fig. 1 is a schematic structural diagram of the gate tube having the superlattice-like structure according to the embodiment of the present invention, as shown in fig. 1.
A gate tube with a superlattice-like structure comprises a substrate 110, a first metal electrode layer 120, a superlattice-like layer 130 and a second metal electrode layer 140 which are sequentially stacked on the substrate 110, wherein the superlattice-like layer 130 comprises n +1 first sub-layers 131 and n second sub-layers 132 which are periodically and alternately stacked, the first sub-layers 131 are made of GeS or GeSe, and the second sub-layers 132 are made of one of GeTe, ZnTe, AlTe, SiTe, BTe or CTe.
In some implementations, the chemical formula of the material of the first sub-layer 131 may be (Ge)xS1-x)1-yMyOr (Ge)xSe1-x)1-zMzWherein, M is a doping material, x is more than or equal to 0.3 and less than or equal to 0.6, y is more than or equal to 0 and less than or equal to 0.5, and z is more than or equal to 0 and less than or equal to 0.5.
The values of y and z in the chemical general formula of the material of the first sublayer 131 may be 0, that is, the material of the first sublayer 131 does not contain a doping material, and the material of the first sublayer 131 is a compound including only GeS or a compound including only GeSe, and when the material of the first sublayer 131 is used for a gate transistor unit, the material has the advantages of large on-current, small leakage current, large gate ratio, good thermal stability, simple material, no toxicity, and the like.
The values of y and z in the chemical general formula of the material of the first sub-layer 131 may be different from zero, that is, the material of the first sub-layer 131 contains a doping material, and at this time, y is greater than 0 and less than or equal to 0.5 or z is greater than 0 and less than or equal to 0.5, that is, the atomic percentage of the doping material in the material of the first sub-layer 131 is less than or equal to 50%.
In an example, the doping material may include a metal or a metal compoundPreferably, the doping material may include at least one of Sc (scandium), Ti (titanium), V (vanadium), Cr (chromium), Mn (manganese), Fe (iron), Co (cobalt), Ni (nickel), Cu (copper), Zn (zinc), Al (aluminum), Y (yttrium), Zr (zirconium), Nb (niobium), Mo (molybdenum), Tc (technetium), Ru (ruthenium), Rh (rhodium), Pd (palladium), Ag (silver), Cd (cadmium), In (indium), Hf (hafnium), Ta (tantalum), and W (tungsten), that is, the dopant material may comprise Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Al, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, In, Hf, Ta, or W, and may also comprise any combination of at least two of Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Al, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, In, Hf, Ta, and W. By applying at GexS1-xOr GexSe1-xAt least one of Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Al, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, In, Hf, Ta and W is doped into the material to be used as a doping material, so that the threshold voltage, the turn-on current, the fatigue property and other properties of the gate tube unit made of the gate material can be adjusted and optimized, and the gate tube unit made of the material of the first sublayer 131 In the example is compared with Ge without the doping materialxS1-xOr GexSe1-xThe gating tube unit prepared by the gating material has the advantages of increased opening current, increased gating ratio and better cycle performance.
In another example, the dopant material may comprise a dielectric material, preferably, the dopant material comprises C, N, Si, SiO2, SiN, SiO, Si3N4, or SiC, and may also comprise a combination of two or more of C, N, Si, SiO2, SiN, SiO, Si3N4, and SiC. By applying at GexS1-xOr GexSe1-xAt least one of C, N, Si, SiO2, SiN, SiO, Si3N4 and SiC is doped into the material to serve as a doping material, so that the thermal stability of the gate tube unit made of the gate material can be improved, the leakage current of the gate tube unit made of the gate material is reduced, and the repeatability of the gate tube unit made of the gate tube material is enhanced; the material of the first sublayer 131 in this example produces a gate tube unit compared to Ge without doping materialxS1-xOr GexSe1-xGate tube made of gate materialThe unit leakage current is reduced, the gating ratio is increased, the thermal stability is improved, and the cycle performance is improved.
In the above example, the atomic percentage of the dopant material is 50% or less, regardless of whether the dopant material is selected to be C, N, Si, SiO2, SiN, SiO, Si3N4, or SiC, or selected to be one or more of C, N, Si, SiO2, SiN, SiO, Si3N4, and SiC.
Optionally, the thickness of the first sub-layer 131 is 2-15 nm, and the thickness of the second sub-layer 132 is 2-10 nm, so that the gate tube has suitable threshold voltage and thermal stability.
Optionally, the number n of the alternating lamination period of the first sub-layer 131 and the second sub-layer 132 is 5-20. Therefore, coupling between adjacent wells is stronger, and periodic quantum wells are formed in the superlattice-like layer 130, so that discrete energy levels in the quantum wells are expanded into energy bands, the band gap width is further reduced, the threshold voltage of a gate tube with the superlattice-like layer 130 is lower, power consumption can be reduced, and the superlattice-like layer can be better integrated with a storage device unit.
Optionally, the first metal electrode layer 120 and the second metal electrode layer 140 are both inert metal electrode layers. Because the inert metal is difficult to combine with other elements in the inert metal electrode layer, on one hand, active metal conductive particles in the superlattice-like layer 130 can be effectively prevented from diffusing into the electrode, and the cycle characteristic of the device is improved; on the other hand, the device failure caused by oxidation or corrosion of the inert metal electrode layer can be effectively prevented.
Preferably, the material of the inert metal electrode layer comprises: at least one of Pt, Ti, W, Au, Ru, Al, TiW, TiN, TaN, IrO2, ITO and IZO, or an alloy material formed by combining any two or more of Pt, Ti, W, Au, Ru, Al, TiW, TiN, TaN, IrO2, ITO and IZO.
An embodiment of the present invention provides a method for manufacturing a gate tube having a superlattice-like structure, and fig. 2 is a flowchart of the method for manufacturing a gate tube having a superlattice-like structure according to the embodiment of the present invention, as shown in fig. 2, the method includes:
providing a substrate;
preparing a first metal electrode layer on a substrate;
preparing a superlattice-like layer on the first metal electrode layer, wherein the superlattice-like layer comprises n +1 first sub-layers and n second sub-layers which are periodically and alternately stacked, the first sub-layers are made of GeS or GeSe, and the second sub-layers are made of one of GeTe, ZnTe, AlTe, SiTe, BTe and CTe;
and preparing a second metal electrode layer on the superlattice-like layer.
Specifically, the method may include:
s11: a substrate is provided.
In this embodiment, the substrate may be a semiconductor substrate. Specifically, the semiconductor substrate may be a silicon wafer having a crystal phase of <100> and a layer of silicon dioxide on the surface.
When the method is implemented, the substrate can be cleaned firstly, and the silicon wafer is placed in acetone and alcohol in sequence for ultrasonic washing for about ten minutes; and after the ultrasonic treatment is finished, a nitrogen gun is used for blowing and drying the residual liquid on the surface for later use. And growing a layer of compact silicon dioxide on the cleaned silicon wafer by using a plasma enhanced chemical vapor deposition method or atomic layer deposition.
S12: preparing a first metal electrode layer on a substrate;
specifically, the first metal electrode layer is an inert metal electrode layer, and the material of the inert metal electrode layer includes: at least one of Pt, Ti, W, Au, Ru, Al, TiW, TiN, TaN, IrO2, ITO and IZO, or an alloy material formed by combining any two or more of Pt, Ti, W, Au, Ru, Al, TiW, TiN, TaN, IrO2, ITO and IZO.
In implementation, a 100nm Pt metal layer can be formed on the substrate through magnetron sputtering to serve as the first metal electrode layer.
S13: depositing a super-lattice-like layer on the first metal electrode layer, wherein the super-lattice-like layer comprises n +1 first sub-layers and n second sub-layers which are periodically and alternately stacked, the first sub-layers are made of GeS or GeSe, and the second sub-layers are made of one of GeTe, ZnTe, AlTe, SiTe, BTe or CTe;
specifically, a first sublayer and a second sublayer are sequentially deposited on the first metal electrode layer until the number n of alternating lamination cycles is completed, wherein n is a positive integer. Wherein the depositing may include depositing the first sub-layer or the second sub-layer using physical vapor deposition, chemical vapor deposition, molecular beam epitaxy, atomic layer deposition, or metal organic deposition processes.
Preferably, the number n of the alternating lamination period of the first sublayer and the second sublayer in the superlattice-like layer is 5-20. The thickness of the first sub-layer is 2-15 nm, and the thickness of the second sub-layer is 2-10 nm.
In the implementation, a GeS material layer can be deposited on the first metal electrode layer to serve as a first sub-layer, and the thickness is 2 nm; then growing a layer of GeTe material as a second sublayer, wherein the thickness is 2 nm; and then alternately growing GeS material layers, GeTe material layers, … and GeS material layers to form the superlattice-like layer. The quasi-superlattice layer comprises n +1 GeS material layers and n GeTe material layers, namely the GeS material layers are in contact with the first metal electrode layer and the second metal electrode layer, so that the diffusion separation of Te in the material of the second sub-layer caused by high temperature is prevented, and the thermal stability of the gating tube with the quasi-superlattice structure is improved.
S14: and preparing a second metal electrode layer on the superlattice-like layer.
And preparing a second metal electrode layer on the superlattice-like layer. Specifically, the second metal electrode layer is an inert metal electrode layer, and the material of the inert metal electrode layer includes: at least one of Pt, Ti, W, Au, Ru, Al, TiW, TiN, TaN, IrO2, ITO and IZO, or an alloy material formed by combining any two or more of Pt, Ti, W, Au, Ru, Al, TiW, TiN, TaN, IrO2, ITO and IZO.
In implementation, a 100nm Pt metal layer can be formed on the superlattice-like layer through magnetron sputtering to serve as a second metal electrode layer.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (10)
1. The gate tube with the superlattice-like structure is characterized by comprising a substrate, and a first metal electrode layer, a superlattice-like layer and a second metal electrode layer which are sequentially stacked on the substrate, wherein the superlattice-like layer comprises n +1 first sub-layers and n second sub-layers which are periodically and alternately stacked, the first sub-layers are made of GeS or GeSe, and the second sub-layers are made of one of GeTe, ZnTe, AlTe, SiTe, BTe or CTe.
2. The gate pipe according to claim 1, wherein the thickness of the first sublayer is 2 to 15nm, and the thickness of the second sublayer is 2 to 10 nm.
3. The gate tube according to claim 1, wherein the number n of alternating lamination periods of the first sublayer and the second sublayer is 5-20.
4. A gate tube according to any one of claims 1-3, wherein the first metal electrode layer and the second metal electrode layer are both inert metal electrode layers.
5. The gate tube according to claim 4, wherein the material of the inert metal electrode layer comprises: at least one of Pt, Ti, W, Au, Ru, Al, TiW, TiN, TaN, IrO2, ITO and IZO, or an alloy material formed by combining any two or more of Pt, Ti, W, Au, Ru, Al, TiW, TiN, TaN, IrO2, ITO and IZO.
6. A preparation method of a gate tube with a superlattice-like structure is characterized by comprising the following steps:
providing a substrate;
preparing a first metal electrode layer on the substrate;
preparing a superlattice-like layer on the first metal electrode layer, wherein the superlattice-like layer comprises n +1 first sub-layers and n second sub-layers which are periodically and alternately stacked, the first sub-layers are made of GeS or GeSe, and the second sub-layers are made of one of GeTe, ZnTe, AlTe, SiTe, BTe or CTe;
and preparing a second metal electrode layer on the superlattice-like layer.
7. The method according to claim 6, wherein preparing a superlattice-like layer on the first metal electrode layer comprises:
and sequentially depositing the first sub-layer and the second sub-layer on the first metal electrode layer until the alternating lamination cycle number n is completed.
8. The method according to claim 7, wherein the number n of the alternating lamination period of the first and second sublayers is 5 to 20.
9. The method of claim 6, wherein the first sub-layer has a thickness of 2 to 15nm and the second sub-layer has a thickness of 2 to 10 nm.
10. The method of claim 7, wherein the depositing comprises physical vapor deposition, chemical vapor deposition, molecular beam epitaxy, atomic layer deposition, or metal organic deposition.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011100542.8A CN112242487B (en) | 2020-10-15 | 2020-10-15 | Gate tube with quasi-superlattice structure and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011100542.8A CN112242487B (en) | 2020-10-15 | 2020-10-15 | Gate tube with quasi-superlattice structure and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112242487A true CN112242487A (en) | 2021-01-19 |
| CN112242487B CN112242487B (en) | 2022-08-12 |
Family
ID=74169006
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011100542.8A Active CN112242487B (en) | 2020-10-15 | 2020-10-15 | Gate tube with quasi-superlattice structure and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112242487B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113113534A (en) * | 2021-03-19 | 2021-07-13 | 华为技术有限公司 | Gating material, gating device and memory |
| WO2023186093A1 (en) * | 2022-03-31 | 2023-10-05 | 华为技术有限公司 | Gating tube, preparation method for gating tube, and memory |
| WO2024021929A1 (en) * | 2022-07-28 | 2024-02-01 | 华为技术有限公司 | Selector and preparation method therefor |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104795494A (en) * | 2015-04-27 | 2015-07-22 | 江苏理工学院 | GeTe/Sb superlattice phase-change film material for high-speed phase change memories and preparation method of file material |
| CN106941129A (en) * | 2017-01-17 | 2017-07-11 | 杭州电子科技大学 | A kind of GeTe/Bi for low power consumption phase changing memory2Te3Superlattice structure storage medium |
| CN110571329A (en) * | 2019-08-16 | 2019-12-13 | 华中科技大学 | High-reliability phase-change material, phase-change memory and preparation method |
| CN110875069A (en) * | 2018-09-03 | 2020-03-10 | 三星电子株式会社 | Memory device |
| CN110931635A (en) * | 2019-10-28 | 2020-03-27 | 华中科技大学 | Low-density-change superlattice phase change film, phase change memory and preparation method of phase change film |
-
2020
- 2020-10-15 CN CN202011100542.8A patent/CN112242487B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104795494A (en) * | 2015-04-27 | 2015-07-22 | 江苏理工学院 | GeTe/Sb superlattice phase-change film material for high-speed phase change memories and preparation method of file material |
| CN106941129A (en) * | 2017-01-17 | 2017-07-11 | 杭州电子科技大学 | A kind of GeTe/Bi for low power consumption phase changing memory2Te3Superlattice structure storage medium |
| CN110875069A (en) * | 2018-09-03 | 2020-03-10 | 三星电子株式会社 | Memory device |
| CN110571329A (en) * | 2019-08-16 | 2019-12-13 | 华中科技大学 | High-reliability phase-change material, phase-change memory and preparation method |
| CN110931635A (en) * | 2019-10-28 | 2020-03-27 | 华中科技大学 | Low-density-change superlattice phase change film, phase change memory and preparation method of phase change film |
Non-Patent Citations (2)
| Title |
|---|
| ZEYU LI: "The electronic structure of GeSe monolayer with light nonmetallic elements decoration", 《SUPERLATTICES AND MICROSTRUCTURES》 * |
| 黄多辉: "GeTe和GeSe分子在外电场下的特性研究", 《物理学报》 * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113113534A (en) * | 2021-03-19 | 2021-07-13 | 华为技术有限公司 | Gating material, gating device and memory |
| WO2023186093A1 (en) * | 2022-03-31 | 2023-10-05 | 华为技术有限公司 | Gating tube, preparation method for gating tube, and memory |
| WO2024021929A1 (en) * | 2022-07-28 | 2024-02-01 | 华为技术有限公司 | Selector and preparation method therefor |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112242487B (en) | 2022-08-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN112242487B (en) | Gate tube with quasi-superlattice structure and preparation method thereof | |
| US11532709B2 (en) | Field effect transistor including channel formed of 2D material | |
| CN112652713A (en) | Gate tube with quasi-superlattice structure and preparation method thereof | |
| CN100500924C (en) | Method for preparing metal nano-crystal thin film | |
| JP2009530812A (en) | Preparation technology of precursor film and compound film for manufacturing thin film solar cell and apparatus corresponding thereto | |
| CN108493255B (en) | Two-dimensional material schottky diode with controllable electric field | |
| CN111463346B (en) | OTS gating material, OTS gating unit, preparation method of OTS gating unit and memory | |
| US20120325305A1 (en) | Ohmic contact between thin film solar cell and carbon-based transparent electrode | |
| CN108110026B (en) | Ge-Te-Al-As threshold switch material, threshold switch device unit and preparation method thereof | |
| CN110676376A (en) | Resistive random access memory based on two-dimensional MXene material and preparation method | |
| TW200913251A (en) | Phase change memory bridge cell | |
| CN102593350B (en) | Phase change memory cell and producing method thereof | |
| CN108428700B (en) | Preparation method of device with stable coexistence of memristor and negative differential effect at room temperature | |
| US20230081646A1 (en) | Multi bridge channel field effect transistor and method of fabricating the same | |
| CN101478030B (en) | Phase-change memory including interlayer and manufacturing process | |
| CN112820823A (en) | Multi-value phase change memory cell, phase change memory, electronic equipment and preparation method | |
| CN112909162A (en) | Phase change memory cell with superlattice buffer layer and preparation method | |
| WO2024021929A1 (en) | Selector and preparation method therefor | |
| JPH11224953A (en) | Photovolatic device and manufacture thereof | |
| CN114678468B (en) | Phase change memory and manufacturing method thereof | |
| CN220796755U (en) | Solar cell and photovoltaic module | |
| CN115915912A (en) | Heterojunction type threshold gating device and preparation method thereof | |
| CN101964351A (en) | Phase change memory using compound semiconductor-based Schottky barrier diode as switch and method | |
| CN102959735A (en) | Solar cell and method for manufacturing the same | |
| CN116709899A (en) | Tellurium-based threshold gating switching device and preparation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |